1 //===-- RegAllocBase.cpp - Register Allocator Base Class ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the RegAllocBase class which provides comon functionality
11 // for LiveIntervalUnion-based register allocators.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regalloc"
16 #include "RegAllocBase.h"
18 #include "VirtRegMap.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
21 #include "llvm/CodeGen/LiveRangeEdit.h"
22 #include "llvm/CodeGen/MachineInstr.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/Target/TargetMachine.h"
25 #include "llvm/Target/TargetRegisterInfo.h"
27 #include "llvm/ADT/SparseBitVector.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/raw_ostream.h"
33 #include "llvm/Support/Timer.h"
37 STATISTIC(NumAssigned , "Number of registers assigned");
38 STATISTIC(NumUnassigned , "Number of registers unassigned");
39 STATISTIC(NumNewQueued , "Number of new live ranges queued");
41 // Temporary verification option until we can put verification inside
43 static cl::opt<bool, true>
44 VerifyRegAlloc("verify-regalloc", cl::location(RegAllocBase::VerifyEnabled),
45 cl::desc("Verify during register allocation"));
47 const char *RegAllocBase::TimerGroupName = "Register Allocation";
48 bool RegAllocBase::VerifyEnabled = false;
51 // Verify each LiveIntervalUnion.
52 void RegAllocBase::verify() {
53 LiveVirtRegBitSet VisitedVRegs;
54 OwningArrayPtr<LiveVirtRegBitSet>
55 unionVRegs(new LiveVirtRegBitSet[TRI->getNumRegs()]);
57 // Verify disjoint unions.
58 for (unsigned PhysReg = 0, NumRegs = TRI->getNumRegs(); PhysReg != NumRegs;
60 DEBUG(PhysReg2LiveUnion[PhysReg].print(dbgs(), TRI));
61 LiveVirtRegBitSet &VRegs = unionVRegs[PhysReg];
62 PhysReg2LiveUnion[PhysReg].verify(VRegs);
63 // Union + intersection test could be done efficiently in one pass, but
64 // don't add a method to SparseBitVector unless we really need it.
65 assert(!VisitedVRegs.intersects(VRegs) && "vreg in multiple unions");
66 VisitedVRegs |= VRegs;
69 // Verify vreg coverage.
70 for (LiveIntervals::iterator liItr = LIS->begin(), liEnd = LIS->end();
71 liItr != liEnd; ++liItr) {
72 unsigned reg = liItr->first;
73 LiveInterval* li = liItr->second;
74 if (TargetRegisterInfo::isPhysicalRegister(reg)) continue;
75 if (!VRM->hasPhys(reg)) continue; // spilled?
76 if (li->empty()) continue; // unionVRegs will only be filled if li is
78 unsigned PhysReg = VRM->getPhys(reg);
79 if (!unionVRegs[PhysReg].test(reg)) {
80 dbgs() << "LiveVirtReg " << PrintReg(reg, TRI) << " not in union " <<
81 TRI->getName(PhysReg) << "\n";
82 llvm_unreachable("unallocated live vreg");
85 // FIXME: I'm not sure how to verify spilled intervals.
89 //===----------------------------------------------------------------------===//
90 // RegAllocBase Implementation
91 //===----------------------------------------------------------------------===//
93 void RegAllocBase::init(VirtRegMap &vrm, LiveIntervals &lis) {
94 NamedRegionTimer T("Initialize", TimerGroupName, TimePassesIsEnabled);
95 TRI = &vrm.getTargetRegInfo();
96 MRI = &vrm.getRegInfo();
99 MRI->freezeReservedRegs(vrm.getMachineFunction());
100 RegClassInfo.runOnMachineFunction(vrm.getMachineFunction());
102 const unsigned NumRegs = TRI->getNumRegs();
103 if (NumRegs != PhysReg2LiveUnion.size()) {
104 PhysReg2LiveUnion.init(UnionAllocator, NumRegs);
105 // Cache an interferece query for each physical reg
106 Queries.reset(new LiveIntervalUnion::Query[NumRegs]);
110 void RegAllocBase::releaseMemory() {
111 for (unsigned r = 0, e = PhysReg2LiveUnion.size(); r != e; ++r)
112 PhysReg2LiveUnion[r].clear();
115 // Visit all the live registers. If they are already assigned to a physical
116 // register, unify them with the corresponding LiveIntervalUnion, otherwise push
117 // them on the priority queue for later assignment.
118 void RegAllocBase::seedLiveRegs() {
119 NamedRegionTimer T("Seed Live Regs", TimerGroupName, TimePassesIsEnabled);
120 for (LiveIntervals::iterator I = LIS->begin(), E = LIS->end(); I != E; ++I) {
121 unsigned RegNum = I->first;
122 LiveInterval &VirtReg = *I->second;
123 if (TargetRegisterInfo::isPhysicalRegister(RegNum))
124 PhysReg2LiveUnion[RegNum].unify(VirtReg);
130 void RegAllocBase::assign(LiveInterval &VirtReg, unsigned PhysReg) {
131 DEBUG(dbgs() << "assigning " << PrintReg(VirtReg.reg, TRI)
132 << " to " << PrintReg(PhysReg, TRI) << '\n');
133 assert(!VRM->hasPhys(VirtReg.reg) && "Duplicate VirtReg assignment");
134 VRM->assignVirt2Phys(VirtReg.reg, PhysReg);
135 MRI->setPhysRegUsed(PhysReg);
136 PhysReg2LiveUnion[PhysReg].unify(VirtReg);
140 void RegAllocBase::unassign(LiveInterval &VirtReg, unsigned PhysReg) {
141 DEBUG(dbgs() << "unassigning " << PrintReg(VirtReg.reg, TRI)
142 << " from " << PrintReg(PhysReg, TRI) << '\n');
143 assert(VRM->getPhys(VirtReg.reg) == PhysReg && "Inconsistent unassign");
144 PhysReg2LiveUnion[PhysReg].extract(VirtReg);
145 VRM->clearVirt(VirtReg.reg);
149 // Top-level driver to manage the queue of unassigned VirtRegs and call the
150 // selectOrSplit implementation.
151 void RegAllocBase::allocatePhysRegs() {
154 // Continue assigning vregs one at a time to available physical registers.
155 while (LiveInterval *VirtReg = dequeue()) {
156 assert(!VRM->hasPhys(VirtReg->reg) && "Register already assigned");
158 // Unused registers can appear when the spiller coalesces snippets.
159 if (MRI->reg_nodbg_empty(VirtReg->reg)) {
160 DEBUG(dbgs() << "Dropping unused " << *VirtReg << '\n');
161 LIS->removeInterval(VirtReg->reg);
165 // Invalidate all interference queries, live ranges could have changed.
166 invalidateVirtRegs();
168 // selectOrSplit requests the allocator to return an available physical
169 // register if possible and populate a list of new live intervals that
170 // result from splitting.
171 DEBUG(dbgs() << "\nselectOrSplit "
172 << MRI->getRegClass(VirtReg->reg)->getName()
173 << ':' << PrintReg(VirtReg->reg) << ' ' << *VirtReg << '\n');
174 typedef SmallVector<LiveInterval*, 4> VirtRegVec;
175 VirtRegVec SplitVRegs;
176 unsigned AvailablePhysReg = selectOrSplit(*VirtReg, SplitVRegs);
178 if (AvailablePhysReg == ~0u) {
179 // selectOrSplit failed to find a register!
180 const char *Msg = "ran out of registers during register allocation";
181 // Probably caused by an inline asm.
183 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(VirtReg->reg);
184 (MI = I.skipInstruction());)
185 if (MI->isInlineAsm())
190 report_fatal_error(Msg);
191 // Keep going after reporting the error.
192 VRM->assignVirt2Phys(VirtReg->reg,
193 RegClassInfo.getOrder(MRI->getRegClass(VirtReg->reg)).front());
197 if (AvailablePhysReg)
198 assign(*VirtReg, AvailablePhysReg);
200 for (VirtRegVec::iterator I = SplitVRegs.begin(), E = SplitVRegs.end();
202 LiveInterval *SplitVirtReg = *I;
203 assert(!VRM->hasPhys(SplitVirtReg->reg) && "Register already assigned");
204 if (MRI->reg_nodbg_empty(SplitVirtReg->reg)) {
205 DEBUG(dbgs() << "not queueing unused " << *SplitVirtReg << '\n');
206 LIS->removeInterval(SplitVirtReg->reg);
209 DEBUG(dbgs() << "queuing new interval: " << *SplitVirtReg << "\n");
210 assert(TargetRegisterInfo::isVirtualRegister(SplitVirtReg->reg) &&
211 "expect split value in virtual register");
212 enqueue(SplitVirtReg);
218 // Check if this live virtual register interferes with a physical register. If
219 // not, then check for interference on each register that aliases with the
220 // physical register. Return the interfering register.
221 unsigned RegAllocBase::checkPhysRegInterference(LiveInterval &VirtReg,
223 for (MCRegAliasIterator AI(PhysReg, TRI, true); AI.isValid(); ++AI)
224 if (query(VirtReg, *AI).checkInterference())