1 //===-- PhyRegAlloc.cpp ---------------------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Traditional graph-coloring global register allocator currently used
11 // by the SPARC back-end.
13 // NOTE: This register allocator has some special support
14 // for the Reoptimizer, such as not saving some registers on calls to
15 // the first-level instrumentation function.
17 // NOTE 2: This register allocator can save its state in a global
18 // variable in the module it's working on. This feature is not
19 // thread-safe; if you have doubts, leave it turned off.
21 //===----------------------------------------------------------------------===//
24 #include "PhyRegAlloc.h"
25 #include "RegAllocCommon.h"
27 #include "llvm/Constants.h"
28 #include "llvm/DerivedTypes.h"
29 #include "llvm/iOther.h"
30 #include "llvm/Module.h"
31 #include "llvm/Type.h"
32 #include "llvm/Analysis/LoopInfo.h"
33 #include "llvm/CodeGen/FunctionLiveVarInfo.h"
34 #include "llvm/CodeGen/InstrSelection.h"
35 #include "llvm/CodeGen/MachineFunction.h"
36 #include "llvm/CodeGen/MachineFunctionInfo.h"
37 #include "llvm/CodeGen/MachineInstr.h"
38 #include "llvm/CodeGen/MachineInstrBuilder.h"
39 #include "llvm/CodeGen/MachineInstrAnnot.h"
40 #include "llvm/CodeGen/Passes.h"
41 #include "llvm/Support/InstIterator.h"
42 #include "llvm/Target/TargetInstrInfo.h"
43 #include "Support/CommandLine.h"
44 #include "Support/SetOperations.h"
45 #include "Support/STLExtras.h"
48 RegAllocDebugLevel_t DEBUG_RA;
50 static cl::opt<RegAllocDebugLevel_t, true>
51 DRA_opt("dregalloc", cl::Hidden, cl::location(DEBUG_RA),
52 cl::desc("enable register allocation debugging information"),
54 clEnumValN(RA_DEBUG_None , "n", "disable debug output"),
55 clEnumValN(RA_DEBUG_Results, "y", "debug output for allocation results"),
56 clEnumValN(RA_DEBUG_Coloring, "c", "debug output for graph coloring step"),
57 clEnumValN(RA_DEBUG_Interference,"ig","debug output for interference graphs"),
58 clEnumValN(RA_DEBUG_LiveRanges , "lr","debug output for live ranges"),
59 clEnumValN(RA_DEBUG_Verbose, "v", "extra debug output"),
63 SaveRegAllocState("save-ra-state", cl::Hidden,
64 cl::desc("write reg. allocator state into module"));
66 FunctionPass *getRegisterAllocator(TargetMachine &T) {
67 return new PhyRegAlloc (T);
70 void PhyRegAlloc::getAnalysisUsage(AnalysisUsage &AU) const {
71 AU.addRequired<LoopInfo> ();
72 AU.addRequired<FunctionLiveVarInfo> ();
76 /// Initialize interference graphs (one in each reg class) and IGNodeLists
77 /// (one in each IG). The actual nodes will be pushed later.
79 void PhyRegAlloc::createIGNodeListsAndIGs() {
80 if (DEBUG_RA >= RA_DEBUG_LiveRanges) std::cerr << "Creating LR lists ...\n";
82 LiveRangeMapType::const_iterator HMI = LRI->getLiveRangeMap()->begin();
83 LiveRangeMapType::const_iterator HMIEnd = LRI->getLiveRangeMap()->end();
85 for (; HMI != HMIEnd ; ++HMI ) {
87 LiveRange *L = HMI->second; // get the LiveRange
90 std::cerr << "\n**** ?!?WARNING: NULL LIVE RANGE FOUND FOR: "
91 << RAV(HMI->first) << "****\n";
95 // if the Value * is not null, and LR is not yet written to the IGNodeList
96 if (!(L->getUserIGNode()) ) {
97 RegClass *const RC = // RegClass of first value in the LR
98 RegClassList[ L->getRegClassID() ];
99 RC->addLRToIG(L); // add this LR to an IG
105 for ( unsigned rc=0; rc < NumOfRegClasses ; rc++)
106 RegClassList[rc]->createInterferenceGraph();
108 if (DEBUG_RA >= RA_DEBUG_LiveRanges) std::cerr << "LRLists Created!\n";
112 /// Add all interferences for a given instruction. Interference occurs only
113 /// if the LR of Def (Inst or Arg) is of the same reg class as that of live
114 /// var. The live var passed to this function is the LVset AFTER the
117 void PhyRegAlloc::addInterference(const Value *Def, const ValueSet *LVSet,
119 ValueSet::const_iterator LIt = LVSet->begin();
121 // get the live range of instruction
122 const LiveRange *const LROfDef = LRI->getLiveRangeForValue( Def );
124 IGNode *const IGNodeOfDef = LROfDef->getUserIGNode();
125 assert( IGNodeOfDef );
127 RegClass *const RCOfDef = LROfDef->getRegClass();
129 // for each live var in live variable set
130 for ( ; LIt != LVSet->end(); ++LIt) {
132 if (DEBUG_RA >= RA_DEBUG_Verbose)
133 std::cerr << "< Def=" << RAV(Def) << ", Lvar=" << RAV(*LIt) << "> ";
135 // get the live range corresponding to live var
136 LiveRange *LROfVar = LRI->getLiveRangeForValue(*LIt);
138 // LROfVar can be null if it is a const since a const
139 // doesn't have a dominating def - see Assumptions above
141 if (LROfDef != LROfVar) // do not set interf for same LR
142 if (RCOfDef == LROfVar->getRegClass()) // 2 reg classes are the same
143 RCOfDef->setInterference( LROfDef, LROfVar);
148 /// For a call instruction, this method sets the CallInterference flag in
149 /// the LR of each variable live in the Live Variable Set live after the
150 /// call instruction (except the return value of the call instruction - since
151 /// the return value does not interfere with that call itself).
153 void PhyRegAlloc::setCallInterferences(const MachineInstr *MInst,
154 const ValueSet *LVSetAft) {
155 if (DEBUG_RA >= RA_DEBUG_Interference)
156 std::cerr << "\n For call inst: " << *MInst;
158 // for each live var in live variable set after machine inst
159 for (ValueSet::const_iterator LIt = LVSetAft->begin(), LEnd = LVSetAft->end();
160 LIt != LEnd; ++LIt) {
162 // get the live range corresponding to live var
163 LiveRange *const LR = LRI->getLiveRangeForValue(*LIt );
165 // LR can be null if it is a const since a const
166 // doesn't have a dominating def - see Assumptions above
168 if (DEBUG_RA >= RA_DEBUG_Interference) {
169 std::cerr << "\n\tLR after Call: ";
172 LR->setCallInterference();
173 if (DEBUG_RA >= RA_DEBUG_Interference) {
174 std::cerr << "\n ++After adding call interference for LR: " ;
181 // Now find the LR of the return value of the call
182 // We do this because, we look at the LV set *after* the instruction
183 // to determine, which LRs must be saved across calls. The return value
184 // of the call is live in this set - but it does not interfere with call
185 // (i.e., we can allocate a volatile register to the return value)
186 CallArgsDescriptor* argDesc = CallArgsDescriptor::get(MInst);
188 if (const Value *RetVal = argDesc->getReturnValue()) {
189 LiveRange *RetValLR = LRI->getLiveRangeForValue( RetVal );
190 assert( RetValLR && "No LR for RetValue of call");
191 RetValLR->clearCallInterference();
194 // If the CALL is an indirect call, find the LR of the function pointer.
195 // That has a call interference because it conflicts with outgoing args.
196 if (const Value *AddrVal = argDesc->getIndirectFuncPtr()) {
197 LiveRange *AddrValLR = LRI->getLiveRangeForValue( AddrVal );
198 assert( AddrValLR && "No LR for indirect addr val of call");
199 AddrValLR->setCallInterference();
204 /// Create interferences in the IG of each RegClass, and calculate the spill
205 /// cost of each Live Range (it is done in this method to save another pass
208 void PhyRegAlloc::buildInterferenceGraphs() {
209 if (DEBUG_RA >= RA_DEBUG_Interference)
210 std::cerr << "Creating interference graphs ...\n";
212 unsigned BBLoopDepthCost;
213 for (MachineFunction::iterator BBI = MF->begin(), BBE = MF->end();
215 const MachineBasicBlock &MBB = *BBI;
216 const BasicBlock *BB = MBB.getBasicBlock();
218 // find the 10^(loop_depth) of this BB
219 BBLoopDepthCost = (unsigned)pow(10.0, LoopDepthCalc->getLoopDepth(BB));
221 // get the iterator for machine instructions
222 MachineBasicBlock::const_iterator MII = MBB.begin();
224 // iterate over all the machine instructions in BB
225 for ( ; MII != MBB.end(); ++MII) {
226 const MachineInstr *MInst = *MII;
228 // get the LV set after the instruction
229 const ValueSet &LVSetAI = LVI->getLiveVarSetAfterMInst(MInst, BB);
230 bool isCallInst = TM.getInstrInfo().isCall(MInst->getOpCode());
233 // set the isCallInterference flag of each live range which extends
234 // across this call instruction. This information is used by graph
235 // coloring algorithm to avoid allocating volatile colors to live ranges
236 // that span across calls (since they have to be saved/restored)
237 setCallInterferences(MInst, &LVSetAI);
240 // iterate over all MI operands to find defs
241 for (MachineInstr::const_val_op_iterator OpI = MInst->begin(),
242 OpE = MInst->end(); OpI != OpE; ++OpI) {
243 if (OpI.isDefOnly() || OpI.isDefAndUse()) // create a new LR since def
244 addInterference(*OpI, &LVSetAI, isCallInst);
246 // Calculate the spill cost of each live range
247 LiveRange *LR = LRI->getLiveRangeForValue(*OpI);
248 if (LR) LR->addSpillCost(BBLoopDepthCost);
251 // Mark all operands of pseudo-instructions as interfering with one
252 // another. This must be done because pseudo-instructions may be
253 // expanded to multiple instructions by the assembler, so all the
254 // operands must get distinct registers.
255 if (TM.getInstrInfo().isPseudoInstr(MInst->getOpCode()))
256 addInterf4PseudoInstr(MInst);
258 // Also add interference for any implicit definitions in a machine
259 // instr (currently, only calls have this).
260 unsigned NumOfImpRefs = MInst->getNumImplicitRefs();
261 for (unsigned z=0; z < NumOfImpRefs; z++)
262 if (MInst->getImplicitOp(z).opIsDefOnly() ||
263 MInst->getImplicitOp(z).opIsDefAndUse())
264 addInterference( MInst->getImplicitRef(z), &LVSetAI, isCallInst );
266 } // for all machine instructions in BB
267 } // for all BBs in function
269 // add interferences for function arguments. Since there are no explicit
270 // defs in the function for args, we have to add them manually
271 addInterferencesForArgs();
273 if (DEBUG_RA >= RA_DEBUG_Interference)
274 std::cerr << "Interference graphs calculated!\n";
278 /// Mark all operands of the given MachineInstr as interfering with one
281 void PhyRegAlloc::addInterf4PseudoInstr(const MachineInstr *MInst) {
282 bool setInterf = false;
284 // iterate over MI operands to find defs
285 for (MachineInstr::const_val_op_iterator It1 = MInst->begin(),
286 ItE = MInst->end(); It1 != ItE; ++It1) {
287 const LiveRange *LROfOp1 = LRI->getLiveRangeForValue(*It1);
288 assert((LROfOp1 || !It1.isUseOnly())&&"No LR for Def in PSEUDO insruction");
290 MachineInstr::const_val_op_iterator It2 = It1;
291 for (++It2; It2 != ItE; ++It2) {
292 const LiveRange *LROfOp2 = LRI->getLiveRangeForValue(*It2);
295 RegClass *RCOfOp1 = LROfOp1->getRegClass();
296 RegClass *RCOfOp2 = LROfOp2->getRegClass();
298 if (RCOfOp1 == RCOfOp2 ){
299 RCOfOp1->setInterference( LROfOp1, LROfOp2 );
303 } // for all other defs in machine instr
304 } // for all operands in an instruction
306 if (!setInterf && MInst->getNumOperands() > 2) {
307 std::cerr << "\nInterf not set for any operand in pseudo instr:\n";
309 assert(0 && "Interf not set for pseudo instr with > 2 operands" );
314 /// Add interferences for incoming arguments to a function.
316 void PhyRegAlloc::addInterferencesForArgs() {
317 // get the InSet of root BB
318 const ValueSet &InSet = LVI->getInSetOfBB(&Fn->front());
320 for (Function::const_aiterator AI = Fn->abegin(); AI != Fn->aend(); ++AI) {
321 // add interferences between args and LVars at start
322 addInterference(AI, &InSet, false);
324 if (DEBUG_RA >= RA_DEBUG_Interference)
325 std::cerr << " - %% adding interference for argument " << RAV(AI) << "\n";
330 /// The following are utility functions used solely by updateMachineCode and
331 /// the functions that it calls. They should probably be folded back into
332 /// updateMachineCode at some point.
335 // used by: updateMachineCode (1 time), PrependInstructions (1 time)
336 inline void InsertBefore(MachineInstr* newMI, MachineBasicBlock& MBB,
337 MachineBasicBlock::iterator& MII) {
338 MII = MBB.insert(MII, newMI);
342 // used by: AppendInstructions (1 time)
343 inline void InsertAfter(MachineInstr* newMI, MachineBasicBlock& MBB,
344 MachineBasicBlock::iterator& MII) {
345 ++MII; // insert before the next instruction
346 MII = MBB.insert(MII, newMI);
349 // used by: updateMachineCode (1 time)
350 inline void DeleteInstruction(MachineBasicBlock& MBB,
351 MachineBasicBlock::iterator& MII) {
352 MII = MBB.erase(MII);
355 // used by: updateMachineCode (1 time)
356 inline void SubstituteInPlace(MachineInstr* newMI, MachineBasicBlock& MBB,
357 MachineBasicBlock::iterator MII) {
361 // used by: updateMachineCode (2 times)
362 inline void PrependInstructions(std::vector<MachineInstr *> &IBef,
363 MachineBasicBlock& MBB,
364 MachineBasicBlock::iterator& MII,
365 const std::string& msg) {
367 MachineInstr* OrigMI = *MII;
368 std::vector<MachineInstr *>::iterator AdIt;
369 for (AdIt = IBef.begin(); AdIt != IBef.end() ; ++AdIt) {
371 if (OrigMI) std::cerr << "For MInst:\n " << *OrigMI;
372 std::cerr << msg << "PREPENDed instr:\n " << **AdIt << "\n";
374 InsertBefore(*AdIt, MBB, MII);
379 // used by: updateMachineCode (1 time)
380 inline void AppendInstructions(std::vector<MachineInstr *> &IAft,
381 MachineBasicBlock& MBB,
382 MachineBasicBlock::iterator& MII,
383 const std::string& msg) {
385 MachineInstr* OrigMI = *MII;
386 std::vector<MachineInstr *>::iterator AdIt;
387 for ( AdIt = IAft.begin(); AdIt != IAft.end() ; ++AdIt ) {
389 if (OrigMI) std::cerr << "For MInst:\n " << *OrigMI;
390 std::cerr << msg << "APPENDed instr:\n " << **AdIt << "\n";
392 InsertAfter(*AdIt, MBB, MII);
397 /// Set the registers for operands in the given MachineInstr, if a register was
398 /// successfully allocated. Return true if any of its operands has been marked
401 bool PhyRegAlloc::markAllocatedRegs(MachineInstr* MInst)
403 bool instrNeedsSpills = false;
405 // First, set the registers for operands in the machine instruction
406 // if a register was successfully allocated. Do this first because we
407 // will need to know which registers are already used by this instr'n.
408 for (unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
409 MachineOperand& Op = MInst->getOperand(OpNum);
410 if (Op.getType() == MachineOperand::MO_VirtualRegister ||
411 Op.getType() == MachineOperand::MO_CCRegister) {
412 const Value *const Val = Op.getVRegValue();
413 if (const LiveRange* LR = LRI->getLiveRangeForValue(Val)) {
414 // Remember if any operand needs spilling
415 instrNeedsSpills |= LR->isMarkedForSpill();
417 // An operand may have a color whether or not it needs spilling
419 MInst->SetRegForOperand(OpNum,
420 MRI.getUnifiedRegNum(LR->getRegClassID(),
424 } // for each operand
426 return instrNeedsSpills;
429 /// Mark allocated registers (using markAllocatedRegs()) on the instruction
430 /// that MII points to. Then, if it's a call instruction, insert caller-saving
431 /// code before and after it. Finally, insert spill code before and after it,
432 /// using insertCode4SpilledLR().
434 void PhyRegAlloc::updateInstruction(MachineBasicBlock::iterator& MII,
435 MachineBasicBlock &MBB) {
436 MachineInstr* MInst = *MII;
437 unsigned Opcode = MInst->getOpCode();
439 // Reset tmp stack positions so they can be reused for each machine instr.
440 MF->getInfo()->popAllTempValues();
442 // Mark the operands for which regs have been allocated.
443 bool instrNeedsSpills = markAllocatedRegs(*MII);
446 // Mark that the operands have been updated. Later,
447 // setRelRegsUsedByThisInst() is called to find registers used by each
448 // MachineInst, and it should not be used for an instruction until
449 // this is done. This flag just serves as a sanity check.
450 OperandsColoredMap[MInst] = true;
453 // Now insert caller-saving code before/after the call.
454 // Do this before inserting spill code since some registers must be
455 // used by save/restore and spill code should not use those registers.
456 if (TM.getInstrInfo().isCall(Opcode)) {
457 AddedInstrns &AI = AddedInstrMap[MInst];
458 insertCallerSavingCode(AI.InstrnsBefore, AI.InstrnsAfter, MInst,
459 MBB.getBasicBlock());
462 // Now insert spill code for remaining operands not allocated to
463 // registers. This must be done even for call return instructions
464 // since those are not handled by the special code above.
465 if (instrNeedsSpills)
466 for (unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
467 MachineOperand& Op = MInst->getOperand(OpNum);
468 if (Op.getType() == MachineOperand::MO_VirtualRegister ||
469 Op.getType() == MachineOperand::MO_CCRegister) {
470 const Value* Val = Op.getVRegValue();
471 if (const LiveRange *LR = LRI->getLiveRangeForValue(Val))
472 if (LR->isMarkedForSpill())
473 insertCode4SpilledLR(LR, MII, MBB, OpNum);
475 } // for each operand
478 /// Iterate over all the MachineBasicBlocks in the current function and set
479 /// the allocated registers for each instruction (using updateInstruction()),
480 /// after register allocation is complete. Then move code out of delay slots.
482 void PhyRegAlloc::updateMachineCode()
484 // Insert any instructions needed at method entry
485 MachineBasicBlock::iterator MII = MF->front().begin();
486 PrependInstructions(AddedInstrAtEntry.InstrnsBefore, MF->front(), MII,
487 "At function entry: \n");
488 assert(AddedInstrAtEntry.InstrnsAfter.empty() &&
489 "InstrsAfter should be unnecessary since we are just inserting at "
490 "the function entry point here.");
492 for (MachineFunction::iterator BBI = MF->begin(), BBE = MF->end();
494 MachineBasicBlock &MBB = *BBI;
496 // Iterate over all machine instructions in BB and mark operands with
497 // their assigned registers or insert spill code, as appropriate.
498 // Also, fix operands of call/return instructions.
499 for (MachineBasicBlock::iterator MII = MBB.begin(); MII != MBB.end(); ++MII)
500 if (! TM.getInstrInfo().isDummyPhiInstr((*MII)->getOpCode()))
501 updateInstruction(MII, MBB);
503 // Now, move code out of delay slots of branches and returns if needed.
504 // (Also, move "after" code from calls to the last delay slot instruction.)
505 // Moving code out of delay slots is needed in 2 situations:
506 // (1) If this is a branch and it needs instructions inserted after it,
507 // move any existing instructions out of the delay slot so that the
508 // instructions can go into the delay slot. This only supports the
509 // case that #instrsAfter <= #delay slots.
511 // (2) If any instruction in the delay slot needs
512 // instructions inserted, move it out of the delay slot and before the
513 // branch because putting code before or after it would be VERY BAD!
515 // If the annul bit of the branch is set, neither of these is legal!
516 // If so, we need to handle spill differently but annulling is not yet used.
517 for (MachineBasicBlock::iterator MII = MBB.begin();
518 MII != MBB.end(); ++MII)
519 if (unsigned delaySlots =
520 TM.getInstrInfo().getNumDelaySlots((*MII)->getOpCode())) {
521 MachineInstr *MInst = *MII, *DelaySlotMI = *(MII+1);
523 // Check the 2 conditions above:
524 // (1) Does a branch need instructions added after it?
525 // (2) O/w does delay slot instr. need instrns before or after?
526 bool isBranch = (TM.getInstrInfo().isBranch(MInst->getOpCode()) ||
527 TM.getInstrInfo().isReturn(MInst->getOpCode()));
528 bool cond1 = (isBranch &&
529 AddedInstrMap.count(MInst) &&
530 AddedInstrMap[MInst].InstrnsAfter.size() > 0);
531 bool cond2 = (AddedInstrMap.count(DelaySlotMI) &&
532 (AddedInstrMap[DelaySlotMI].InstrnsBefore.size() > 0 ||
533 AddedInstrMap[DelaySlotMI].InstrnsAfter.size() > 0));
535 if (cond1 || cond2) {
536 assert((MInst->getOpCodeFlags() & AnnulFlag) == 0 &&
537 "FIXME: Moving an annulled delay slot instruction!");
538 assert(delaySlots==1 &&
539 "InsertBefore does not yet handle >1 delay slots!");
540 InsertBefore(DelaySlotMI, MBB, MII); // MII pts back to branch
542 // In case (1), delete it and don't replace with anything!
543 // Otherwise (i.e., case (2) only) replace it with a NOP.
545 DeleteInstruction(MBB, ++MII); // MII now points to next inst.
546 --MII; // reset MII for ++MII of loop
549 SubstituteInPlace(BuildMI(TM.getInstrInfo().getNOPOpCode(),1),
550 MBB, MII+1); // replace with NOP
553 std::cerr << "\nRegAlloc: Moved instr. with added code: "
555 << " out of delay slots of instr: " << *MInst;
559 // For non-branch instr with delay slots (probably a call), move
560 // InstrAfter to the instr. in the last delay slot.
561 move2DelayedInstr(*MII, *(MII+delaySlots));
564 // Finally iterate over all instructions in BB and insert before/after
565 for (MachineBasicBlock::iterator MII=MBB.begin(); MII != MBB.end(); ++MII) {
566 MachineInstr *MInst = *MII;
568 // do not process Phis
569 if (TM.getInstrInfo().isDummyPhiInstr(MInst->getOpCode()))
572 // if there are any added instructions...
573 if (AddedInstrMap.count(MInst)) {
574 AddedInstrns &CallAI = AddedInstrMap[MInst];
577 bool isBranch = (TM.getInstrInfo().isBranch(MInst->getOpCode()) ||
578 TM.getInstrInfo().isReturn(MInst->getOpCode()));
580 AddedInstrMap[MInst].InstrnsAfter.size() <=
581 TM.getInstrInfo().getNumDelaySlots(MInst->getOpCode())) &&
582 "Cannot put more than #delaySlots instrns after "
583 "branch or return! Need to handle temps differently.");
587 // Temporary sanity checking code to detect whether the same machine
588 // instruction is ever inserted twice before/after a call.
589 // I suspect this is happening but am not sure. --Vikram, 7/1/03.
590 std::set<const MachineInstr*> instrsSeen;
591 for (int i = 0, N = CallAI.InstrnsBefore.size(); i < N; ++i) {
592 assert(instrsSeen.count(CallAI.InstrnsBefore[i]) == 0 &&
593 "Duplicate machine instruction in InstrnsBefore!");
594 instrsSeen.insert(CallAI.InstrnsBefore[i]);
596 for (int i = 0, N = CallAI.InstrnsAfter.size(); i < N; ++i) {
597 assert(instrsSeen.count(CallAI.InstrnsAfter[i]) == 0 &&
598 "Duplicate machine instruction in InstrnsBefore/After!");
599 instrsSeen.insert(CallAI.InstrnsAfter[i]);
603 // Now add the instructions before/after this MI.
604 // We do this here to ensure that spill for an instruction is inserted
605 // as close as possible to an instruction (see above insertCode4Spill)
606 if (! CallAI.InstrnsBefore.empty())
607 PrependInstructions(CallAI.InstrnsBefore, MBB, MII,"");
609 if (! CallAI.InstrnsAfter.empty())
610 AppendInstructions(CallAI.InstrnsAfter, MBB, MII,"");
612 } // if there are any added instructions
613 } // for each machine instruction
618 /// Insert spill code for AN operand whose LR was spilled. May be called
619 /// repeatedly for a single MachineInstr if it has many spilled operands. On
620 /// each call, it finds a register which is not live at that instruction and
621 /// also which is not used by other spilled operands of the same
622 /// instruction. Then it uses this register temporarily to accommodate the
625 void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
626 MachineBasicBlock::iterator& MII,
627 MachineBasicBlock &MBB,
628 const unsigned OpNum) {
629 MachineInstr *MInst = *MII;
630 const BasicBlock *BB = MBB.getBasicBlock();
632 assert((! TM.getInstrInfo().isCall(MInst->getOpCode()) || OpNum == 0) &&
633 "Outgoing arg of a call must be handled elsewhere (func arg ok)");
634 assert(! TM.getInstrInfo().isReturn(MInst->getOpCode()) &&
635 "Return value of a ret must be handled elsewhere");
637 MachineOperand& Op = MInst->getOperand(OpNum);
638 bool isDef = Op.opIsDefOnly();
639 bool isDefAndUse = Op.opIsDefAndUse();
640 unsigned RegType = MRI.getRegTypeForLR(LR);
641 int SpillOff = LR->getSpillOffFromFP();
642 RegClass *RC = LR->getRegClass();
644 // Get the live-variable set to find registers free before this instr.
645 const ValueSet &LVSetBef = LVI->getLiveVarSetBeforeMInst(MInst, BB);
648 // If this instr. is in the delay slot of a branch or return, we need to
649 // include all live variables before that branch or return -- we don't want to
650 // trample those! Verify that the set is included in the LV set before MInst.
651 if (MII != MBB.begin()) {
652 MachineInstr *PredMI = *(MII-1);
653 if (unsigned DS = TM.getInstrInfo().getNumDelaySlots(PredMI->getOpCode()))
654 assert(set_difference(LVI->getLiveVarSetBeforeMInst(PredMI), LVSetBef)
655 .empty() && "Live-var set before branch should be included in "
656 "live-var set of each delay slot instruction!");
660 MF->getInfo()->pushTempValue(MRI.getSpilledRegSize(RegType));
662 std::vector<MachineInstr*> MIBef, MIAft;
663 std::vector<MachineInstr*> AdIMid;
665 // Choose a register to hold the spilled value, if one was not preallocated.
666 // This may insert code before and after MInst to free up the value. If so,
667 // this code should be first/last in the spill sequence before/after MInst.
668 int TmpRegU=(LR->hasColor()
669 ? MRI.getUnifiedRegNum(LR->getRegClassID(),LR->getColor())
670 : getUsableUniRegAtMI(RegType, &LVSetBef, MInst, MIBef,MIAft));
672 // Set the operand first so that it this register does not get used
673 // as a scratch register for later calls to getUsableUniRegAtMI below
674 MInst->SetRegForOperand(OpNum, TmpRegU);
676 // get the added instructions for this instruction
677 AddedInstrns &AI = AddedInstrMap[MInst];
679 // We may need a scratch register to copy the spilled value to/from memory.
680 // This may itself have to insert code to free up a scratch register.
681 // Any such code should go before (after) the spill code for a load (store).
682 // The scratch reg is not marked as used because it is only used
683 // for the copy and not used across MInst.
684 int scratchRegType = -1;
686 if (MRI.regTypeNeedsScratchReg(RegType, scratchRegType)) {
687 scratchReg = getUsableUniRegAtMI(scratchRegType, &LVSetBef,
688 MInst, MIBef, MIAft);
689 assert(scratchReg != MRI.getInvalidRegNum());
692 if (!isDef || isDefAndUse) {
693 // for a USE, we have to load the value of LR from stack to a TmpReg
694 // and use the TmpReg as one operand of instruction
696 // actual loading instruction(s)
697 MRI.cpMem2RegMI(AdIMid, MRI.getFramePointer(), SpillOff, TmpRegU,
698 RegType, scratchReg);
700 // the actual load should be after the instructions to free up TmpRegU
701 MIBef.insert(MIBef.end(), AdIMid.begin(), AdIMid.end());
705 if (isDef || isDefAndUse) { // if this is a Def
706 // for a DEF, we have to store the value produced by this instruction
707 // on the stack position allocated for this LR
709 // actual storing instruction(s)
710 MRI.cpReg2MemMI(AdIMid, TmpRegU, MRI.getFramePointer(), SpillOff,
711 RegType, scratchReg);
713 MIAft.insert(MIAft.begin(), AdIMid.begin(), AdIMid.end());
716 // Finally, insert the entire spill code sequences before/after MInst
717 AI.InstrnsBefore.insert(AI.InstrnsBefore.end(), MIBef.begin(), MIBef.end());
718 AI.InstrnsAfter.insert(AI.InstrnsAfter.begin(), MIAft.begin(), MIAft.end());
721 std::cerr << "\nFor Inst:\n " << *MInst;
722 std::cerr << "SPILLED LR# " << LR->getUserIGNode()->getIndex();
723 std::cerr << "; added Instructions:";
724 for_each(MIBef.begin(), MIBef.end(), std::mem_fun(&MachineInstr::dump));
725 for_each(MIAft.begin(), MIAft.end(), std::mem_fun(&MachineInstr::dump));
730 /// Insert caller saving/restoring instructions before/after a call machine
731 /// instruction (before or after any other instructions that were inserted for
735 PhyRegAlloc::insertCallerSavingCode(std::vector<MachineInstr*> &instrnsBefore,
736 std::vector<MachineInstr*> &instrnsAfter,
737 MachineInstr *CallMI,
738 const BasicBlock *BB) {
739 assert(TM.getInstrInfo().isCall(CallMI->getOpCode()));
741 // hash set to record which registers were saved/restored
742 hash_set<unsigned> PushedRegSet;
744 CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
746 // if the call is to a instrumentation function, do not insert save and
747 // restore instructions the instrumentation function takes care of save
748 // restore for volatile regs.
750 // FIXME: this should be made general, not specific to the reoptimizer!
751 const Function *Callee = argDesc->getCallInst()->getCalledFunction();
752 bool isLLVMFirstTrigger = Callee && Callee->getName() == "llvm_first_trigger";
754 // Now check if the call has a return value (using argDesc) and if so,
755 // find the LR of the TmpInstruction representing the return value register.
756 // (using the last or second-last *implicit operand* of the call MI).
757 // Insert it to to the PushedRegSet since we must not save that register
758 // and restore it after the call.
759 // We do this because, we look at the LV set *after* the instruction
760 // to determine, which LRs must be saved across calls. The return value
761 // of the call is live in this set - but we must not save/restore it.
762 if (const Value *origRetVal = argDesc->getReturnValue()) {
763 unsigned retValRefNum = (CallMI->getNumImplicitRefs() -
764 (argDesc->getIndirectFuncPtr()? 1 : 2));
765 const TmpInstruction* tmpRetVal =
766 cast<TmpInstruction>(CallMI->getImplicitRef(retValRefNum));
767 assert(tmpRetVal->getOperand(0) == origRetVal &&
768 tmpRetVal->getType() == origRetVal->getType() &&
769 "Wrong implicit ref?");
770 LiveRange *RetValLR = LRI->getLiveRangeForValue(tmpRetVal);
771 assert(RetValLR && "No LR for RetValue of call");
773 if (! RetValLR->isMarkedForSpill())
774 PushedRegSet.insert(MRI.getUnifiedRegNum(RetValLR->getRegClassID(),
775 RetValLR->getColor()));
778 const ValueSet &LVSetAft = LVI->getLiveVarSetAfterMInst(CallMI, BB);
779 ValueSet::const_iterator LIt = LVSetAft.begin();
781 // for each live var in live variable set after machine inst
782 for( ; LIt != LVSetAft.end(); ++LIt) {
783 // get the live range corresponding to live var
784 LiveRange *const LR = LRI->getLiveRangeForValue(*LIt);
786 // LR can be null if it is a const since a const
787 // doesn't have a dominating def - see Assumptions above
789 if (! LR->isMarkedForSpill()) {
790 assert(LR->hasColor() && "LR is neither spilled nor colored?");
791 unsigned RCID = LR->getRegClassID();
792 unsigned Color = LR->getColor();
794 if (MRI.isRegVolatile(RCID, Color) ) {
795 // if this is a call to the first-level reoptimizer
796 // instrumentation entry point, and the register is not
797 // modified by call, don't save and restore it.
798 if (isLLVMFirstTrigger && !MRI.modifiedByCall(RCID, Color))
801 // if the value is in both LV sets (i.e., live before and after
802 // the call machine instruction)
803 unsigned Reg = MRI.getUnifiedRegNum(RCID, Color);
805 // if we haven't already pushed this register...
806 if( PushedRegSet.find(Reg) == PushedRegSet.end() ) {
807 unsigned RegType = MRI.getRegTypeForLR(LR);
809 // Now get two instructions - to push on stack and pop from stack
810 // and add them to InstrnsBefore and InstrnsAfter of the
813 MF->getInfo()->pushTempValue(MRI.getSpilledRegSize(RegType));
815 //---- Insert code for pushing the reg on stack ----------
817 std::vector<MachineInstr*> AdIBef, AdIAft;
819 // We may need a scratch register to copy the saved value
820 // to/from memory. This may itself have to insert code to
821 // free up a scratch register. Any such code should go before
822 // the save code. The scratch register, if any, is by default
823 // temporary and not "used" by the instruction unless the
824 // copy code itself decides to keep the value in the scratch reg.
825 int scratchRegType = -1;
827 if (MRI.regTypeNeedsScratchReg(RegType, scratchRegType))
828 { // Find a register not live in the LVSet before CallMI
829 const ValueSet &LVSetBef =
830 LVI->getLiveVarSetBeforeMInst(CallMI, BB);
831 scratchReg = getUsableUniRegAtMI(scratchRegType, &LVSetBef,
832 CallMI, AdIBef, AdIAft);
833 assert(scratchReg != MRI.getInvalidRegNum());
836 if (AdIBef.size() > 0)
837 instrnsBefore.insert(instrnsBefore.end(),
838 AdIBef.begin(), AdIBef.end());
840 MRI.cpReg2MemMI(instrnsBefore, Reg, MRI.getFramePointer(),
841 StackOff, RegType, scratchReg);
843 if (AdIAft.size() > 0)
844 instrnsBefore.insert(instrnsBefore.end(),
845 AdIAft.begin(), AdIAft.end());
847 //---- Insert code for popping the reg from the stack ----------
851 // We may need a scratch register to copy the saved value
852 // from memory. This may itself have to insert code to
853 // free up a scratch register. Any such code should go
854 // after the save code. As above, scratch is not marked "used".
857 if (MRI.regTypeNeedsScratchReg(RegType, scratchRegType))
858 { // Find a register not live in the LVSet after CallMI
859 scratchReg = getUsableUniRegAtMI(scratchRegType, &LVSetAft,
860 CallMI, AdIBef, AdIAft);
861 assert(scratchReg != MRI.getInvalidRegNum());
864 if (AdIBef.size() > 0)
865 instrnsAfter.insert(instrnsAfter.end(),
866 AdIBef.begin(), AdIBef.end());
868 MRI.cpMem2RegMI(instrnsAfter, MRI.getFramePointer(), StackOff,
869 Reg, RegType, scratchReg);
871 if (AdIAft.size() > 0)
872 instrnsAfter.insert(instrnsAfter.end(),
873 AdIAft.begin(), AdIAft.end());
875 PushedRegSet.insert(Reg);
878 std::cerr << "\nFor call inst:" << *CallMI;
879 std::cerr << " -inserted caller saving instrs: Before:\n\t ";
880 for_each(instrnsBefore.begin(), instrnsBefore.end(),
881 std::mem_fun(&MachineInstr::dump));
882 std::cerr << " -and After:\n\t ";
883 for_each(instrnsAfter.begin(), instrnsAfter.end(),
884 std::mem_fun(&MachineInstr::dump));
886 } // if not already pushed
887 } // if LR has a volatile color
889 } // if there is a LR for Var
890 } // for each value in the LV set after instruction
894 /// Returns the unified register number of a temporary register to be used
895 /// BEFORE MInst. If no register is available, it will pick one and modify
896 /// MIBef and MIAft to contain instructions used to free up this returned
899 int PhyRegAlloc::getUsableUniRegAtMI(const int RegType,
900 const ValueSet *LVSetBef,
902 std::vector<MachineInstr*>& MIBef,
903 std::vector<MachineInstr*>& MIAft) {
904 RegClass* RC = getRegClassByID(MRI.getRegClassIDOfRegType(RegType));
906 int RegU = getUnusedUniRegAtMI(RC, RegType, MInst, LVSetBef);
909 // we couldn't find an unused register. Generate code to free up a reg by
910 // saving it on stack and restoring after the instruction
912 int TmpOff = MF->getInfo()->pushTempValue(MRI.getSpilledRegSize(RegType));
914 RegU = getUniRegNotUsedByThisInst(RC, RegType, MInst);
916 // Check if we need a scratch register to copy this register to memory.
917 int scratchRegType = -1;
918 if (MRI.regTypeNeedsScratchReg(RegType, scratchRegType)) {
919 int scratchReg = getUsableUniRegAtMI(scratchRegType, LVSetBef,
920 MInst, MIBef, MIAft);
921 assert(scratchReg != MRI.getInvalidRegNum());
923 // We may as well hold the value in the scratch register instead
924 // of copying it to memory and back. But we have to mark the
925 // register as used by this instruction, so it does not get used
926 // as a scratch reg. by another operand or anyone else.
927 ScratchRegsUsed.insert(std::make_pair(MInst, scratchReg));
928 MRI.cpReg2RegMI(MIBef, RegU, scratchReg, RegType);
929 MRI.cpReg2RegMI(MIAft, scratchReg, RegU, RegType);
930 } else { // the register can be copied directly to/from memory so do it.
931 MRI.cpReg2MemMI(MIBef, RegU, MRI.getFramePointer(), TmpOff, RegType);
932 MRI.cpMem2RegMI(MIAft, MRI.getFramePointer(), TmpOff, RegU, RegType);
940 /// Returns the register-class register number of a new unused register that
941 /// can be used to accommodate a temporary value. May be called repeatedly
942 /// for a single MachineInstr. On each call, it finds a register which is not
943 /// live at that instruction and which is not used by any spilled operands of
944 /// that instruction.
946 int PhyRegAlloc::getUnusedUniRegAtMI(RegClass *RC, const int RegType,
947 const MachineInstr *MInst,
948 const ValueSet* LVSetBef) {
949 RC->clearColorsUsed(); // Reset array
951 if (LVSetBef == NULL) {
952 LVSetBef = &LVI->getLiveVarSetBeforeMInst(MInst);
953 assert(LVSetBef != NULL && "Unable to get live-var set before MInst?");
956 ValueSet::const_iterator LIt = LVSetBef->begin();
958 // for each live var in live variable set after machine inst
959 for ( ; LIt != LVSetBef->end(); ++LIt) {
960 // Get the live range corresponding to live var, and its RegClass
961 LiveRange *const LRofLV = LRI->getLiveRangeForValue(*LIt );
963 // LR can be null if it is a const since a const
964 // doesn't have a dominating def - see Assumptions above
965 if (LRofLV && LRofLV->getRegClass() == RC && LRofLV->hasColor())
966 RC->markColorsUsed(LRofLV->getColor(),
967 MRI.getRegTypeForLR(LRofLV), RegType);
970 // It is possible that one operand of this MInst was already spilled
971 // and it received some register temporarily. If that's the case,
972 // it is recorded in machine operand. We must skip such registers.
973 setRelRegsUsedByThisInst(RC, RegType, MInst);
975 int unusedReg = RC->getUnusedColor(RegType); // find first unused color
977 return MRI.getUnifiedRegNum(RC->getID(), unusedReg);
983 /// Return the unified register number of a register in class RC which is not
984 /// used by any operands of MInst.
986 int PhyRegAlloc::getUniRegNotUsedByThisInst(RegClass *RC,
988 const MachineInstr *MInst) {
989 RC->clearColorsUsed();
991 setRelRegsUsedByThisInst(RC, RegType, MInst);
993 // find the first unused color
994 int unusedReg = RC->getUnusedColor(RegType);
995 assert(unusedReg >= 0 &&
996 "FATAL: No free register could be found in reg class!!");
998 return MRI.getUnifiedRegNum(RC->getID(), unusedReg);
1002 /// Modify the IsColorUsedArr of register class RC, by setting the bits
1003 /// corresponding to register RegNo. This is a helper method of
1004 /// setRelRegsUsedByThisInst().
1006 static void markRegisterUsed(int RegNo, RegClass *RC, int RegType,
1007 const TargetRegInfo &TRI) {
1008 unsigned classId = 0;
1009 int classRegNum = TRI.getClassRegNum(RegNo, classId);
1010 if (RC->getID() == classId)
1011 RC->markColorsUsed(classRegNum, RegType, RegType);
1014 void PhyRegAlloc::setRelRegsUsedByThisInst(RegClass *RC, int RegType,
1015 const MachineInstr *MI) {
1016 assert(OperandsColoredMap[MI] == true &&
1017 "Illegal to call setRelRegsUsedByThisInst() until colored operands "
1018 "are marked for an instruction.");
1020 // Add the registers already marked as used by the instruction. Both
1021 // explicit and implicit operands are set.
1022 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
1023 if (MI->getOperand(i).hasAllocatedReg())
1024 markRegisterUsed(MI->getOperand(i).getAllocatedRegNum(), RC, RegType,MRI);
1026 for (unsigned i = 0, e = MI->getNumImplicitRefs(); i != e; ++i)
1027 if (MI->getImplicitOp(i).hasAllocatedReg())
1028 markRegisterUsed(MI->getImplicitOp(i).getAllocatedRegNum(), RC,
1031 // Add all of the scratch registers that are used to save values across the
1032 // instruction (e.g., for saving state register values).
1033 std::pair<ScratchRegsUsedTy::iterator, ScratchRegsUsedTy::iterator>
1034 IR = ScratchRegsUsed.equal_range(MI);
1035 for (ScratchRegsUsedTy::iterator I = IR.first; I != IR.second; ++I)
1036 markRegisterUsed(I->second, RC, RegType, MRI);
1038 // If there are implicit references, mark their allocated regs as well
1039 for (unsigned z=0; z < MI->getNumImplicitRefs(); z++)
1040 if (const LiveRange*
1041 LRofImpRef = LRI->getLiveRangeForValue(MI->getImplicitRef(z)))
1042 if (LRofImpRef->hasColor())
1043 // this implicit reference is in a LR that received a color
1044 RC->markColorsUsed(LRofImpRef->getColor(),
1045 MRI.getRegTypeForLR(LRofImpRef), RegType);
1049 /// If there are delay slots for an instruction, the instructions added after
1050 /// it must really go after the delayed instruction(s). So, we Move the
1051 /// InstrAfter of that instruction to the corresponding delayed instruction
1052 /// using the following method.
1054 void PhyRegAlloc::move2DelayedInstr(const MachineInstr *OrigMI,
1055 const MachineInstr *DelayedMI)
1057 // "added after" instructions of the original instr
1058 std::vector<MachineInstr *> &OrigAft = AddedInstrMap[OrigMI].InstrnsAfter;
1060 if (DEBUG_RA && OrigAft.size() > 0) {
1061 std::cerr << "\nRegAlloc: Moved InstrnsAfter for: " << *OrigMI;
1062 std::cerr << " to last delay slot instrn: " << *DelayedMI;
1065 // "added after" instructions of the delayed instr
1066 std::vector<MachineInstr *> &DelayedAft=AddedInstrMap[DelayedMI].InstrnsAfter;
1068 // go thru all the "added after instructions" of the original instruction
1069 // and append them to the "added after instructions" of the delayed
1071 DelayedAft.insert(DelayedAft.end(), OrigAft.begin(), OrigAft.end());
1073 // empty the "added after instructions" of the original instruction
1078 void PhyRegAlloc::colorIncomingArgs()
1080 MRI.colorMethodArgs(Fn, *LRI, AddedInstrAtEntry.InstrnsBefore,
1081 AddedInstrAtEntry.InstrnsAfter);
1085 /// Determine whether the suggested color of each live range is really usable,
1086 /// and then call its setSuggestedColorUsable() method to record the answer. A
1087 /// suggested color is NOT usable when the suggested color is volatile AND
1088 /// when there are call interferences.
1090 void PhyRegAlloc::markUnusableSugColors()
1092 LiveRangeMapType::const_iterator HMI = (LRI->getLiveRangeMap())->begin();
1093 LiveRangeMapType::const_iterator HMIEnd = (LRI->getLiveRangeMap())->end();
1095 for (; HMI != HMIEnd ; ++HMI ) {
1097 LiveRange *L = HMI->second; // get the LiveRange
1098 if (L && L->hasSuggestedColor ())
1099 L->setSuggestedColorUsable
1100 (!(MRI.isRegVolatile (L->getRegClassID (), L->getSuggestedColor ())
1101 && L->isCallInterference ()));
1103 } // for all LR's in hash map
1107 /// For each live range that is spilled, allocates a new spill position on the
1108 /// stack, and set the stack offsets of the live range that will be spilled to
1109 /// that position. This must be called just after coloring the LRs.
1111 void PhyRegAlloc::allocateStackSpace4SpilledLRs() {
1112 if (DEBUG_RA) std::cerr << "\nSetting LR stack offsets for spills...\n";
1114 LiveRangeMapType::const_iterator HMI = LRI->getLiveRangeMap()->begin();
1115 LiveRangeMapType::const_iterator HMIEnd = LRI->getLiveRangeMap()->end();
1117 for ( ; HMI != HMIEnd ; ++HMI) {
1118 if (HMI->first && HMI->second) {
1119 LiveRange *L = HMI->second; // get the LiveRange
1120 if (L->isMarkedForSpill()) { // NOTE: allocating size of long Type **
1121 int stackOffset = MF->getInfo()->allocateSpilledValue(Type::LongTy);
1122 L->setSpillOffFromFP(stackOffset);
1124 std::cerr << " LR# " << L->getUserIGNode()->getIndex()
1125 << ": stack-offset = " << stackOffset << "\n";
1128 } // for all LR's in hash map
1133 /// AllocInfo - Structure representing one instruction's
1134 /// operand's-worth of register allocation state. We create tables
1135 /// made out of these data structures to generate mapping information
1136 /// for this register allocator. (FIXME: This might move to a header
1137 /// file at some point.)
1140 unsigned Instruction;
1142 unsigned AllocState;
1144 AllocInfo (unsigned Instruction_, unsigned Operand_,
1145 unsigned AllocState_, int Placement_) :
1146 Instruction (Instruction_), Operand (Operand_),
1147 AllocState (AllocState_), Placement (Placement_) { }
1148 /// getConstantType - Return a StructType representing an AllocInfo
1151 static StructType *getConstantType () {
1152 std::vector<const Type *> TV;
1153 TV.push_back (Type::UIntTy);
1154 TV.push_back (Type::UIntTy);
1155 TV.push_back (Type::UIntTy);
1156 TV.push_back (Type::IntTy);
1157 return StructType::get (TV);
1159 /// toConstant - Convert this AllocInfo into an LLVM Constant of type
1160 /// getConstantType(), and return the Constant.
1162 Constant *toConstant () const {
1163 StructType *ST = getConstantType ();
1164 std::vector<Constant *> CV;
1165 CV.push_back (ConstantUInt::get (Type::UIntTy, Instruction));
1166 CV.push_back (ConstantUInt::get (Type::UIntTy, Operand));
1167 CV.push_back (ConstantUInt::get (Type::UIntTy, AllocState));
1168 CV.push_back (ConstantSInt::get (Type::IntTy, Placement));
1169 return ConstantStruct::get (ST, CV);
1174 /// Save the global register allocation decisions made by the register
1175 /// allocator so that they can be accessed later (sort of like "poor man's
1178 void PhyRegAlloc::saveState () {
1179 std::vector<Constant *> &state = FnAllocState[Fn];
1181 LiveRangeMapType::const_iterator HMIEnd = LRI->getLiveRangeMap ()->end ();
1182 for (const_inst_iterator II=inst_begin (Fn), IE=inst_end (Fn); II != IE; ++II)
1183 for (unsigned i = 0; i < (*II)->getNumOperands (); ++i) {
1184 const Value *V = (*II)->getOperand (i);
1185 // Don't worry about it unless it's something whose reg. we'll need.
1186 if (!isa<Argument> (V) && !isa<Instruction> (V))
1188 LiveRangeMapType::const_iterator HMI = LRI->getLiveRangeMap ()->find (V);
1189 static const unsigned NotAllocated = 0, Allocated = 1, Spilled = 2;
1190 unsigned AllocState = NotAllocated;
1192 if ((HMI != HMIEnd) && HMI->second) {
1193 LiveRange *L = HMI->second;
1194 assert ((L->hasColor () || L->isMarkedForSpill ())
1195 && "Live range exists but not colored or spilled");
1196 if (L->hasColor()) {
1197 AllocState = Allocated;
1198 Placement = MRI.getUnifiedRegNum (L->getRegClassID (),
1200 } else if (L->isMarkedForSpill ()) {
1201 AllocState = Spilled;
1202 assert (L->hasSpillOffset ()
1203 && "Live range marked for spill but has no spill offset");
1204 Placement = L->getSpillOffFromFP ();
1207 state.push_back (AllocInfo (Insn, i, AllocState,
1208 Placement).toConstant ());
1212 /// Check the saved state filled in by saveState(), and abort if it looks
1213 /// wrong. Only used when debugging.
1215 void PhyRegAlloc::verifySavedState () {
1216 /// not yet implemented
1219 bool PhyRegAlloc::doFinalization (Module &M) {
1220 if (!SaveRegAllocState)
1221 return false; // Nothing to do here, unless we're saving state.
1223 // Convert FnAllocState to a single Constant array and add it
1225 ArrayType *AT = ArrayType::get (AllocInfo::getConstantType (), 0);
1226 std::vector<const Type *> TV;
1227 TV.push_back (Type::UIntTy);
1229 PointerType *PT = PointerType::get (StructType::get (TV));
1231 std::vector<Constant *> allstate;
1232 for (Module::iterator I = M.begin (), E = M.end (); I != E; ++I) {
1234 if (FnAllocState.find (F) == FnAllocState.end ()) {
1235 allstate.push_back (ConstantPointerNull::get (PT));
1237 std::vector<Constant *> &state = FnAllocState[F];
1239 // Convert state into an LLVM ConstantArray, and put it in a
1240 // ConstantStruct (named S) along with its size.
1241 unsigned Size = state.size ();
1242 ArrayType *AT = ArrayType::get (AllocInfo::getConstantType (), Size);
1243 std::vector<const Type *> TV;
1244 TV.push_back (Type::UIntTy);
1246 StructType *ST = StructType::get (TV);
1247 std::vector<Constant *> CV;
1248 CV.push_back (ConstantUInt::get (Type::UIntTy, Size));
1249 CV.push_back (ConstantArray::get (AT, state));
1250 Constant *S = ConstantStruct::get (ST, CV);
1252 GlobalVariable *GV =
1253 new GlobalVariable (ST, true,
1254 GlobalValue::InternalLinkage, S,
1255 F->getName () + ".regAllocState", &M);
1257 // Have: { uint, [Size x { uint, uint, uint, int }] } *
1258 // Cast it to: { uint, [0 x { uint, uint, uint, int }] } *
1259 Constant *CE = ConstantExpr::getCast (ConstantPointerRef::get (GV), PT);
1260 allstate.push_back (CE);
1264 unsigned Size = allstate.size ();
1265 // Final structure type is:
1266 // { uint, [Size x { uint, [0 x { uint, uint, uint, int }] } *] }
1267 std::vector<const Type *> TV2;
1268 TV2.push_back (Type::UIntTy);
1269 ArrayType *AT2 = ArrayType::get (PT, Size);
1270 TV2.push_back (AT2);
1271 StructType *ST2 = StructType::get (TV2);
1272 std::vector<Constant *> CV2;
1273 CV2.push_back (ConstantUInt::get (Type::UIntTy, Size));
1274 CV2.push_back (ConstantArray::get (AT2, allstate));
1275 new GlobalVariable (ST2, true, GlobalValue::InternalLinkage,
1276 ConstantStruct::get (ST2, CV2), "_llvm_regAllocState",
1278 return false; // No error.
1282 /// Allocate registers for the machine code previously generated for F using
1283 /// the graph-coloring algorithm.
1285 bool PhyRegAlloc::runOnFunction (Function &F) {
1287 std::cerr << "\n********* Function "<< F.getName () << " ***********\n";
1290 MF = &MachineFunction::get (Fn);
1291 LVI = &getAnalysis<FunctionLiveVarInfo> ();
1292 LRI = new LiveRangeInfo (Fn, TM, RegClassList);
1293 LoopDepthCalc = &getAnalysis<LoopInfo> ();
1295 // Create each RegClass for the target machine and add it to the
1296 // RegClassList. This must be done before calling constructLiveRanges().
1297 for (unsigned rc = 0; rc != NumOfRegClasses; ++rc)
1298 RegClassList.push_back (new RegClass (Fn, &TM.getRegInfo (),
1299 MRI.getMachineRegClass (rc)));
1301 LRI->constructLiveRanges(); // create LR info
1302 if (DEBUG_RA >= RA_DEBUG_LiveRanges)
1303 LRI->printLiveRanges();
1305 createIGNodeListsAndIGs(); // create IGNode list and IGs
1307 buildInterferenceGraphs(); // build IGs in all reg classes
1309 if (DEBUG_RA >= RA_DEBUG_LiveRanges) {
1310 // print all LRs in all reg classes
1311 for ( unsigned rc=0; rc < NumOfRegClasses ; rc++)
1312 RegClassList[rc]->printIGNodeList();
1314 // print IGs in all register classes
1315 for ( unsigned rc=0; rc < NumOfRegClasses ; rc++)
1316 RegClassList[rc]->printIG();
1319 LRI->coalesceLRs(); // coalesce all live ranges
1321 if (DEBUG_RA >= RA_DEBUG_LiveRanges) {
1322 // print all LRs in all reg classes
1323 for (unsigned rc=0; rc < NumOfRegClasses; rc++)
1324 RegClassList[rc]->printIGNodeList();
1326 // print IGs in all register classes
1327 for (unsigned rc=0; rc < NumOfRegClasses; rc++)
1328 RegClassList[rc]->printIG();
1331 // mark un-usable suggested color before graph coloring algorithm.
1332 // When this is done, the graph coloring algo will not reserve
1333 // suggested color unnecessarily - they can be used by another LR
1334 markUnusableSugColors();
1336 // color all register classes using the graph coloring algo
1337 for (unsigned rc=0; rc < NumOfRegClasses ; rc++)
1338 RegClassList[rc]->colorAllRegs();
1340 // After graph coloring, if some LRs did not receive a color (i.e, spilled)
1341 // a position for such spilled LRs
1342 allocateStackSpace4SpilledLRs();
1344 // Reset the temp. area on the stack before use by the first instruction.
1345 // This will also happen after updating each instruction.
1346 MF->getInfo()->popAllTempValues();
1348 // color incoming args - if the correct color was not received
1349 // insert code to copy to the correct register
1350 colorIncomingArgs();
1352 // Save register allocation state for this function in a Constant.
1353 if (SaveRegAllocState)
1355 if (DEBUG_RA) { // Check our work.
1356 verifySavedState ();
1359 // Now update the machine code with register names and add any additional
1360 // code inserted by the register allocator to the instruction stream.
1361 updateMachineCode();
1364 std::cerr << "\n**** Machine Code After Register Allocation:\n\n";
1368 // Tear down temporary data structures
1369 for (unsigned rc = 0; rc < NumOfRegClasses; ++rc)
1370 delete RegClassList[rc];
1371 RegClassList.clear ();
1372 AddedInstrMap.clear ();
1373 OperandsColoredMap.clear ();
1374 ScratchRegsUsed.clear ();
1375 AddedInstrAtEntry.clear ();
1378 if (DEBUG_RA) std::cerr << "\nRegister allocation complete!\n";
1379 return false; // Function was not modified