1 //===-- PhyRegAlloc.cpp ---------------------------------------------------===//
3 // Register allocation for LLVM.
5 //===----------------------------------------------------------------------===//
7 #include "llvm/CodeGen/RegisterAllocation.h"
8 #include "RegAllocCommon.h"
9 #include "llvm/CodeGen/IGNode.h"
10 #include "llvm/CodeGen/RegClass.h"
11 #include "llvm/CodeGen/PhyRegAlloc.h"
12 #include "llvm/CodeGen/MachineInstrBuilder.h"
13 #include "llvm/CodeGen/MachineInstrAnnot.h"
14 #include "llvm/CodeGen/MachineFunction.h"
15 #include "llvm/CodeGen/MachineFunctionInfo.h"
16 #include "llvm/CodeGen/FunctionLiveVarInfo.h"
17 #include "llvm/Analysis/LoopInfo.h"
18 #include "llvm/Target/TargetMachine.h"
19 #include "llvm/Target/TargetFrameInfo.h"
20 #include "llvm/Target/TargetInstrInfo.h"
21 #include "llvm/Function.h"
22 #include "llvm/Type.h"
23 #include "llvm/iOther.h"
24 #include "Support/STLExtras.h"
25 #include "Support/CommandLine.h"
30 RegAllocDebugLevel_t DEBUG_RA;
32 static cl::opt<RegAllocDebugLevel_t, true>
33 DRA_opt("dregalloc", cl::Hidden, cl::location(DEBUG_RA),
34 cl::desc("enable register allocation debugging information"),
36 clEnumValN(RA_DEBUG_None , "n", "disable debug output"),
37 clEnumValN(RA_DEBUG_Results, "y", "debug output for allocation results"),
38 clEnumValN(RA_DEBUG_Coloring, "c", "debug output for graph coloring step"),
39 clEnumValN(RA_DEBUG_Interference,"ig","debug output for interference graphs"),
40 clEnumValN(RA_DEBUG_LiveRanges , "lr","debug output for live ranges"),
41 clEnumValN(RA_DEBUG_Verbose, "v", "extra debug output"),
44 //----------------------------------------------------------------------------
45 // RegisterAllocation pass front end...
46 //----------------------------------------------------------------------------
48 class RegisterAllocator : public FunctionPass {
49 TargetMachine &Target;
51 inline RegisterAllocator(TargetMachine &T) : Target(T) {}
53 const char *getPassName() const { return "Register Allocation"; }
55 bool runOnFunction(Function &F) {
57 cerr << "\n********* Function "<< F.getName() << " ***********\n";
59 PhyRegAlloc PRA(&F, Target, &getAnalysis<FunctionLiveVarInfo>(),
60 &getAnalysis<LoopInfo>());
61 PRA.allocateRegisters();
63 if (DEBUG_RA) cerr << "\nRegister allocation complete!\n";
67 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
68 AU.addRequired<LoopInfo>();
69 AU.addRequired<FunctionLiveVarInfo>();
74 Pass *getRegisterAllocator(TargetMachine &T) {
75 return new RegisterAllocator(T);
78 //----------------------------------------------------------------------------
79 // Constructor: Init local composite objects and create register classes.
80 //----------------------------------------------------------------------------
81 PhyRegAlloc::PhyRegAlloc(Function *F, const TargetMachine& tm,
82 FunctionLiveVarInfo *Lvi, LoopInfo *LDC)
83 : TM(tm), Fn(F), MF(MachineFunction::get(F)), LVI(Lvi),
84 LRI(F, tm, RegClassList), MRI(tm.getRegInfo()),
85 NumOfRegClasses(MRI.getNumOfRegClasses()), LoopDepthCalc(LDC) {
87 // create each RegisterClass and put in RegClassList
89 for (unsigned rc=0; rc != NumOfRegClasses; rc++)
90 RegClassList.push_back(new RegClass(F, MRI.getMachineRegClass(rc),
95 //----------------------------------------------------------------------------
96 // Destructor: Deletes register classes
97 //----------------------------------------------------------------------------
98 PhyRegAlloc::~PhyRegAlloc() {
99 for ( unsigned rc=0; rc < NumOfRegClasses; rc++)
100 delete RegClassList[rc];
102 AddedInstrMap.clear();
105 //----------------------------------------------------------------------------
106 // This method initally creates interference graphs (one in each reg class)
107 // and IGNodeList (one in each IG). The actual nodes will be pushed later.
108 //----------------------------------------------------------------------------
109 void PhyRegAlloc::createIGNodeListsAndIGs() {
110 if (DEBUG_RA >= RA_DEBUG_LiveRanges) cerr << "Creating LR lists ...\n";
113 LiveRangeMapType::const_iterator HMI = LRI.getLiveRangeMap()->begin();
116 LiveRangeMapType::const_iterator HMIEnd = LRI.getLiveRangeMap()->end();
118 for (; HMI != HMIEnd ; ++HMI ) {
120 LiveRange *L = HMI->second; // get the LiveRange
123 cerr << "\n**** ?!?WARNING: NULL LIVE RANGE FOUND FOR: "
124 << RAV(HMI->first) << "****\n";
128 // if the Value * is not null, and LR is not yet written to the IGNodeList
129 if (!(L->getUserIGNode()) ) {
130 RegClass *const RC = // RegClass of first value in the LR
131 RegClassList[ L->getRegClass()->getID() ];
132 RC->addLRToIG(L); // add this LR to an IG
138 for ( unsigned rc=0; rc < NumOfRegClasses ; rc++)
139 RegClassList[rc]->createInterferenceGraph();
141 if (DEBUG_RA >= RA_DEBUG_LiveRanges) cerr << "LRLists Created!\n";
145 //----------------------------------------------------------------------------
146 // This method will add all interferences at for a given instruction.
147 // Interence occurs only if the LR of Def (Inst or Arg) is of the same reg
148 // class as that of live var. The live var passed to this function is the
149 // LVset AFTER the instruction
150 //----------------------------------------------------------------------------
152 void PhyRegAlloc::addInterference(const Value *Def,
153 const ValueSet *LVSet,
156 ValueSet::const_iterator LIt = LVSet->begin();
158 // get the live range of instruction
160 const LiveRange *const LROfDef = LRI.getLiveRangeForValue( Def );
162 IGNode *const IGNodeOfDef = LROfDef->getUserIGNode();
163 assert( IGNodeOfDef );
165 RegClass *const RCOfDef = LROfDef->getRegClass();
167 // for each live var in live variable set
169 for ( ; LIt != LVSet->end(); ++LIt) {
171 if (DEBUG_RA >= RA_DEBUG_Verbose)
172 cerr << "< Def=" << RAV(Def) << ", Lvar=" << RAV(*LIt) << "> ";
174 // get the live range corresponding to live var
176 LiveRange *LROfVar = LRI.getLiveRangeForValue(*LIt);
178 // LROfVar can be null if it is a const since a const
179 // doesn't have a dominating def - see Assumptions above
182 if (LROfDef != LROfVar) // do not set interf for same LR
183 if (RCOfDef == LROfVar->getRegClass()) // 2 reg classes are the same
184 RCOfDef->setInterference( LROfDef, LROfVar);
190 //----------------------------------------------------------------------------
191 // For a call instruction, this method sets the CallInterference flag in
192 // the LR of each variable live int the Live Variable Set live after the
193 // call instruction (except the return value of the call instruction - since
194 // the return value does not interfere with that call itself).
195 //----------------------------------------------------------------------------
197 void PhyRegAlloc::setCallInterferences(const MachineInstr *MInst,
198 const ValueSet *LVSetAft) {
200 if (DEBUG_RA >= RA_DEBUG_Interference)
201 cerr << "\n For call inst: " << *MInst;
203 ValueSet::const_iterator LIt = LVSetAft->begin();
205 // for each live var in live variable set after machine inst
207 for ( ; LIt != LVSetAft->end(); ++LIt) {
209 // get the live range corresponding to live var
211 LiveRange *const LR = LRI.getLiveRangeForValue(*LIt );
213 // LR can be null if it is a const since a const
214 // doesn't have a dominating def - see Assumptions above
217 if (DEBUG_RA >= RA_DEBUG_Interference) {
218 cerr << "\n\tLR after Call: ";
221 LR->setCallInterference();
222 if (DEBUG_RA >= RA_DEBUG_Interference) {
223 cerr << "\n ++After adding call interference for LR: " ;
230 // Now find the LR of the return value of the call
231 // We do this because, we look at the LV set *after* the instruction
232 // to determine, which LRs must be saved across calls. The return value
233 // of the call is live in this set - but it does not interfere with call
234 // (i.e., we can allocate a volatile register to the return value)
236 CallArgsDescriptor* argDesc = CallArgsDescriptor::get(MInst);
238 if (const Value *RetVal = argDesc->getReturnValue()) {
239 LiveRange *RetValLR = LRI.getLiveRangeForValue( RetVal );
240 assert( RetValLR && "No LR for RetValue of call");
241 RetValLR->clearCallInterference();
244 // If the CALL is an indirect call, find the LR of the function pointer.
245 // That has a call interference because it conflicts with outgoing args.
246 if (const Value *AddrVal = argDesc->getIndirectFuncPtr()) {
247 LiveRange *AddrValLR = LRI.getLiveRangeForValue( AddrVal );
248 assert( AddrValLR && "No LR for indirect addr val of call");
249 AddrValLR->setCallInterference();
257 //----------------------------------------------------------------------------
258 // This method will walk thru code and create interferences in the IG of
259 // each RegClass. Also, this method calculates the spill cost of each
260 // Live Range (it is done in this method to save another pass over the code).
261 //----------------------------------------------------------------------------
262 void PhyRegAlloc::buildInterferenceGraphs()
265 if (DEBUG_RA >= RA_DEBUG_Interference)
266 cerr << "Creating interference graphs ...\n";
268 unsigned BBLoopDepthCost;
269 for (MachineFunction::iterator BBI = MF.begin(), BBE = MF.end();
271 const MachineBasicBlock &MBB = *BBI;
272 const BasicBlock *BB = MBB.getBasicBlock();
274 // find the 10^(loop_depth) of this BB
276 BBLoopDepthCost = (unsigned)pow(10.0, LoopDepthCalc->getLoopDepth(BB));
278 // get the iterator for machine instructions
280 MachineBasicBlock::const_iterator MII = MBB.begin();
282 // iterate over all the machine instructions in BB
284 for ( ; MII != MBB.end(); ++MII) {
285 const MachineInstr *MInst = *MII;
287 // get the LV set after the instruction
289 const ValueSet &LVSetAI = LVI->getLiveVarSetAfterMInst(MInst, BB);
290 bool isCallInst = TM.getInstrInfo().isCall(MInst->getOpCode());
293 // set the isCallInterference flag of each live range wich extends
294 // accross this call instruction. This information is used by graph
295 // coloring algo to avoid allocating volatile colors to live ranges
296 // that span across calls (since they have to be saved/restored)
298 setCallInterferences(MInst, &LVSetAI);
301 // iterate over all MI operands to find defs
303 for (MachineInstr::const_val_op_iterator OpI = MInst->begin(),
304 OpE = MInst->end(); OpI != OpE; ++OpI) {
305 if (OpI.isDef()) // create a new LR iff this operand is a def
306 addInterference(*OpI, &LVSetAI, isCallInst);
308 // Calculate the spill cost of each live range
310 LiveRange *LR = LRI.getLiveRangeForValue(*OpI);
311 if (LR) LR->addSpillCost(BBLoopDepthCost);
315 // if there are multiple defs in this instruction e.g. in SETX
317 if (TM.getInstrInfo().isPseudoInstr(MInst->getOpCode()))
318 addInterf4PseudoInstr(MInst);
321 // Also add interference for any implicit definitions in a machine
322 // instr (currently, only calls have this).
324 unsigned NumOfImpRefs = MInst->getNumImplicitRefs();
325 if ( NumOfImpRefs > 0 ) {
326 for (unsigned z=0; z < NumOfImpRefs; z++)
327 if (MInst->implicitRefIsDefined(z) )
328 addInterference( MInst->getImplicitRef(z), &LVSetAI, isCallInst );
332 } // for all machine instructions in BB
333 } // for all BBs in function
336 // add interferences for function arguments. Since there are no explict
337 // defs in the function for args, we have to add them manually
339 addInterferencesForArgs();
341 if (DEBUG_RA >= RA_DEBUG_Interference)
342 cerr << "Interference graphs calculated!\n";
347 //--------------------------------------------------------------------------
348 // Pseudo instructions will be exapnded to multiple instructions by the
349 // assembler. Consequently, all the opernds must get distinct registers.
350 // Therefore, we mark all operands of a pseudo instruction as they interfere
352 //--------------------------------------------------------------------------
353 void PhyRegAlloc::addInterf4PseudoInstr(const MachineInstr *MInst) {
355 bool setInterf = false;
357 // iterate over MI operands to find defs
359 for (MachineInstr::const_val_op_iterator It1 = MInst->begin(),
360 ItE = MInst->end(); It1 != ItE; ++It1) {
361 const LiveRange *LROfOp1 = LRI.getLiveRangeForValue(*It1);
362 assert((LROfOp1 || !It1.isDef()) && "No LR for Def in PSEUDO insruction");
364 MachineInstr::const_val_op_iterator It2 = It1;
365 for (++It2; It2 != ItE; ++It2) {
366 const LiveRange *LROfOp2 = LRI.getLiveRangeForValue(*It2);
369 RegClass *RCOfOp1 = LROfOp1->getRegClass();
370 RegClass *RCOfOp2 = LROfOp2->getRegClass();
372 if (RCOfOp1 == RCOfOp2 ){
373 RCOfOp1->setInterference( LROfOp1, LROfOp2 );
377 } // for all other defs in machine instr
378 } // for all operands in an instruction
380 if (!setInterf && MInst->getNumOperands() > 2) {
381 cerr << "\nInterf not set for any operand in pseudo instr:\n";
383 assert(0 && "Interf not set for pseudo instr with > 2 operands" );
389 //----------------------------------------------------------------------------
390 // This method will add interferences for incoming arguments to a function.
391 //----------------------------------------------------------------------------
393 void PhyRegAlloc::addInterferencesForArgs() {
394 // get the InSet of root BB
395 const ValueSet &InSet = LVI->getInSetOfBB(&Fn->front());
397 for (Function::const_aiterator AI = Fn->abegin(); AI != Fn->aend(); ++AI) {
398 // add interferences between args and LVars at start
399 addInterference(AI, &InSet, false);
401 if (DEBUG_RA >= RA_DEBUG_Interference)
402 cerr << " - %% adding interference for argument " << RAV(AI) << "\n";
407 //----------------------------------------------------------------------------
408 // This method is called after register allocation is complete to set the
409 // allocated reisters in the machine code. This code will add register numbers
410 // to MachineOperands that contain a Value. Also it calls target specific
411 // methods to produce caller saving instructions. At the end, it adds all
412 // additional instructions produced by the register allocator to the
413 // instruction stream.
414 //----------------------------------------------------------------------------
416 //-----------------------------
417 // Utility functions used below
418 //-----------------------------
420 InsertBefore(MachineInstr* newMI,
421 MachineBasicBlock& MBB,
422 MachineBasicBlock::iterator& MII)
424 MII = MBB.insert(MII, newMI);
429 InsertAfter(MachineInstr* newMI,
430 MachineBasicBlock& MBB,
431 MachineBasicBlock::iterator& MII)
433 ++MII; // insert before the next instruction
434 MII = MBB.insert(MII, newMI);
438 SubstituteInPlace(MachineInstr* newMI,
439 MachineBasicBlock& MBB,
440 MachineBasicBlock::iterator MII)
446 PrependInstructions(vector<MachineInstr *> &IBef,
447 MachineBasicBlock& MBB,
448 MachineBasicBlock::iterator& MII,
449 const std::string& msg)
453 MachineInstr* OrigMI = *MII;
454 std::vector<MachineInstr *>::iterator AdIt;
455 for (AdIt = IBef.begin(); AdIt != IBef.end() ; ++AdIt)
458 if (OrigMI) cerr << "For MInst:\n " << *OrigMI;
459 cerr << msg << "PREPENDed instr:\n " << **AdIt << "\n";
461 InsertBefore(*AdIt, MBB, MII);
467 AppendInstructions(std::vector<MachineInstr *> &IAft,
468 MachineBasicBlock& MBB,
469 MachineBasicBlock::iterator& MII,
470 const std::string& msg)
474 MachineInstr* OrigMI = *MII;
475 std::vector<MachineInstr *>::iterator AdIt;
476 for ( AdIt = IAft.begin(); AdIt != IAft.end() ; ++AdIt )
479 if (OrigMI) cerr << "For MInst:\n " << *OrigMI;
480 cerr << msg << "APPENDed instr:\n " << **AdIt << "\n";
482 InsertAfter(*AdIt, MBB, MII);
488 void PhyRegAlloc::updateMachineCode() {
489 // Insert any instructions needed at method entry
490 MachineBasicBlock::iterator MII = MF.front().begin();
491 PrependInstructions(AddedInstrAtEntry.InstrnsBefore, MF.front(), MII,
492 "At function entry: \n");
493 assert(AddedInstrAtEntry.InstrnsAfter.empty() &&
494 "InstrsAfter should be unnecessary since we are just inserting at "
495 "the function entry point here.");
497 for (MachineFunction::iterator BBI = MF.begin(), BBE = MF.end();
500 // iterate over all the machine instructions in BB
501 MachineBasicBlock &MBB = *BBI;
502 for (MachineBasicBlock::iterator MII = MBB.begin();
503 MII != MBB.end(); ++MII) {
505 MachineInstr *MInst = *MII;
506 unsigned Opcode = MInst->getOpCode();
508 // do not process Phis
509 if (TM.getInstrInfo().isDummyPhiInstr(Opcode))
512 // Reset tmp stack positions so they can be reused for each machine instr.
513 MF.getInfo()->popAllTempValues();
515 // Now insert speical instructions (if necessary) for call/return
518 if (TM.getInstrInfo().isCall(Opcode) ||
519 TM.getInstrInfo().isReturn(Opcode)) {
520 AddedInstrns &AI = AddedInstrMap[MInst];
522 if (TM.getInstrInfo().isCall(Opcode))
523 MRI.colorCallArgs(MInst, LRI, &AI, *this, MBB.getBasicBlock());
524 else if (TM.getInstrInfo().isReturn(Opcode))
525 MRI.colorRetValue(MInst, LRI, &AI);
528 // Set the registers for operands in the machine instruction
529 // if a register was successfully allocated. If not, insert
530 // code to spill the register value.
532 for (unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum)
534 MachineOperand& Op = MInst->getOperand(OpNum);
535 if (Op.getType() == MachineOperand::MO_VirtualRegister ||
536 Op.getType() == MachineOperand::MO_CCRegister)
538 const Value *const Val = Op.getVRegValue();
540 LiveRange *const LR = LRI.getLiveRangeForValue(Val);
541 if (!LR) // consts or labels will have no live range
543 // if register is not allocated, mark register as invalid
544 if (Op.getAllocatedRegNum() == -1)
545 MInst->SetRegForOperand(OpNum, MRI.getInvalidRegNum());
550 MInst->SetRegForOperand(OpNum,
551 MRI.getUnifiedRegNum(LR->getRegClass()->getID(),
554 // LR did NOT receive a color (register). Insert spill code.
555 insertCode4SpilledLR(LR, MInst, MBB.getBasicBlock(), OpNum);
557 } // for each operand
559 // Now add instructions that the register allocator inserts before/after
560 // this machine instructions (done only for calls/rets/incoming args)
561 // We do this here, to ensure that spill for an instruction is inserted
562 // closest as possible to an instruction (see above insertCode4Spill...)
564 // First, if the instruction in the delay slot of a branch needs
565 // instructions inserted, move it out of the delay slot and before the
566 // branch because putting code before or after it would be VERY BAD!
568 unsigned bumpIteratorBy = 0;
569 if (MII != MBB.begin())
570 if (unsigned predDelaySlots =
571 TM.getInstrInfo().getNumDelaySlots((*(MII-1))->getOpCode()))
573 assert(predDelaySlots==1 && "Not handling multiple delay slots!");
574 if (TM.getInstrInfo().isBranch((*(MII-1))->getOpCode())
575 && (AddedInstrMap.count(MInst) ||
576 AddedInstrMap[MInst].InstrnsAfter.size() > 0))
578 // Current instruction is in the delay slot of a branch and it
579 // needs spill code inserted before or after it.
580 // Move it before the preceding branch.
581 InsertBefore(MInst, MBB, --MII);
582 MachineInstr* nopI = BuildMI(TM.getInstrInfo().getNOPOpCode(),1);
583 SubstituteInPlace(nopI, MBB, MII+1); // replace orig with NOP
584 --MII; // point to MInst in new location
585 bumpIteratorBy = 2; // later skip the branch and the NOP!
589 // If there are instructions to be added, *before* this machine
590 // instruction, add them now.
592 if (AddedInstrMap.count(MInst)) {
593 PrependInstructions(AddedInstrMap[MInst].InstrnsBefore, MBB, MII,"");
596 // If there are instructions to be added *after* this machine
597 // instruction, add them now
599 if (!AddedInstrMap[MInst].InstrnsAfter.empty()) {
601 // if there are delay slots for this instruction, the instructions
602 // added after it must really go after the delayed instruction(s)
603 // So, we move the InstrAfter of the current instruction to the
604 // corresponding delayed instruction
606 TM.getInstrInfo().getNumDelaySlots(MInst->getOpCode())) {
608 // Delayed instructions are typically branches or calls. Let's make
609 // sure this is not a branch, otherwise "insert-after" is meaningless,
610 // and should never happen for any reason (spill code, register
612 assert(! TM.getInstrInfo().isBranch(MInst->getOpCode()) &&
613 ! TM.getInstrInfo().isReturn(MInst->getOpCode()) &&
614 "INTERNAL ERROR: Register allocator should not be inserting "
615 "any code after a branch or return!");
617 move2DelayedInstr(MInst, *(MII+delay) );
620 // Here we can add the "instructions after" to the current
621 // instruction since there are no delay slots for this instruction
622 AppendInstructions(AddedInstrMap[MInst].InstrnsAfter, MBB, MII,"");
626 // If we mucked with the instruction order above, adjust the loop iterator
628 MII = MII + bumpIteratorBy;
630 } // for each machine instruction
636 //----------------------------------------------------------------------------
637 // This method inserts spill code for AN operand whose LR was spilled.
638 // This method may be called several times for a single machine instruction
639 // if it contains many spilled operands. Each time it is called, it finds
640 // a register which is not live at that instruction and also which is not
641 // used by other spilled operands of the same instruction. Then it uses
642 // this register temporarily to accomodate the spilled value.
643 //----------------------------------------------------------------------------
644 void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
646 const BasicBlock *BB,
647 const unsigned OpNum) {
649 assert((! TM.getInstrInfo().isCall(MInst->getOpCode()) || OpNum == 0) &&
650 "Outgoing arg of a call must be handled elsewhere (func arg ok)");
651 assert(! TM.getInstrInfo().isReturn(MInst->getOpCode()) &&
652 "Return value of a ret must be handled elsewhere");
654 MachineOperand& Op = MInst->getOperand(OpNum);
655 bool isDef = MInst->operandIsDefined(OpNum);
656 bool isDefAndUse = MInst->operandIsDefinedAndUsed(OpNum);
657 unsigned RegType = MRI.getRegType( LR );
658 int SpillOff = LR->getSpillOffFromFP();
659 RegClass *RC = LR->getRegClass();
660 const ValueSet &LVSetBef = LVI->getLiveVarSetBeforeMInst(MInst, BB);
662 MF.getInfo()->pushTempValue(MRI.getSpilledRegSize(RegType) );
664 vector<MachineInstr*> MIBef, MIAft;
665 vector<MachineInstr*> AdIMid;
667 // Choose a register to hold the spilled value. This may insert code
668 // before and after MInst to free up the value. If so, this code should
669 // be first and last in the spill sequence before/after MInst.
670 int TmpRegU = getUsableUniRegAtMI(RegType, &LVSetBef, MInst, MIBef, MIAft);
672 // Set the operand first so that it this register does not get used
673 // as a scratch register for later calls to getUsableUniRegAtMI below
674 MInst->SetRegForOperand(OpNum, TmpRegU);
676 // get the added instructions for this instruction
677 AddedInstrns &AI = AddedInstrMap[MInst];
679 // We may need a scratch register to copy the spilled value to/from memory.
680 // This may itself have to insert code to free up a scratch register.
681 // Any such code should go before (after) the spill code for a load (store).
682 int scratchRegType = -1;
684 if (MRI.regTypeNeedsScratchReg(RegType, scratchRegType))
686 scratchReg = getUsableUniRegAtMI(scratchRegType, &LVSetBef,
687 MInst, MIBef, MIAft);
688 assert(scratchReg != MRI.getInvalidRegNum());
689 MInst->insertUsedReg(scratchReg);
692 if (!isDef || isDefAndUse) {
693 // for a USE, we have to load the value of LR from stack to a TmpReg
694 // and use the TmpReg as one operand of instruction
696 // actual loading instruction(s)
697 MRI.cpMem2RegMI(AdIMid, MRI.getFramePointer(), SpillOff, TmpRegU, RegType,
700 // the actual load should be after the instructions to free up TmpRegU
701 MIBef.insert(MIBef.end(), AdIMid.begin(), AdIMid.end());
705 if (isDef) { // if this is a Def
706 // for a DEF, we have to store the value produced by this instruction
707 // on the stack position allocated for this LR
709 // actual storing instruction(s)
710 MRI.cpReg2MemMI(AdIMid, TmpRegU, MRI.getFramePointer(), SpillOff, RegType,
713 MIAft.insert(MIAft.begin(), AdIMid.begin(), AdIMid.end());
716 // Finally, insert the entire spill code sequences before/after MInst
717 AI.InstrnsBefore.insert(AI.InstrnsBefore.end(), MIBef.begin(), MIBef.end());
718 AI.InstrnsAfter.insert(AI.InstrnsAfter.begin(), MIAft.begin(), MIAft.end());
721 cerr << "\nFor Inst:\n " << *MInst;
722 cerr << "SPILLED LR# " << LR->getUserIGNode()->getIndex();
723 cerr << "; added Instructions:";
724 for_each(MIBef.begin(), MIBef.end(), std::mem_fun(&MachineInstr::dump));
725 for_each(MIAft.begin(), MIAft.end(), std::mem_fun(&MachineInstr::dump));
730 //----------------------------------------------------------------------------
731 // We can use the following method to get a temporary register to be used
732 // BEFORE any given machine instruction. If there is a register available,
733 // this method will simply return that register and set MIBef = MIAft = NULL.
734 // Otherwise, it will return a register and MIAft and MIBef will contain
735 // two instructions used to free up this returned register.
736 // Returned register number is the UNIFIED register number
737 //----------------------------------------------------------------------------
739 int PhyRegAlloc::getUsableUniRegAtMI(const int RegType,
740 const ValueSet *LVSetBef,
742 std::vector<MachineInstr*>& MIBef,
743 std::vector<MachineInstr*>& MIAft) {
745 RegClass* RC = getRegClassByID(MRI.getRegClassIDOfRegType(RegType));
747 int RegU = getUnusedUniRegAtMI(RC, MInst, LVSetBef);
750 // we couldn't find an unused register. Generate code to free up a reg by
751 // saving it on stack and restoring after the instruction
753 int TmpOff = MF.getInfo()->pushTempValue(MRI.getSpilledRegSize(RegType));
755 RegU = getUniRegNotUsedByThisInst(RC, MInst);
757 // Check if we need a scratch register to copy this register to memory.
758 int scratchRegType = -1;
759 if (MRI.regTypeNeedsScratchReg(RegType, scratchRegType))
761 int scratchReg = getUsableUniRegAtMI(scratchRegType, LVSetBef,
762 MInst, MIBef, MIAft);
763 assert(scratchReg != MRI.getInvalidRegNum());
765 // We may as well hold the value in the scratch register instead
766 // of copying it to memory and back. But we have to mark the
767 // register as used by this instruction, so it does not get used
768 // as a scratch reg. by another operand or anyone else.
769 MInst->insertUsedReg(scratchReg);
770 MRI.cpReg2RegMI(MIBef, RegU, scratchReg, RegType);
771 MRI.cpReg2RegMI(MIAft, scratchReg, RegU, RegType);
774 { // the register can be copied directly to/from memory so do it.
775 MRI.cpReg2MemMI(MIBef, RegU, MRI.getFramePointer(), TmpOff, RegType);
776 MRI.cpMem2RegMI(MIAft, MRI.getFramePointer(), TmpOff, RegU, RegType);
783 //----------------------------------------------------------------------------
784 // This method is called to get a new unused register that can be used to
785 // accomodate a spilled value.
786 // This method may be called several times for a single machine instruction
787 // if it contains many spilled operands. Each time it is called, it finds
788 // a register which is not live at that instruction and also which is not
789 // used by other spilled operands of the same instruction.
790 // Return register number is relative to the register class. NOT
792 //----------------------------------------------------------------------------
793 int PhyRegAlloc::getUnusedUniRegAtMI(RegClass *RC,
794 const MachineInstr *MInst,
795 const ValueSet *LVSetBef) {
797 unsigned NumAvailRegs = RC->getNumOfAvailRegs();
799 std::vector<bool> &IsColorUsedArr = RC->getIsColorUsedArr();
801 for (unsigned i=0; i < NumAvailRegs; i++) // Reset array
802 IsColorUsedArr[i] = false;
804 ValueSet::const_iterator LIt = LVSetBef->begin();
806 // for each live var in live variable set after machine inst
807 for ( ; LIt != LVSetBef->end(); ++LIt) {
809 // get the live range corresponding to live var
810 LiveRange *const LRofLV = LRI.getLiveRangeForValue(*LIt );
812 // LR can be null if it is a const since a const
813 // doesn't have a dominating def - see Assumptions above
814 if (LRofLV && LRofLV->getRegClass() == RC && LRofLV->hasColor() )
815 IsColorUsedArr[ LRofLV->getColor() ] = true;
818 // It is possible that one operand of this MInst was already spilled
819 // and it received some register temporarily. If that's the case,
820 // it is recorded in machine operand. We must skip such registers.
822 setRelRegsUsedByThisInst(RC, MInst);
824 for (unsigned c=0; c < NumAvailRegs; c++) // find first unused color
825 if (!IsColorUsedArr[c])
826 return MRI.getUnifiedRegNum(RC->getID(), c);
832 //----------------------------------------------------------------------------
833 // Get any other register in a register class, other than what is used
834 // by operands of a machine instruction. Returns the unified reg number.
835 //----------------------------------------------------------------------------
836 int PhyRegAlloc::getUniRegNotUsedByThisInst(RegClass *RC,
837 const MachineInstr *MInst) {
839 vector<bool> &IsColorUsedArr = RC->getIsColorUsedArr();
840 unsigned NumAvailRegs = RC->getNumOfAvailRegs();
842 for (unsigned i=0; i < NumAvailRegs ; i++) // Reset array
843 IsColorUsedArr[i] = false;
845 setRelRegsUsedByThisInst(RC, MInst);
847 for (unsigned c=0; c < RC->getNumOfAvailRegs(); c++)// find first unused color
848 if (!IsColorUsedArr[c])
849 return MRI.getUnifiedRegNum(RC->getID(), c);
851 assert(0 && "FATAL: No free register could be found in reg class!!");
856 //----------------------------------------------------------------------------
857 // This method modifies the IsColorUsedArr of the register class passed to it.
858 // It sets the bits corresponding to the registers used by this machine
859 // instructions. Both explicit and implicit operands are set.
860 //----------------------------------------------------------------------------
861 void PhyRegAlloc::setRelRegsUsedByThisInst(RegClass *RC,
862 const MachineInstr *MInst ) {
864 vector<bool> &IsColorUsedArr = RC->getIsColorUsedArr();
866 // Add the registers already marked as used by the instruction.
867 // This should include any scratch registers that are used to save
868 // values across the instruction (e.g., for saving state register values).
869 const vector<bool> ®sUsed = MInst->getRegsUsed();
870 for (unsigned i = 0, e = regsUsed.size(); i != e; ++i)
872 unsigned classId = 0;
873 int classRegNum = MRI.getClassRegNum(i, classId);
874 if (RC->getID() == classId)
876 assert(classRegNum < (int) IsColorUsedArr.size() &&
877 "Illegal register number for this reg class?");
878 IsColorUsedArr[classRegNum] = true;
882 // Now add registers allocated to the live ranges of values used in
883 // the instruction. These are not yet recorded in the instruction.
884 for (unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum)
886 const MachineOperand& Op = MInst->getOperand(OpNum);
888 if (MInst->getOperandType(OpNum) == MachineOperand::MO_VirtualRegister ||
889 MInst->getOperandType(OpNum) == MachineOperand::MO_CCRegister)
890 if (const Value* Val = Op.getVRegValue())
891 if (MRI.getRegClassIDOfValue(Val) == RC->getID())
892 if (Op.getAllocatedRegNum() == -1)
893 if (LiveRange *LROfVal = LRI.getLiveRangeForValue(Val))
894 if (LROfVal->hasColor() )
895 // this operand is in a LR that received a color
896 IsColorUsedArr[LROfVal->getColor()] = true;
899 // If there are implicit references, mark their allocated regs as well
901 for (unsigned z=0; z < MInst->getNumImplicitRefs(); z++)
903 LRofImpRef = LRI.getLiveRangeForValue(MInst->getImplicitRef(z)))
904 if (LRofImpRef->hasColor())
905 // this implicit reference is in a LR that received a color
906 IsColorUsedArr[LRofImpRef->getColor()] = true;
910 //----------------------------------------------------------------------------
911 // If there are delay slots for an instruction, the instructions
912 // added after it must really go after the delayed instruction(s).
913 // So, we move the InstrAfter of that instruction to the
914 // corresponding delayed instruction using the following method.
916 //----------------------------------------------------------------------------
917 void PhyRegAlloc::move2DelayedInstr(const MachineInstr *OrigMI,
918 const MachineInstr *DelayedMI) {
920 // "added after" instructions of the original instr
921 std::vector<MachineInstr *> &OrigAft = AddedInstrMap[OrigMI].InstrnsAfter;
923 // "added instructions" of the delayed instr
924 AddedInstrns &DelayAdI = AddedInstrMap[DelayedMI];
926 // "added after" instructions of the delayed instr
927 std::vector<MachineInstr *> &DelayedAft = DelayAdI.InstrnsAfter;
929 // go thru all the "added after instructions" of the original instruction
930 // and append them to the "addded after instructions" of the delayed
932 DelayedAft.insert(DelayedAft.end(), OrigAft.begin(), OrigAft.end());
934 // empty the "added after instructions" of the original instruction
938 //----------------------------------------------------------------------------
939 // This method prints the code with registers after register allocation is
941 //----------------------------------------------------------------------------
942 void PhyRegAlloc::printMachineCode()
945 cerr << "\n;************** Function " << Fn->getName()
946 << " *****************\n";
948 for (MachineFunction::iterator BBI = MF.begin(), BBE = MF.end();
950 cerr << "\n"; printLabel(BBI->getBasicBlock()); cerr << ": ";
952 // get the iterator for machine instructions
953 MachineBasicBlock& MBB = *BBI;
954 MachineBasicBlock::iterator MII = MBB.begin();
956 // iterate over all the machine instructions in BB
957 for ( ; MII != MBB.end(); ++MII) {
958 MachineInstr *MInst = *MII;
961 cerr << TM.getInstrInfo().getName(MInst->getOpCode());
963 for (unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
964 MachineOperand& Op = MInst->getOperand(OpNum);
966 if (Op.getType() == MachineOperand::MO_VirtualRegister ||
967 Op.getType() == MachineOperand::MO_CCRegister /*||
968 Op.getType() == MachineOperand::MO_PCRelativeDisp*/ ) {
970 const Value *const Val = Op.getVRegValue () ;
971 // ****this code is temporary till NULL Values are fixed
973 cerr << "\t<*NULL*>";
977 // if a label or a constant
978 if (isa<BasicBlock>(Val)) {
979 cerr << "\t"; printLabel( Op.getVRegValue () );
981 // else it must be a register value
982 const int RegNum = Op.getAllocatedRegNum();
984 cerr << "\t" << "%" << MRI.getUnifiedRegName( RegNum );
986 cerr << "(" << Val->getName() << ")";
988 cerr << "(" << Val << ")";
993 const LiveRange *LROfVal = LRI.getLiveRangeForValue(Val);
995 if (LROfVal->hasSpillOffset() )
1000 else if (Op.getType() == MachineOperand::MO_MachineRegister) {
1001 cerr << "\t" << "%" << MRI.getUnifiedRegName(Op.getMachineRegNum());
1005 cerr << "\t" << Op; // use dump field
1010 unsigned NumOfImpRefs = MInst->getNumImplicitRefs();
1011 if (NumOfImpRefs > 0) {
1012 cerr << "\tImplicit:";
1014 for (unsigned z=0; z < NumOfImpRefs; z++)
1015 cerr << RAV(MInst->getImplicitRef(z)) << "\t";
1018 } // for all machine instructions
1028 //----------------------------------------------------------------------------
1030 //----------------------------------------------------------------------------
1031 void PhyRegAlloc::colorIncomingArgs()
1033 MRI.colorMethodArgs(Fn, LRI, &AddedInstrAtEntry);
1037 //----------------------------------------------------------------------------
1038 // Used to generate a label for a basic block
1039 //----------------------------------------------------------------------------
1040 void PhyRegAlloc::printLabel(const Value *Val) {
1042 cerr << Val->getName();
1044 cerr << "Label" << Val;
1048 //----------------------------------------------------------------------------
1049 // This method calls setSugColorUsable method of each live range. This
1050 // will determine whether the suggested color of LR is really usable.
1051 // A suggested color is not usable when the suggested color is volatile
1052 // AND when there are call interferences
1053 //----------------------------------------------------------------------------
1055 void PhyRegAlloc::markUnusableSugColors()
1057 // hash map iterator
1058 LiveRangeMapType::const_iterator HMI = (LRI.getLiveRangeMap())->begin();
1059 LiveRangeMapType::const_iterator HMIEnd = (LRI.getLiveRangeMap())->end();
1061 for (; HMI != HMIEnd ; ++HMI ) {
1063 LiveRange *L = HMI->second; // get the LiveRange
1065 if (L->hasSuggestedColor()) {
1066 int RCID = L->getRegClass()->getID();
1067 if (MRI.isRegVolatile( RCID, L->getSuggestedColor()) &&
1068 L->isCallInterference() )
1069 L->setSuggestedColorUsable( false );
1071 L->setSuggestedColorUsable( true );
1073 } // if L->hasSuggestedColor()
1075 } // for all LR's in hash map
1080 //----------------------------------------------------------------------------
1081 // The following method will set the stack offsets of the live ranges that
1082 // are decided to be spillled. This must be called just after coloring the
1083 // LRs using the graph coloring algo. For each live range that is spilled,
1084 // this method allocate a new spill position on the stack.
1085 //----------------------------------------------------------------------------
1087 void PhyRegAlloc::allocateStackSpace4SpilledLRs() {
1088 if (DEBUG_RA) cerr << "\nSetting LR stack offsets for spills...\n";
1090 LiveRangeMapType::const_iterator HMI = LRI.getLiveRangeMap()->begin();
1091 LiveRangeMapType::const_iterator HMIEnd = LRI.getLiveRangeMap()->end();
1093 for ( ; HMI != HMIEnd ; ++HMI) {
1094 if (HMI->first && HMI->second) {
1095 LiveRange *L = HMI->second; // get the LiveRange
1096 if (!L->hasColor()) { // NOTE: ** allocating the size of long Type **
1097 int stackOffset = MF.getInfo()->allocateSpilledValue(Type::LongTy);
1098 L->setSpillOffFromFP(stackOffset);
1100 cerr << " LR# " << L->getUserIGNode()->getIndex()
1101 << ": stack-offset = " << stackOffset << "\n";
1104 } // for all LR's in hash map
1109 //----------------------------------------------------------------------------
1110 // The entry pont to Register Allocation
1111 //----------------------------------------------------------------------------
1113 void PhyRegAlloc::allocateRegisters()
1116 // make sure that we put all register classes into the RegClassList
1117 // before we call constructLiveRanges (now done in the constructor of
1118 // PhyRegAlloc class).
1120 LRI.constructLiveRanges(); // create LR info
1122 if (DEBUG_RA >= RA_DEBUG_LiveRanges)
1123 LRI.printLiveRanges();
1125 createIGNodeListsAndIGs(); // create IGNode list and IGs
1127 buildInterferenceGraphs(); // build IGs in all reg classes
1130 if (DEBUG_RA >= RA_DEBUG_LiveRanges) {
1131 // print all LRs in all reg classes
1132 for ( unsigned rc=0; rc < NumOfRegClasses ; rc++)
1133 RegClassList[rc]->printIGNodeList();
1135 // print IGs in all register classes
1136 for ( unsigned rc=0; rc < NumOfRegClasses ; rc++)
1137 RegClassList[rc]->printIG();
1140 LRI.coalesceLRs(); // coalesce all live ranges
1142 if (DEBUG_RA >= RA_DEBUG_LiveRanges) {
1143 // print all LRs in all reg classes
1144 for (unsigned rc=0; rc < NumOfRegClasses; rc++)
1145 RegClassList[rc]->printIGNodeList();
1147 // print IGs in all register classes
1148 for (unsigned rc=0; rc < NumOfRegClasses; rc++)
1149 RegClassList[rc]->printIG();
1153 // mark un-usable suggested color before graph coloring algorithm.
1154 // When this is done, the graph coloring algo will not reserve
1155 // suggested color unnecessarily - they can be used by another LR
1157 markUnusableSugColors();
1159 // color all register classes using the graph coloring algo
1160 for (unsigned rc=0; rc < NumOfRegClasses ; rc++)
1161 RegClassList[rc]->colorAllRegs();
1163 // Atter graph coloring, if some LRs did not receive a color (i.e, spilled)
1164 // a poistion for such spilled LRs
1166 allocateStackSpace4SpilledLRs();
1168 MF.getInfo()->popAllTempValues(); // TODO **Check
1170 // color incoming args - if the correct color was not received
1171 // insert code to copy to the correct register
1173 colorIncomingArgs();
1175 // Now update the machine code with register names and add any
1176 // additional code inserted by the register allocator to the instruction
1179 updateMachineCode();
1182 cerr << "\n**** Machine Code After Register Allocation:\n\n";