1 //===-- PhyRegAlloc.cpp ---------------------------------------------------===//
3 // Register allocation for LLVM.
5 //===----------------------------------------------------------------------===//
7 #include "llvm/CodeGen/RegisterAllocation.h"
8 #include "RegAllocCommon.h"
10 #include "llvm/CodeGen/IGNode.h"
11 #include "llvm/CodeGen/PhyRegAlloc.h"
12 #include "llvm/CodeGen/MachineInstrBuilder.h"
13 #include "llvm/CodeGen/MachineInstrAnnot.h"
14 #include "llvm/CodeGen/MachineFunction.h"
15 #include "llvm/CodeGen/MachineFunctionInfo.h"
16 #include "llvm/CodeGen/FunctionLiveVarInfo.h"
17 #include "llvm/Analysis/LoopInfo.h"
18 #include "llvm/Target/TargetMachine.h"
19 #include "llvm/Target/TargetFrameInfo.h"
20 #include "llvm/Target/TargetInstrInfo.h"
21 #include "llvm/Function.h"
22 #include "llvm/Type.h"
23 #include "llvm/iOther.h"
24 #include "Support/STLExtras.h"
25 #include "Support/CommandLine.h"
30 RegAllocDebugLevel_t DEBUG_RA;
32 static cl::opt<RegAllocDebugLevel_t, true>
33 DRA_opt("dregalloc", cl::Hidden, cl::location(DEBUG_RA),
34 cl::desc("enable register allocation debugging information"),
36 clEnumValN(RA_DEBUG_None , "n", "disable debug output"),
37 clEnumValN(RA_DEBUG_Results, "y", "debug output for allocation results"),
38 clEnumValN(RA_DEBUG_Coloring, "c", "debug output for graph coloring step"),
39 clEnumValN(RA_DEBUG_Interference,"ig","debug output for interference graphs"),
40 clEnumValN(RA_DEBUG_LiveRanges , "lr","debug output for live ranges"),
41 clEnumValN(RA_DEBUG_Verbose, "v", "extra debug output"),
44 //----------------------------------------------------------------------------
45 // RegisterAllocation pass front end...
46 //----------------------------------------------------------------------------
48 class RegisterAllocator : public FunctionPass {
49 TargetMachine &Target;
51 inline RegisterAllocator(TargetMachine &T) : Target(T) {}
53 const char *getPassName() const { return "Register Allocation"; }
55 bool runOnFunction(Function &F) {
57 cerr << "\n********* Function "<< F.getName() << " ***********\n";
59 PhyRegAlloc PRA(&F, Target, &getAnalysis<FunctionLiveVarInfo>(),
60 &getAnalysis<LoopInfo>());
61 PRA.allocateRegisters();
63 if (DEBUG_RA) cerr << "\nRegister allocation complete!\n";
67 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
68 AU.addRequired<LoopInfo>();
69 AU.addRequired<FunctionLiveVarInfo>();
74 Pass *getRegisterAllocator(TargetMachine &T) {
75 return new RegisterAllocator(T);
78 //----------------------------------------------------------------------------
79 // Constructor: Init local composite objects and create register classes.
80 //----------------------------------------------------------------------------
81 PhyRegAlloc::PhyRegAlloc(Function *F, const TargetMachine& tm,
82 FunctionLiveVarInfo *Lvi, LoopInfo *LDC)
83 : TM(tm), Fn(F), MF(MachineFunction::get(F)), LVI(Lvi),
84 LRI(F, tm, RegClassList), MRI(tm.getRegInfo()),
85 NumOfRegClasses(MRI.getNumOfRegClasses()), LoopDepthCalc(LDC) {
87 // create each RegisterClass and put in RegClassList
89 for (unsigned rc=0; rc != NumOfRegClasses; rc++)
90 RegClassList.push_back(new RegClass(F, MRI.getMachineRegClass(rc),
95 //----------------------------------------------------------------------------
96 // Destructor: Deletes register classes
97 //----------------------------------------------------------------------------
98 PhyRegAlloc::~PhyRegAlloc() {
99 for ( unsigned rc=0; rc < NumOfRegClasses; rc++)
100 delete RegClassList[rc];
102 AddedInstrMap.clear();
105 //----------------------------------------------------------------------------
106 // This method initally creates interference graphs (one in each reg class)
107 // and IGNodeList (one in each IG). The actual nodes will be pushed later.
108 //----------------------------------------------------------------------------
109 void PhyRegAlloc::createIGNodeListsAndIGs() {
110 if (DEBUG_RA >= RA_DEBUG_LiveRanges) cerr << "Creating LR lists ...\n";
113 LiveRangeMapType::const_iterator HMI = LRI.getLiveRangeMap()->begin();
116 LiveRangeMapType::const_iterator HMIEnd = LRI.getLiveRangeMap()->end();
118 for (; HMI != HMIEnd ; ++HMI ) {
120 LiveRange *L = HMI->second; // get the LiveRange
123 cerr << "\n**** ?!?WARNING: NULL LIVE RANGE FOUND FOR: "
124 << RAV(HMI->first) << "****\n";
128 // if the Value * is not null, and LR is not yet written to the IGNodeList
129 if (!(L->getUserIGNode()) ) {
130 RegClass *const RC = // RegClass of first value in the LR
131 RegClassList[ L->getRegClass()->getID() ];
132 RC->addLRToIG(L); // add this LR to an IG
138 for ( unsigned rc=0; rc < NumOfRegClasses ; rc++)
139 RegClassList[rc]->createInterferenceGraph();
141 if (DEBUG_RA >= RA_DEBUG_LiveRanges) cerr << "LRLists Created!\n";
145 //----------------------------------------------------------------------------
146 // This method will add all interferences at for a given instruction.
147 // Interence occurs only if the LR of Def (Inst or Arg) is of the same reg
148 // class as that of live var. The live var passed to this function is the
149 // LVset AFTER the instruction
150 //----------------------------------------------------------------------------
152 void PhyRegAlloc::addInterference(const Value *Def,
153 const ValueSet *LVSet,
156 ValueSet::const_iterator LIt = LVSet->begin();
158 // get the live range of instruction
160 const LiveRange *const LROfDef = LRI.getLiveRangeForValue( Def );
162 IGNode *const IGNodeOfDef = LROfDef->getUserIGNode();
163 assert( IGNodeOfDef );
165 RegClass *const RCOfDef = LROfDef->getRegClass();
167 // for each live var in live variable set
169 for ( ; LIt != LVSet->end(); ++LIt) {
171 if (DEBUG_RA >= RA_DEBUG_Verbose)
172 cerr << "< Def=" << RAV(Def) << ", Lvar=" << RAV(*LIt) << "> ";
174 // get the live range corresponding to live var
176 LiveRange *LROfVar = LRI.getLiveRangeForValue(*LIt);
178 // LROfVar can be null if it is a const since a const
179 // doesn't have a dominating def - see Assumptions above
182 if (LROfDef != LROfVar) // do not set interf for same LR
183 if (RCOfDef == LROfVar->getRegClass()) // 2 reg classes are the same
184 RCOfDef->setInterference( LROfDef, LROfVar);
190 //----------------------------------------------------------------------------
191 // For a call instruction, this method sets the CallInterference flag in
192 // the LR of each variable live int the Live Variable Set live after the
193 // call instruction (except the return value of the call instruction - since
194 // the return value does not interfere with that call itself).
195 //----------------------------------------------------------------------------
197 void PhyRegAlloc::setCallInterferences(const MachineInstr *MInst,
198 const ValueSet *LVSetAft) {
200 if (DEBUG_RA >= RA_DEBUG_Interference)
201 cerr << "\n For call inst: " << *MInst;
203 ValueSet::const_iterator LIt = LVSetAft->begin();
205 // for each live var in live variable set after machine inst
207 for ( ; LIt != LVSetAft->end(); ++LIt) {
209 // get the live range corresponding to live var
211 LiveRange *const LR = LRI.getLiveRangeForValue(*LIt );
213 // LR can be null if it is a const since a const
214 // doesn't have a dominating def - see Assumptions above
217 if (DEBUG_RA >= RA_DEBUG_Interference) {
218 cerr << "\n\tLR after Call: ";
221 LR->setCallInterference();
222 if (DEBUG_RA >= RA_DEBUG_Interference) {
223 cerr << "\n ++After adding call interference for LR: " ;
230 // Now find the LR of the return value of the call
231 // We do this because, we look at the LV set *after* the instruction
232 // to determine, which LRs must be saved across calls. The return value
233 // of the call is live in this set - but it does not interfere with call
234 // (i.e., we can allocate a volatile register to the return value)
236 CallArgsDescriptor* argDesc = CallArgsDescriptor::get(MInst);
238 if (const Value *RetVal = argDesc->getReturnValue()) {
239 LiveRange *RetValLR = LRI.getLiveRangeForValue( RetVal );
240 assert( RetValLR && "No LR for RetValue of call");
241 RetValLR->clearCallInterference();
244 // If the CALL is an indirect call, find the LR of the function pointer.
245 // That has a call interference because it conflicts with outgoing args.
246 if (const Value *AddrVal = argDesc->getIndirectFuncPtr()) {
247 LiveRange *AddrValLR = LRI.getLiveRangeForValue( AddrVal );
248 assert( AddrValLR && "No LR for indirect addr val of call");
249 AddrValLR->setCallInterference();
257 //----------------------------------------------------------------------------
258 // This method will walk thru code and create interferences in the IG of
259 // each RegClass. Also, this method calculates the spill cost of each
260 // Live Range (it is done in this method to save another pass over the code).
261 //----------------------------------------------------------------------------
262 void PhyRegAlloc::buildInterferenceGraphs()
265 if (DEBUG_RA >= RA_DEBUG_Interference)
266 cerr << "Creating interference graphs ...\n";
268 unsigned BBLoopDepthCost;
269 for (MachineFunction::iterator BBI = MF.begin(), BBE = MF.end();
271 const MachineBasicBlock &MBB = *BBI;
272 const BasicBlock *BB = MBB.getBasicBlock();
274 // find the 10^(loop_depth) of this BB
276 BBLoopDepthCost = (unsigned)pow(10.0, LoopDepthCalc->getLoopDepth(BB));
278 // get the iterator for machine instructions
280 MachineBasicBlock::const_iterator MII = MBB.begin();
282 // iterate over all the machine instructions in BB
284 for ( ; MII != MBB.end(); ++MII) {
285 const MachineInstr *MInst = *MII;
287 // get the LV set after the instruction
289 const ValueSet &LVSetAI = LVI->getLiveVarSetAfterMInst(MInst, BB);
290 bool isCallInst = TM.getInstrInfo().isCall(MInst->getOpCode());
293 // set the isCallInterference flag of each live range wich extends
294 // accross this call instruction. This information is used by graph
295 // coloring algo to avoid allocating volatile colors to live ranges
296 // that span across calls (since they have to be saved/restored)
298 setCallInterferences(MInst, &LVSetAI);
301 // iterate over all MI operands to find defs
303 for (MachineInstr::const_val_op_iterator OpI = MInst->begin(),
304 OpE = MInst->end(); OpI != OpE; ++OpI) {
305 if (OpI.isDefOnly() || OpI.isDefAndUse()) // create a new LR since def
306 addInterference(*OpI, &LVSetAI, isCallInst);
308 // Calculate the spill cost of each live range
310 LiveRange *LR = LRI.getLiveRangeForValue(*OpI);
311 if (LR) LR->addSpillCost(BBLoopDepthCost);
315 // if there are multiple defs in this instruction e.g. in SETX
317 if (TM.getInstrInfo().isPseudoInstr(MInst->getOpCode()))
318 addInterf4PseudoInstr(MInst);
321 // Also add interference for any implicit definitions in a machine
322 // instr (currently, only calls have this).
324 unsigned NumOfImpRefs = MInst->getNumImplicitRefs();
325 for (unsigned z=0; z < NumOfImpRefs; z++)
326 if (MInst->getImplicitOp(z).opIsDefOnly() ||
327 MInst->getImplicitOp(z).opIsDefAndUse())
328 addInterference( MInst->getImplicitRef(z), &LVSetAI, isCallInst );
330 } // for all machine instructions in BB
331 } // for all BBs in function
334 // add interferences for function arguments. Since there are no explict
335 // defs in the function for args, we have to add them manually
337 addInterferencesForArgs();
339 if (DEBUG_RA >= RA_DEBUG_Interference)
340 cerr << "Interference graphs calculated!\n";
345 //--------------------------------------------------------------------------
346 // Pseudo instructions will be exapnded to multiple instructions by the
347 // assembler. Consequently, all the opernds must get distinct registers.
348 // Therefore, we mark all operands of a pseudo instruction as they interfere
350 //--------------------------------------------------------------------------
351 void PhyRegAlloc::addInterf4PseudoInstr(const MachineInstr *MInst) {
353 bool setInterf = false;
355 // iterate over MI operands to find defs
357 for (MachineInstr::const_val_op_iterator It1 = MInst->begin(),
358 ItE = MInst->end(); It1 != ItE; ++It1) {
359 const LiveRange *LROfOp1 = LRI.getLiveRangeForValue(*It1);
360 assert((LROfOp1 || !It1.isUseOnly())&& "No LR for Def in PSEUDO insruction");
362 MachineInstr::const_val_op_iterator It2 = It1;
363 for (++It2; It2 != ItE; ++It2) {
364 const LiveRange *LROfOp2 = LRI.getLiveRangeForValue(*It2);
367 RegClass *RCOfOp1 = LROfOp1->getRegClass();
368 RegClass *RCOfOp2 = LROfOp2->getRegClass();
370 if (RCOfOp1 == RCOfOp2 ){
371 RCOfOp1->setInterference( LROfOp1, LROfOp2 );
375 } // for all other defs in machine instr
376 } // for all operands in an instruction
378 if (!setInterf && MInst->getNumOperands() > 2) {
379 cerr << "\nInterf not set for any operand in pseudo instr:\n";
381 assert(0 && "Interf not set for pseudo instr with > 2 operands" );
387 //----------------------------------------------------------------------------
388 // This method will add interferences for incoming arguments to a function.
389 //----------------------------------------------------------------------------
391 void PhyRegAlloc::addInterferencesForArgs() {
392 // get the InSet of root BB
393 const ValueSet &InSet = LVI->getInSetOfBB(&Fn->front());
395 for (Function::const_aiterator AI = Fn->abegin(); AI != Fn->aend(); ++AI) {
396 // add interferences between args and LVars at start
397 addInterference(AI, &InSet, false);
399 if (DEBUG_RA >= RA_DEBUG_Interference)
400 cerr << " - %% adding interference for argument " << RAV(AI) << "\n";
405 //----------------------------------------------------------------------------
406 // This method is called after register allocation is complete to set the
407 // allocated reisters in the machine code. This code will add register numbers
408 // to MachineOperands that contain a Value. Also it calls target specific
409 // methods to produce caller saving instructions. At the end, it adds all
410 // additional instructions produced by the register allocator to the
411 // instruction stream.
412 //----------------------------------------------------------------------------
414 //-----------------------------
415 // Utility functions used below
416 //-----------------------------
418 InsertBefore(MachineInstr* newMI,
419 MachineBasicBlock& MBB,
420 MachineBasicBlock::iterator& MII)
422 MII = MBB.insert(MII, newMI);
427 InsertAfter(MachineInstr* newMI,
428 MachineBasicBlock& MBB,
429 MachineBasicBlock::iterator& MII)
431 ++MII; // insert before the next instruction
432 MII = MBB.insert(MII, newMI);
436 SubstituteInPlace(MachineInstr* newMI,
437 MachineBasicBlock& MBB,
438 MachineBasicBlock::iterator MII)
444 PrependInstructions(vector<MachineInstr *> &IBef,
445 MachineBasicBlock& MBB,
446 MachineBasicBlock::iterator& MII,
447 const std::string& msg)
451 MachineInstr* OrigMI = *MII;
452 std::vector<MachineInstr *>::iterator AdIt;
453 for (AdIt = IBef.begin(); AdIt != IBef.end() ; ++AdIt)
456 if (OrigMI) cerr << "For MInst:\n " << *OrigMI;
457 cerr << msg << "PREPENDed instr:\n " << **AdIt << "\n";
459 InsertBefore(*AdIt, MBB, MII);
465 AppendInstructions(std::vector<MachineInstr *> &IAft,
466 MachineBasicBlock& MBB,
467 MachineBasicBlock::iterator& MII,
468 const std::string& msg)
472 MachineInstr* OrigMI = *MII;
473 std::vector<MachineInstr *>::iterator AdIt;
474 for ( AdIt = IAft.begin(); AdIt != IAft.end() ; ++AdIt )
477 if (OrigMI) cerr << "For MInst:\n " << *OrigMI;
478 cerr << msg << "APPENDed instr:\n " << **AdIt << "\n";
480 InsertAfter(*AdIt, MBB, MII);
486 void PhyRegAlloc::updateMachineCode() {
487 // Insert any instructions needed at method entry
488 MachineBasicBlock::iterator MII = MF.front().begin();
489 PrependInstructions(AddedInstrAtEntry.InstrnsBefore, MF.front(), MII,
490 "At function entry: \n");
491 assert(AddedInstrAtEntry.InstrnsAfter.empty() &&
492 "InstrsAfter should be unnecessary since we are just inserting at "
493 "the function entry point here.");
495 for (MachineFunction::iterator BBI = MF.begin(), BBE = MF.end();
498 // iterate over all the machine instructions in BB
499 MachineBasicBlock &MBB = *BBI;
500 for (MachineBasicBlock::iterator MII = MBB.begin();
501 MII != MBB.end(); ++MII) {
503 MachineInstr *MInst = *MII;
504 unsigned Opcode = MInst->getOpCode();
506 // do not process Phis
507 if (TM.getInstrInfo().isDummyPhiInstr(Opcode))
510 // Reset tmp stack positions so they can be reused for each machine instr.
511 MF.getInfo()->popAllTempValues();
513 // Now insert speical instructions (if necessary) for call/return
516 if (TM.getInstrInfo().isCall(Opcode) ||
517 TM.getInstrInfo().isReturn(Opcode)) {
518 AddedInstrns &AI = AddedInstrMap[MInst];
520 if (TM.getInstrInfo().isCall(Opcode))
521 MRI.colorCallArgs(MInst, LRI, &AI, *this, MBB.getBasicBlock());
522 else if (TM.getInstrInfo().isReturn(Opcode))
523 MRI.colorRetValue(MInst, LRI, &AI);
526 // Set the registers for operands in the machine instruction
527 // if a register was successfully allocated. If not, insert
528 // code to spill the register value.
530 for (unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum)
532 MachineOperand& Op = MInst->getOperand(OpNum);
533 if (Op.getType() == MachineOperand::MO_VirtualRegister ||
534 Op.getType() == MachineOperand::MO_CCRegister)
536 const Value *const Val = Op.getVRegValue();
538 LiveRange *const LR = LRI.getLiveRangeForValue(Val);
539 if (!LR) // consts or labels will have no live range
541 // if register is not allocated, mark register as invalid
542 if (Op.getAllocatedRegNum() == -1)
543 MInst->SetRegForOperand(OpNum, MRI.getInvalidRegNum());
548 MInst->SetRegForOperand(OpNum,
549 MRI.getUnifiedRegNum(LR->getRegClass()->getID(),
552 // LR did NOT receive a color (register). Insert spill code.
553 insertCode4SpilledLR(LR, MInst, MBB.getBasicBlock(), OpNum);
555 } // for each operand
557 // Now add instructions that the register allocator inserts before/after
558 // this machine instructions (done only for calls/rets/incoming args)
559 // We do this here, to ensure that spill for an instruction is inserted
560 // closest as possible to an instruction (see above insertCode4Spill...)
562 // First, if the instruction in the delay slot of a branch needs
563 // instructions inserted, move it out of the delay slot and before the
564 // branch because putting code before or after it would be VERY BAD!
566 unsigned bumpIteratorBy = 0;
567 if (MII != MBB.begin())
568 if (unsigned predDelaySlots =
569 TM.getInstrInfo().getNumDelaySlots((*(MII-1))->getOpCode()))
571 assert(predDelaySlots==1 && "Not handling multiple delay slots!");
572 if (TM.getInstrInfo().isBranch((*(MII-1))->getOpCode())
573 && (AddedInstrMap.count(MInst) ||
574 AddedInstrMap[MInst].InstrnsAfter.size() > 0))
576 // Current instruction is in the delay slot of a branch and it
577 // needs spill code inserted before or after it.
578 // Move it before the preceding branch.
579 InsertBefore(MInst, MBB, --MII);
580 MachineInstr* nopI = BuildMI(TM.getInstrInfo().getNOPOpCode(),1);
581 SubstituteInPlace(nopI, MBB, MII+1); // replace orig with NOP
582 --MII; // point to MInst in new location
583 bumpIteratorBy = 2; // later skip the branch and the NOP!
587 // If there are instructions to be added, *before* this machine
588 // instruction, add them now.
590 if (AddedInstrMap.count(MInst)) {
591 PrependInstructions(AddedInstrMap[MInst].InstrnsBefore, MBB, MII,"");
594 // If there are instructions to be added *after* this machine
595 // instruction, add them now
597 if (!AddedInstrMap[MInst].InstrnsAfter.empty()) {
599 // if there are delay slots for this instruction, the instructions
600 // added after it must really go after the delayed instruction(s)
601 // So, we move the InstrAfter of the current instruction to the
602 // corresponding delayed instruction
604 TM.getInstrInfo().getNumDelaySlots(MInst->getOpCode())) {
606 // Delayed instructions are typically branches or calls. Let's make
607 // sure this is not a branch, otherwise "insert-after" is meaningless,
608 // and should never happen for any reason (spill code, register
610 assert(! TM.getInstrInfo().isBranch(MInst->getOpCode()) &&
611 ! TM.getInstrInfo().isReturn(MInst->getOpCode()) &&
612 "INTERNAL ERROR: Register allocator should not be inserting "
613 "any code after a branch or return!");
615 move2DelayedInstr(MInst, *(MII+delay) );
618 // Here we can add the "instructions after" to the current
619 // instruction since there are no delay slots for this instruction
620 AppendInstructions(AddedInstrMap[MInst].InstrnsAfter, MBB, MII,"");
624 // If we mucked with the instruction order above, adjust the loop iterator
626 MII = MII + bumpIteratorBy;
628 } // for each machine instruction
634 //----------------------------------------------------------------------------
635 // This method inserts spill code for AN operand whose LR was spilled.
636 // This method may be called several times for a single machine instruction
637 // if it contains many spilled operands. Each time it is called, it finds
638 // a register which is not live at that instruction and also which is not
639 // used by other spilled operands of the same instruction. Then it uses
640 // this register temporarily to accomodate the spilled value.
641 //----------------------------------------------------------------------------
642 void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
644 const BasicBlock *BB,
645 const unsigned OpNum) {
647 assert((! TM.getInstrInfo().isCall(MInst->getOpCode()) || OpNum == 0) &&
648 "Outgoing arg of a call must be handled elsewhere (func arg ok)");
649 assert(! TM.getInstrInfo().isReturn(MInst->getOpCode()) &&
650 "Return value of a ret must be handled elsewhere");
652 MachineOperand& Op = MInst->getOperand(OpNum);
653 bool isDef = Op.opIsDefOnly();
654 bool isDefAndUse = Op.opIsDefAndUse();
655 unsigned RegType = MRI.getRegType(LR);
656 int SpillOff = LR->getSpillOffFromFP();
657 RegClass *RC = LR->getRegClass();
658 const ValueSet &LVSetBef = LVI->getLiveVarSetBeforeMInst(MInst, BB);
660 MF.getInfo()->pushTempValue(MRI.getSpilledRegSize(RegType) );
662 vector<MachineInstr*> MIBef, MIAft;
663 vector<MachineInstr*> AdIMid;
665 // Choose a register to hold the spilled value. This may insert code
666 // before and after MInst to free up the value. If so, this code should
667 // be first and last in the spill sequence before/after MInst.
668 int TmpRegU = getUsableUniRegAtMI(RegType, &LVSetBef, MInst, MIBef, MIAft);
670 // Set the operand first so that it this register does not get used
671 // as a scratch register for later calls to getUsableUniRegAtMI below
672 MInst->SetRegForOperand(OpNum, TmpRegU);
674 // get the added instructions for this instruction
675 AddedInstrns &AI = AddedInstrMap[MInst];
677 // We may need a scratch register to copy the spilled value to/from memory.
678 // This may itself have to insert code to free up a scratch register.
679 // Any such code should go before (after) the spill code for a load (store).
680 int scratchRegType = -1;
682 if (MRI.regTypeNeedsScratchReg(RegType, scratchRegType))
684 scratchReg = getUsableUniRegAtMI(scratchRegType, &LVSetBef,
685 MInst, MIBef, MIAft);
686 assert(scratchReg != MRI.getInvalidRegNum());
687 MInst->insertUsedReg(scratchReg);
690 if (!isDef || isDefAndUse) {
691 // for a USE, we have to load the value of LR from stack to a TmpReg
692 // and use the TmpReg as one operand of instruction
694 // actual loading instruction(s)
695 MRI.cpMem2RegMI(AdIMid, MRI.getFramePointer(), SpillOff, TmpRegU, RegType,
698 // the actual load should be after the instructions to free up TmpRegU
699 MIBef.insert(MIBef.end(), AdIMid.begin(), AdIMid.end());
703 if (isDef) { // if this is a Def
704 // for a DEF, we have to store the value produced by this instruction
705 // on the stack position allocated for this LR
707 // actual storing instruction(s)
708 MRI.cpReg2MemMI(AdIMid, TmpRegU, MRI.getFramePointer(), SpillOff, RegType,
711 MIAft.insert(MIAft.begin(), AdIMid.begin(), AdIMid.end());
714 // Finally, insert the entire spill code sequences before/after MInst
715 AI.InstrnsBefore.insert(AI.InstrnsBefore.end(), MIBef.begin(), MIBef.end());
716 AI.InstrnsAfter.insert(AI.InstrnsAfter.begin(), MIAft.begin(), MIAft.end());
719 cerr << "\nFor Inst:\n " << *MInst;
720 cerr << "SPILLED LR# " << LR->getUserIGNode()->getIndex();
721 cerr << "; added Instructions:";
722 for_each(MIBef.begin(), MIBef.end(), std::mem_fun(&MachineInstr::dump));
723 for_each(MIAft.begin(), MIAft.end(), std::mem_fun(&MachineInstr::dump));
728 //----------------------------------------------------------------------------
729 // We can use the following method to get a temporary register to be used
730 // BEFORE any given machine instruction. If there is a register available,
731 // this method will simply return that register and set MIBef = MIAft = NULL.
732 // Otherwise, it will return a register and MIAft and MIBef will contain
733 // two instructions used to free up this returned register.
734 // Returned register number is the UNIFIED register number
735 //----------------------------------------------------------------------------
737 int PhyRegAlloc::getUsableUniRegAtMI(const int RegType,
738 const ValueSet *LVSetBef,
740 std::vector<MachineInstr*>& MIBef,
741 std::vector<MachineInstr*>& MIAft) {
743 RegClass* RC = getRegClassByID(MRI.getRegClassIDOfRegType(RegType));
745 int RegU = getUnusedUniRegAtMI(RC, MInst, LVSetBef);
748 // we couldn't find an unused register. Generate code to free up a reg by
749 // saving it on stack and restoring after the instruction
751 int TmpOff = MF.getInfo()->pushTempValue(MRI.getSpilledRegSize(RegType));
753 RegU = getUniRegNotUsedByThisInst(RC, MInst);
755 // Check if we need a scratch register to copy this register to memory.
756 int scratchRegType = -1;
757 if (MRI.regTypeNeedsScratchReg(RegType, scratchRegType))
759 int scratchReg = getUsableUniRegAtMI(scratchRegType, LVSetBef,
760 MInst, MIBef, MIAft);
761 assert(scratchReg != MRI.getInvalidRegNum());
763 // We may as well hold the value in the scratch register instead
764 // of copying it to memory and back. But we have to mark the
765 // register as used by this instruction, so it does not get used
766 // as a scratch reg. by another operand or anyone else.
767 MInst->insertUsedReg(scratchReg);
768 MRI.cpReg2RegMI(MIBef, RegU, scratchReg, RegType);
769 MRI.cpReg2RegMI(MIAft, scratchReg, RegU, RegType);
772 { // the register can be copied directly to/from memory so do it.
773 MRI.cpReg2MemMI(MIBef, RegU, MRI.getFramePointer(), TmpOff, RegType);
774 MRI.cpMem2RegMI(MIAft, MRI.getFramePointer(), TmpOff, RegU, RegType);
781 //----------------------------------------------------------------------------
782 // This method is called to get a new unused register that can be used to
783 // accomodate a spilled value.
784 // This method may be called several times for a single machine instruction
785 // if it contains many spilled operands. Each time it is called, it finds
786 // a register which is not live at that instruction and also which is not
787 // used by other spilled operands of the same instruction.
788 // Return register number is relative to the register class. NOT
790 //----------------------------------------------------------------------------
791 int PhyRegAlloc::getUnusedUniRegAtMI(RegClass *RC,
792 const MachineInstr *MInst,
793 const ValueSet *LVSetBef) {
795 unsigned NumAvailRegs = RC->getNumOfAvailRegs();
797 std::vector<bool> &IsColorUsedArr = RC->getIsColorUsedArr();
799 for (unsigned i=0; i < NumAvailRegs; i++) // Reset array
800 IsColorUsedArr[i] = false;
802 ValueSet::const_iterator LIt = LVSetBef->begin();
804 // for each live var in live variable set after machine inst
805 for ( ; LIt != LVSetBef->end(); ++LIt) {
807 // get the live range corresponding to live var
808 LiveRange *const LRofLV = LRI.getLiveRangeForValue(*LIt );
810 // LR can be null if it is a const since a const
811 // doesn't have a dominating def - see Assumptions above
812 if (LRofLV && LRofLV->getRegClass() == RC && LRofLV->hasColor() )
813 IsColorUsedArr[ LRofLV->getColor() ] = true;
816 // It is possible that one operand of this MInst was already spilled
817 // and it received some register temporarily. If that's the case,
818 // it is recorded in machine operand. We must skip such registers.
820 setRelRegsUsedByThisInst(RC, MInst);
822 for (unsigned c=0; c < NumAvailRegs; c++) // find first unused color
823 if (!IsColorUsedArr[c])
824 return MRI.getUnifiedRegNum(RC->getID(), c);
830 //----------------------------------------------------------------------------
831 // Get any other register in a register class, other than what is used
832 // by operands of a machine instruction. Returns the unified reg number.
833 //----------------------------------------------------------------------------
834 int PhyRegAlloc::getUniRegNotUsedByThisInst(RegClass *RC,
835 const MachineInstr *MInst) {
837 vector<bool> &IsColorUsedArr = RC->getIsColorUsedArr();
838 unsigned NumAvailRegs = RC->getNumOfAvailRegs();
840 for (unsigned i=0; i < NumAvailRegs ; i++) // Reset array
841 IsColorUsedArr[i] = false;
843 setRelRegsUsedByThisInst(RC, MInst);
845 for (unsigned c=0; c < RC->getNumOfAvailRegs(); c++)// find first unused color
846 if (!IsColorUsedArr[c])
847 return MRI.getUnifiedRegNum(RC->getID(), c);
849 assert(0 && "FATAL: No free register could be found in reg class!!");
854 //----------------------------------------------------------------------------
855 // This method modifies the IsColorUsedArr of the register class passed to it.
856 // It sets the bits corresponding to the registers used by this machine
857 // instructions. Both explicit and implicit operands are set.
858 //----------------------------------------------------------------------------
859 void PhyRegAlloc::setRelRegsUsedByThisInst(RegClass *RC,
860 const MachineInstr *MInst ) {
862 vector<bool> &IsColorUsedArr = RC->getIsColorUsedArr();
864 // Add the registers already marked as used by the instruction.
865 // This should include any scratch registers that are used to save
866 // values across the instruction (e.g., for saving state register values).
867 const vector<bool> ®sUsed = MInst->getRegsUsed();
868 for (unsigned i = 0, e = regsUsed.size(); i != e; ++i)
870 unsigned classId = 0;
871 int classRegNum = MRI.getClassRegNum(i, classId);
872 if (RC->getID() == classId)
874 assert(classRegNum < (int) IsColorUsedArr.size() &&
875 "Illegal register number for this reg class?");
876 IsColorUsedArr[classRegNum] = true;
880 // Now add registers allocated to the live ranges of values used in
881 // the instruction. These are not yet recorded in the instruction.
882 for (unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum)
884 const MachineOperand& Op = MInst->getOperand(OpNum);
886 if (Op.getType() == MachineOperand::MO_VirtualRegister ||
887 Op.getType() == MachineOperand::MO_CCRegister)
888 if (const Value* Val = Op.getVRegValue())
889 if (MRI.getRegClassIDOfType(Val->getType()) == RC->getID())
890 if (Op.getAllocatedRegNum() == -1)
891 if (LiveRange *LROfVal = LRI.getLiveRangeForValue(Val))
892 if (LROfVal->hasColor() )
893 // this operand is in a LR that received a color
894 IsColorUsedArr[LROfVal->getColor()] = true;
897 // If there are implicit references, mark their allocated regs as well
899 for (unsigned z=0; z < MInst->getNumImplicitRefs(); z++)
901 LRofImpRef = LRI.getLiveRangeForValue(MInst->getImplicitRef(z)))
902 if (LRofImpRef->hasColor())
903 // this implicit reference is in a LR that received a color
904 IsColorUsedArr[LRofImpRef->getColor()] = true;
908 //----------------------------------------------------------------------------
909 // If there are delay slots for an instruction, the instructions
910 // added after it must really go after the delayed instruction(s).
911 // So, we move the InstrAfter of that instruction to the
912 // corresponding delayed instruction using the following method.
914 //----------------------------------------------------------------------------
915 void PhyRegAlloc::move2DelayedInstr(const MachineInstr *OrigMI,
916 const MachineInstr *DelayedMI) {
918 // "added after" instructions of the original instr
919 std::vector<MachineInstr *> &OrigAft = AddedInstrMap[OrigMI].InstrnsAfter;
921 // "added instructions" of the delayed instr
922 AddedInstrns &DelayAdI = AddedInstrMap[DelayedMI];
924 // "added after" instructions of the delayed instr
925 std::vector<MachineInstr *> &DelayedAft = DelayAdI.InstrnsAfter;
927 // go thru all the "added after instructions" of the original instruction
928 // and append them to the "addded after instructions" of the delayed
930 DelayedAft.insert(DelayedAft.end(), OrigAft.begin(), OrigAft.end());
932 // empty the "added after instructions" of the original instruction
936 //----------------------------------------------------------------------------
937 // This method prints the code with registers after register allocation is
939 //----------------------------------------------------------------------------
940 void PhyRegAlloc::printMachineCode()
943 cerr << "\n;************** Function " << Fn->getName()
944 << " *****************\n";
946 for (MachineFunction::iterator BBI = MF.begin(), BBE = MF.end();
948 cerr << "\n"; printLabel(BBI->getBasicBlock()); cerr << ": ";
950 // get the iterator for machine instructions
951 MachineBasicBlock& MBB = *BBI;
952 MachineBasicBlock::iterator MII = MBB.begin();
954 // iterate over all the machine instructions in BB
955 for ( ; MII != MBB.end(); ++MII) {
956 MachineInstr *MInst = *MII;
959 cerr << TM.getInstrInfo().getName(MInst->getOpCode());
961 for (unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
962 MachineOperand& Op = MInst->getOperand(OpNum);
964 if (Op.getType() == MachineOperand::MO_VirtualRegister ||
965 Op.getType() == MachineOperand::MO_CCRegister /*||
966 Op.getType() == MachineOperand::MO_PCRelativeDisp*/ ) {
968 const Value *const Val = Op.getVRegValue () ;
969 // ****this code is temporary till NULL Values are fixed
971 cerr << "\t<*NULL*>";
975 // if a label or a constant
976 if (isa<BasicBlock>(Val)) {
977 cerr << "\t"; printLabel( Op.getVRegValue () );
979 // else it must be a register value
980 const int RegNum = Op.getAllocatedRegNum();
982 cerr << "\t" << "%" << MRI.getUnifiedRegName( RegNum );
984 cerr << "(" << Val->getName() << ")";
986 cerr << "(" << Val << ")";
988 if (Op.opIsDefOnly() || Op.opIsDefAndUse())
991 const LiveRange *LROfVal = LRI.getLiveRangeForValue(Val);
993 if (LROfVal->hasSpillOffset() )
998 else if (Op.getType() == MachineOperand::MO_MachineRegister) {
999 cerr << "\t" << "%" << MRI.getUnifiedRegName(Op.getMachineRegNum());
1003 cerr << "\t" << Op; // use dump field
1008 unsigned NumOfImpRefs = MInst->getNumImplicitRefs();
1009 if (NumOfImpRefs > 0) {
1010 cerr << "\tImplicit:";
1012 for (unsigned z=0; z < NumOfImpRefs; z++)
1013 cerr << RAV(MInst->getImplicitRef(z)) << "\t";
1016 } // for all machine instructions
1026 //----------------------------------------------------------------------------
1028 //----------------------------------------------------------------------------
1029 void PhyRegAlloc::colorIncomingArgs()
1031 MRI.colorMethodArgs(Fn, LRI, &AddedInstrAtEntry);
1035 //----------------------------------------------------------------------------
1036 // Used to generate a label for a basic block
1037 //----------------------------------------------------------------------------
1038 void PhyRegAlloc::printLabel(const Value *Val) {
1040 cerr << Val->getName();
1042 cerr << "Label" << Val;
1046 //----------------------------------------------------------------------------
1047 // This method calls setSugColorUsable method of each live range. This
1048 // will determine whether the suggested color of LR is really usable.
1049 // A suggested color is not usable when the suggested color is volatile
1050 // AND when there are call interferences
1051 //----------------------------------------------------------------------------
1053 void PhyRegAlloc::markUnusableSugColors()
1055 // hash map iterator
1056 LiveRangeMapType::const_iterator HMI = (LRI.getLiveRangeMap())->begin();
1057 LiveRangeMapType::const_iterator HMIEnd = (LRI.getLiveRangeMap())->end();
1059 for (; HMI != HMIEnd ; ++HMI ) {
1061 LiveRange *L = HMI->second; // get the LiveRange
1063 if (L->hasSuggestedColor()) {
1064 int RCID = L->getRegClass()->getID();
1065 if (MRI.isRegVolatile( RCID, L->getSuggestedColor()) &&
1066 L->isCallInterference() )
1067 L->setSuggestedColorUsable( false );
1069 L->setSuggestedColorUsable( true );
1071 } // if L->hasSuggestedColor()
1073 } // for all LR's in hash map
1078 //----------------------------------------------------------------------------
1079 // The following method will set the stack offsets of the live ranges that
1080 // are decided to be spillled. This must be called just after coloring the
1081 // LRs using the graph coloring algo. For each live range that is spilled,
1082 // this method allocate a new spill position on the stack.
1083 //----------------------------------------------------------------------------
1085 void PhyRegAlloc::allocateStackSpace4SpilledLRs() {
1086 if (DEBUG_RA) cerr << "\nSetting LR stack offsets for spills...\n";
1088 LiveRangeMapType::const_iterator HMI = LRI.getLiveRangeMap()->begin();
1089 LiveRangeMapType::const_iterator HMIEnd = LRI.getLiveRangeMap()->end();
1091 for ( ; HMI != HMIEnd ; ++HMI) {
1092 if (HMI->first && HMI->second) {
1093 LiveRange *L = HMI->second; // get the LiveRange
1094 if (!L->hasColor()) { // NOTE: ** allocating the size of long Type **
1095 int stackOffset = MF.getInfo()->allocateSpilledValue(Type::LongTy);
1096 L->setSpillOffFromFP(stackOffset);
1098 cerr << " LR# " << L->getUserIGNode()->getIndex()
1099 << ": stack-offset = " << stackOffset << "\n";
1102 } // for all LR's in hash map
1107 //----------------------------------------------------------------------------
1108 // The entry pont to Register Allocation
1109 //----------------------------------------------------------------------------
1111 void PhyRegAlloc::allocateRegisters()
1114 // make sure that we put all register classes into the RegClassList
1115 // before we call constructLiveRanges (now done in the constructor of
1116 // PhyRegAlloc class).
1118 LRI.constructLiveRanges(); // create LR info
1120 if (DEBUG_RA >= RA_DEBUG_LiveRanges)
1121 LRI.printLiveRanges();
1123 createIGNodeListsAndIGs(); // create IGNode list and IGs
1125 buildInterferenceGraphs(); // build IGs in all reg classes
1128 if (DEBUG_RA >= RA_DEBUG_LiveRanges) {
1129 // print all LRs in all reg classes
1130 for ( unsigned rc=0; rc < NumOfRegClasses ; rc++)
1131 RegClassList[rc]->printIGNodeList();
1133 // print IGs in all register classes
1134 for ( unsigned rc=0; rc < NumOfRegClasses ; rc++)
1135 RegClassList[rc]->printIG();
1138 LRI.coalesceLRs(); // coalesce all live ranges
1140 if (DEBUG_RA >= RA_DEBUG_LiveRanges) {
1141 // print all LRs in all reg classes
1142 for (unsigned rc=0; rc < NumOfRegClasses; rc++)
1143 RegClassList[rc]->printIGNodeList();
1145 // print IGs in all register classes
1146 for (unsigned rc=0; rc < NumOfRegClasses; rc++)
1147 RegClassList[rc]->printIG();
1151 // mark un-usable suggested color before graph coloring algorithm.
1152 // When this is done, the graph coloring algo will not reserve
1153 // suggested color unnecessarily - they can be used by another LR
1155 markUnusableSugColors();
1157 // color all register classes using the graph coloring algo
1158 for (unsigned rc=0; rc < NumOfRegClasses ; rc++)
1159 RegClassList[rc]->colorAllRegs();
1161 // Atter graph coloring, if some LRs did not receive a color (i.e, spilled)
1162 // a poistion for such spilled LRs
1164 allocateStackSpace4SpilledLRs();
1166 MF.getInfo()->popAllTempValues(); // TODO **Check
1168 // color incoming args - if the correct color was not received
1169 // insert code to copy to the correct register
1171 colorIncomingArgs();
1173 // Now update the machine code with register names and add any
1174 // additional code inserted by the register allocator to the instruction
1177 updateMachineCode();
1180 cerr << "\n**** Machine Code After Register Allocation:\n\n";