1 //===---------------------------------------------------------------------===//
3 Common register allocation / spilling problem:
21 and then "merge" mul and mov:
29 It also increase the likelyhood the store may become dead.
31 //===---------------------------------------------------------------------===//
33 I think we should have a "hasSideEffects" flag (which is automatically set for
34 stuff that "isLoad" "isCall" etc), and the remat pass should eventually be able
35 to remat any instruction that has no side effects, if it can handle it and if
38 For now, I'd suggest having the remat stuff work like this:
40 1. I need to spill/reload this thing.
41 2. Check to see if it has side effects.
42 3. Check to see if it is simple enough: e.g. it only has one register
43 destination and no register input.
44 4. If so, clone the instruction, do the xform, etc.
46 Advantages of this are:
48 1. the .td file describes the behavior of the instructions, not the way the
49 algorithm should work.
50 2. as remat gets smarter in the future, we shouldn't have to be changing the .td
52 3. it is easier to explain what the flag means in the .td file, because you
53 don't have to pull in the explanation of how the current remat algo works.
55 Some potential added complexities:
57 1. Some instructions have to be glued to it's predecessor or successor. All of
58 the PC relative instructions and condition code setting instruction. We could
59 mark them as hasSideEffects, but that's not quite right. PC relative loads
60 from constantpools can be remat'ed, for example. But it requires more than
61 just cloning the instruction. Some instructions can be remat'ed but it
62 expands to more than one instruction. But allocator will have to make a
65 4. As stated in 3, not as simple as cloning in some cases. The target will have
66 to decide how to remat it. For example, an ARM 2-piece constant generation
67 instruction is remat'ed as a load from constantpool.
69 //===---------------------------------------------------------------------===//
73 %reg1037 = ADDri %reg1039, 1
74 %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
75 Successors according to CFG: 0x8b03bf0 (#5)
77 bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
78 Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
79 %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>
81 Note ADDri is not a two-address instruction. However, its result %reg1037 is an
82 operand of the PHI node in bb76 and its operand %reg1039 is the result of the
83 PHI node. We should treat it as a two-address code and make sure the ADDri is
84 scheduled after any node that reads %reg1039.
86 //===---------------------------------------------------------------------===//
88 Use local info (i.e. register scavenger) to assign it a free register to allow
99 //===---------------------------------------------------------------------===//
101 LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
115 Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
116 to implement proper re-materialization to handle this:
123 R1 = X + 4 @ re-materialized
126 R2 = X + 7 @ re-materialized
129 R3 = X + 15 @ re-materialized
132 Furthermore, with re-association, we can enable sharing:
145 //===---------------------------------------------------------------------===//
147 It's not always a good idea to choose rematerialization over spilling. If all
148 the load / store instructions would be folded then spilling is cheaper because
149 it won't require new live intervals / registers. See 2003-05-31-LongShifts for
152 //===---------------------------------------------------------------------===//
154 With a copying garbage collector, derived pointers must not be retained across
155 collector safe points; the collector could move the objects and invalidate the
156 derived pointer. This is bad enough in the first place, but safe points can
157 crop up unpredictably. Consider:
159 %array = load { i32, [0 x %obj] }** %array_addr
160 %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
161 %old = load %obj** %nth_el
163 store %obj* %new, %obj** %nth_el
165 If the i64 division is lowered to a libcall, then a safe point will (must)
166 appear for the call site. If a collection occurs, %array and %nth_el no longer
167 point into the correct object.
169 The fix for this is to copy address calculations so that dependent pointers
170 are never live across safe point boundaries. But the loads cannot be copied
171 like this if there was an intervening store, so may be hard to get right.
173 Only a concurrent mutator can trigger a collection at the libcall safe point.
174 So single-threaded programs do not have this requirement, even with a copying
175 collector. Still, LLVM optimizations would probably undo a front-end's careful
178 //===---------------------------------------------------------------------===//
180 The ocaml frametable structure supports liveness information. It would be good
183 //===---------------------------------------------------------------------===//
185 The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
186 revisited. The check is there to work around a misuse of directives in inline
189 //===---------------------------------------------------------------------===//
191 It would be good to detect collector/target compatibility instead of silently
192 doing the wrong thing.
194 //===---------------------------------------------------------------------===//
196 It would be really nice to be able to write patterns in .td files for copies,
197 which would eliminate a bunch of explicit predicates on them (e.g. no side
198 effects). Once this is in place, it would be even better to have tblgen
199 synthesize the various copy insertion/inspection methods in TargetInstrInfo.
201 //===---------------------------------------------------------------------===//
203 Stack coloring improvments:
205 1. Do proper LiveStackAnalysis on all stack objects including those which are
207 2. Reorder objects to fill in gaps between objects.
208 e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4