1 //===-- PreAllocSplitting.cpp - Pre-allocation Interval Spltting Pass. ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the machine instruction level pre-register allocation
11 // live interval splitting pass. It finds live interval barriers, i.e.
12 // instructions which will kill all physical registers in certain register
13 // classes, and split all live intervals which cross the barrier.
15 //===----------------------------------------------------------------------===//
17 #define DEBUG_TYPE "pre-alloc-split"
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "llvm/CodeGen/LiveStackAnalysis.h"
20 #include "llvm/CodeGen/MachineDominators.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunctionPass.h"
23 #include "llvm/CodeGen/MachineLoopInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/CodeGen/RegisterCoalescer.h"
27 #include "llvm/Target/TargetInstrInfo.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include "llvm/Target/TargetOptions.h"
30 #include "llvm/Target/TargetRegisterInfo.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/ADT/DenseMap.h"
34 #include "llvm/ADT/DepthFirstIterator.h"
35 #include "llvm/ADT/SmallPtrSet.h"
36 #include "llvm/ADT/Statistic.h"
39 static cl::opt<int> PreSplitLimit("pre-split-limit", cl::init(-1), cl::Hidden);
41 STATISTIC(NumSplits, "Number of intervals split");
42 STATISTIC(NumRemats, "Number of intervals split by rematerialization");
43 STATISTIC(NumFolds, "Number of intervals split with spill folding");
44 STATISTIC(NumRenumbers, "Number of intervals renumbered into new registers");
47 class VISIBILITY_HIDDEN PreAllocSplitting : public MachineFunctionPass {
48 MachineFunction *CurrMF;
49 const TargetMachine *TM;
50 const TargetInstrInfo *TII;
51 MachineFrameInfo *MFI;
52 MachineRegisterInfo *MRI;
56 // Barrier - Current barrier being processed.
57 MachineInstr *Barrier;
59 // BarrierMBB - Basic block where the barrier resides in.
60 MachineBasicBlock *BarrierMBB;
62 // Barrier - Current barrier index.
65 // CurrLI - Current live interval being split.
68 // CurrSLI - Current stack slot live interval.
69 LiveInterval *CurrSLI;
71 // CurrSValNo - Current val# for the stack slot live interval.
74 // IntervalSSMap - A map from live interval to spill slots.
75 DenseMap<unsigned, int> IntervalSSMap;
77 // Def2SpillMap - A map from a def instruction index to spill index.
78 DenseMap<unsigned, unsigned> Def2SpillMap;
82 PreAllocSplitting() : MachineFunctionPass(&ID) {}
84 virtual bool runOnMachineFunction(MachineFunction &MF);
86 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
87 AU.addRequired<LiveIntervals>();
88 AU.addPreserved<LiveIntervals>();
89 AU.addRequired<LiveStacks>();
90 AU.addPreserved<LiveStacks>();
91 AU.addPreserved<RegisterCoalescer>();
93 AU.addPreservedID(StrongPHIEliminationID);
95 AU.addPreservedID(PHIEliminationID);
96 AU.addRequired<MachineDominatorTree>();
97 AU.addRequired<MachineLoopInfo>();
98 AU.addPreserved<MachineDominatorTree>();
99 AU.addPreserved<MachineLoopInfo>();
100 MachineFunctionPass::getAnalysisUsage(AU);
103 virtual void releaseMemory() {
104 IntervalSSMap.clear();
105 Def2SpillMap.clear();
108 virtual const char *getPassName() const {
109 return "Pre-Register Allocaton Live Interval Splitting";
112 /// print - Implement the dump method.
113 virtual void print(std::ostream &O, const Module* M = 0) const {
117 void print(std::ostream *O, const Module* M = 0) const {
122 MachineBasicBlock::iterator
123 findNextEmptySlot(MachineBasicBlock*, MachineInstr*,
126 MachineBasicBlock::iterator
127 findSpillPoint(MachineBasicBlock*, MachineInstr*, MachineInstr*,
128 SmallPtrSet<MachineInstr*, 4>&, unsigned&);
130 MachineBasicBlock::iterator
131 findRestorePoint(MachineBasicBlock*, MachineInstr*, unsigned,
132 SmallPtrSet<MachineInstr*, 4>&, unsigned&);
134 int CreateSpillStackSlot(unsigned, const TargetRegisterClass *);
136 bool IsAvailableInStack(MachineBasicBlock*, unsigned, unsigned, unsigned,
137 unsigned&, int&) const;
139 void UpdateSpillSlotInterval(VNInfo*, unsigned, unsigned);
141 VNInfo* UpdateRegisterInterval(VNInfo*, unsigned, unsigned);
143 bool ShrinkWrapToLastUse(MachineBasicBlock*, VNInfo*,
144 SmallVector<MachineOperand*, 4>&,
145 SmallPtrSet<MachineInstr*, 4>&);
147 void ShrinkWrapLiveInterval(VNInfo*, MachineBasicBlock*, MachineBasicBlock*,
148 MachineBasicBlock*, SmallPtrSet<MachineBasicBlock*, 8>&,
149 DenseMap<MachineBasicBlock*, SmallVector<MachineOperand*, 4> >&,
150 DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 4> >&,
151 SmallVector<MachineBasicBlock*, 4>&);
153 bool SplitRegLiveInterval(LiveInterval*);
155 bool SplitRegLiveIntervals(const TargetRegisterClass **);
157 void RepairLiveInterval(LiveInterval* CurrLI, VNInfo* ValNo,
158 MachineInstr* DefMI, unsigned RestoreIdx);
160 bool createsNewJoin(LiveRange* LR, MachineBasicBlock* DefMBB,
161 MachineBasicBlock* BarrierMBB);
162 bool Rematerialize(unsigned vreg, VNInfo* ValNo,
164 MachineBasicBlock::iterator RestorePt,
166 SmallPtrSet<MachineInstr*, 4>& RefsInMBB);
167 MachineInstr* FoldSpill(unsigned vreg, const TargetRegisterClass* RC,
169 MachineInstr* Barrier,
170 MachineBasicBlock* MBB,
172 SmallPtrSet<MachineInstr*, 4>& RefsInMBB);
173 void RenumberValno(VNInfo* VN);
174 void ReconstructLiveInterval(LiveInterval* LI);
175 VNInfo* PerformPHIConstruction(MachineBasicBlock::iterator use,
176 MachineBasicBlock* MBB,
178 DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 2> >& Defs,
179 DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 2> >& Uses,
180 DenseMap<MachineInstr*, VNInfo*>& NewVNs,
181 DenseMap<MachineBasicBlock*, VNInfo*>& LiveOut,
182 DenseMap<MachineBasicBlock*, VNInfo*>& Phis,
183 bool toplevel, bool intrablock);
185 } // end anonymous namespace
187 char PreAllocSplitting::ID = 0;
189 static RegisterPass<PreAllocSplitting>
190 X("pre-alloc-splitting", "Pre-Register Allocation Live Interval Splitting");
192 const PassInfo *const llvm::PreAllocSplittingID = &X;
195 /// findNextEmptySlot - Find a gap after the given machine instruction in the
196 /// instruction index map. If there isn't one, return end().
197 MachineBasicBlock::iterator
198 PreAllocSplitting::findNextEmptySlot(MachineBasicBlock *MBB, MachineInstr *MI,
199 unsigned &SpotIndex) {
200 MachineBasicBlock::iterator MII = MI;
201 if (++MII != MBB->end()) {
202 unsigned Index = LIs->findGapBeforeInstr(LIs->getInstructionIndex(MII));
211 /// findSpillPoint - Find a gap as far away from the given MI that's suitable
212 /// for spilling the current live interval. The index must be before any
213 /// defs and uses of the live interval register in the mbb. Return begin() if
215 MachineBasicBlock::iterator
216 PreAllocSplitting::findSpillPoint(MachineBasicBlock *MBB, MachineInstr *MI,
218 SmallPtrSet<MachineInstr*, 4> &RefsInMBB,
219 unsigned &SpillIndex) {
220 MachineBasicBlock::iterator Pt = MBB->begin();
222 // Go top down if RefsInMBB is empty.
223 if (RefsInMBB.empty() && !DefMI) {
224 MachineBasicBlock::iterator MII = MBB->begin();
225 MachineBasicBlock::iterator EndPt = MI;
228 unsigned Index = LIs->getInstructionIndex(MII);
229 unsigned Gap = LIs->findGapBeforeInstr(Index);
235 } while (MII != EndPt);
237 MachineBasicBlock::iterator MII = MI;
238 MachineBasicBlock::iterator EndPt = DefMI
239 ? MachineBasicBlock::iterator(DefMI) : MBB->begin();
240 while (MII != EndPt && !RefsInMBB.count(MII)) {
241 unsigned Index = LIs->getInstructionIndex(MII);
242 if (LIs->hasGapBeforeInstr(Index)) {
244 SpillIndex = LIs->findGapBeforeInstr(Index, true);
253 /// findRestorePoint - Find a gap in the instruction index map that's suitable
254 /// for restoring the current live interval value. The index must be before any
255 /// uses of the live interval register in the mbb. Return end() if none is
257 MachineBasicBlock::iterator
258 PreAllocSplitting::findRestorePoint(MachineBasicBlock *MBB, MachineInstr *MI,
260 SmallPtrSet<MachineInstr*, 4> &RefsInMBB,
261 unsigned &RestoreIndex) {
262 // FIXME: Allow spill to be inserted to the beginning of the mbb. Update mbb
263 // begin index accordingly.
264 MachineBasicBlock::iterator Pt = MBB->end();
265 unsigned EndIdx = LIs->getMBBEndIdx(MBB);
267 // Go bottom up if RefsInMBB is empty and the end of the mbb isn't beyond
268 // the last index in the live range.
269 if (RefsInMBB.empty() && LastIdx >= EndIdx) {
270 MachineBasicBlock::iterator MII = MBB->getFirstTerminator();
271 MachineBasicBlock::iterator EndPt = MI;
274 unsigned Index = LIs->getInstructionIndex(MII);
275 unsigned Gap = LIs->findGapBeforeInstr(Index);
282 } while (MII != EndPt);
284 MachineBasicBlock::iterator MII = MI;
286 // FIXME: Limit the number of instructions to examine to reduce
288 while (MII != MBB->end()) {
289 unsigned Index = LIs->getInstructionIndex(MII);
292 unsigned Gap = LIs->findGapBeforeInstr(Index);
297 if (RefsInMBB.count(MII))
306 /// CreateSpillStackSlot - Create a stack slot for the live interval being
307 /// split. If the live interval was previously split, just reuse the same
309 int PreAllocSplitting::CreateSpillStackSlot(unsigned Reg,
310 const TargetRegisterClass *RC) {
312 DenseMap<unsigned, int>::iterator I = IntervalSSMap.find(Reg);
313 if (I != IntervalSSMap.end()) {
316 SS = MFI->CreateStackObject(RC->getSize(), RC->getAlignment());
317 IntervalSSMap[Reg] = SS;
320 // Create live interval for stack slot.
321 CurrSLI = &LSs->getOrCreateInterval(SS);
322 if (CurrSLI->hasAtLeastOneValue())
323 CurrSValNo = CurrSLI->getValNumInfo(0);
325 CurrSValNo = CurrSLI->getNextValue(~0U, 0, LSs->getVNInfoAllocator());
329 /// IsAvailableInStack - Return true if register is available in a split stack
330 /// slot at the specified index.
332 PreAllocSplitting::IsAvailableInStack(MachineBasicBlock *DefMBB,
333 unsigned Reg, unsigned DefIndex,
334 unsigned RestoreIndex, unsigned &SpillIndex,
339 DenseMap<unsigned, int>::iterator I = IntervalSSMap.find(Reg);
340 if (I == IntervalSSMap.end())
342 DenseMap<unsigned, unsigned>::iterator II = Def2SpillMap.find(DefIndex);
343 if (II == Def2SpillMap.end())
346 // If last spill of def is in the same mbb as barrier mbb (where restore will
347 // be), make sure it's not below the intended restore index.
348 // FIXME: Undo the previous spill?
349 assert(LIs->getMBBFromIndex(II->second) == DefMBB);
350 if (DefMBB == BarrierMBB && II->second >= RestoreIndex)
354 SpillIndex = II->second;
358 /// UpdateSpillSlotInterval - Given the specified val# of the register live
359 /// interval being split, and the spill and restore indicies, update the live
360 /// interval of the spill stack slot.
362 PreAllocSplitting::UpdateSpillSlotInterval(VNInfo *ValNo, unsigned SpillIndex,
363 unsigned RestoreIndex) {
364 assert(LIs->getMBBFromIndex(RestoreIndex) == BarrierMBB &&
365 "Expect restore in the barrier mbb");
367 MachineBasicBlock *MBB = LIs->getMBBFromIndex(SpillIndex);
368 if (MBB == BarrierMBB) {
369 // Intra-block spill + restore. We are done.
370 LiveRange SLR(SpillIndex, RestoreIndex, CurrSValNo);
371 CurrSLI->addRange(SLR);
375 SmallPtrSet<MachineBasicBlock*, 4> Processed;
376 unsigned EndIdx = LIs->getMBBEndIdx(MBB);
377 LiveRange SLR(SpillIndex, EndIdx+1, CurrSValNo);
378 CurrSLI->addRange(SLR);
379 Processed.insert(MBB);
381 // Start from the spill mbb, figure out the extend of the spill slot's
383 SmallVector<MachineBasicBlock*, 4> WorkList;
384 const LiveRange *LR = CurrLI->getLiveRangeContaining(SpillIndex);
385 if (LR->end > EndIdx)
386 // If live range extend beyond end of mbb, add successors to work list.
387 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
388 SE = MBB->succ_end(); SI != SE; ++SI)
389 WorkList.push_back(*SI);
391 while (!WorkList.empty()) {
392 MachineBasicBlock *MBB = WorkList.back();
394 if (Processed.count(MBB))
396 unsigned Idx = LIs->getMBBStartIdx(MBB);
397 LR = CurrLI->getLiveRangeContaining(Idx);
398 if (LR && LR->valno == ValNo) {
399 EndIdx = LIs->getMBBEndIdx(MBB);
400 if (Idx <= RestoreIndex && RestoreIndex < EndIdx) {
401 // Spill slot live interval stops at the restore.
402 LiveRange SLR(Idx, RestoreIndex, CurrSValNo);
403 CurrSLI->addRange(SLR);
404 } else if (LR->end > EndIdx) {
405 // Live range extends beyond end of mbb, process successors.
406 LiveRange SLR(Idx, EndIdx+1, CurrSValNo);
407 CurrSLI->addRange(SLR);
408 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
409 SE = MBB->succ_end(); SI != SE; ++SI)
410 WorkList.push_back(*SI);
412 LiveRange SLR(Idx, LR->end, CurrSValNo);
413 CurrSLI->addRange(SLR);
415 Processed.insert(MBB);
420 /// UpdateRegisterInterval - Given the specified val# of the current live
421 /// interval is being split, and the spill and restore indices, update the live
422 /// interval accordingly.
424 PreAllocSplitting::UpdateRegisterInterval(VNInfo *ValNo, unsigned SpillIndex,
425 unsigned RestoreIndex) {
426 assert(LIs->getMBBFromIndex(RestoreIndex) == BarrierMBB &&
427 "Expect restore in the barrier mbb");
429 SmallVector<std::pair<unsigned,unsigned>, 4> Before;
430 SmallVector<std::pair<unsigned,unsigned>, 4> After;
431 SmallVector<unsigned, 4> BeforeKills;
432 SmallVector<unsigned, 4> AfterKills;
433 SmallPtrSet<const LiveRange*, 4> Processed;
435 // First, let's figure out which parts of the live interval is now defined
436 // by the restore, which are defined by the original definition.
437 const LiveRange *LR = CurrLI->getLiveRangeContaining(RestoreIndex);
438 After.push_back(std::make_pair(RestoreIndex, LR->end));
439 if (CurrLI->isKill(ValNo, LR->end))
440 AfterKills.push_back(LR->end);
442 assert(LR->contains(SpillIndex));
443 if (SpillIndex > LR->start) {
444 Before.push_back(std::make_pair(LR->start, SpillIndex));
445 BeforeKills.push_back(SpillIndex);
447 Processed.insert(LR);
449 // Start from the restore mbb, figure out what part of the live interval
450 // are defined by the restore.
451 SmallVector<MachineBasicBlock*, 4> WorkList;
452 MachineBasicBlock *MBB = BarrierMBB;
453 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
454 SE = MBB->succ_end(); SI != SE; ++SI)
455 WorkList.push_back(*SI);
457 SmallPtrSet<MachineBasicBlock*, 4> ProcessedBlocks;
458 ProcessedBlocks.insert(MBB);
460 while (!WorkList.empty()) {
461 MBB = WorkList.back();
463 unsigned Idx = LIs->getMBBStartIdx(MBB);
464 LR = CurrLI->getLiveRangeContaining(Idx);
465 if (LR && LR->valno == ValNo && !Processed.count(LR)) {
466 After.push_back(std::make_pair(LR->start, LR->end));
467 if (CurrLI->isKill(ValNo, LR->end))
468 AfterKills.push_back(LR->end);
469 Idx = LIs->getMBBEndIdx(MBB);
471 // Live range extend beyond at least one mbb. Let's see what other
473 LIs->findReachableMBBs(LR->start, LR->end, WorkList);
475 Processed.insert(LR);
478 ProcessedBlocks.insert(MBB);
480 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
481 SE = MBB->succ_end(); SI != SE; ++SI)
482 if (!ProcessedBlocks.count(*SI))
483 WorkList.push_back(*SI);
486 for (LiveInterval::iterator I = CurrLI->begin(), E = CurrLI->end();
489 if (LR->valno == ValNo && !Processed.count(LR)) {
490 Before.push_back(std::make_pair(LR->start, LR->end));
491 if (CurrLI->isKill(ValNo, LR->end))
492 BeforeKills.push_back(LR->end);
496 // Now create new val#s to represent the live ranges defined by the old def
497 // those defined by the restore.
498 unsigned AfterDef = ValNo->def;
499 MachineInstr *AfterCopy = ValNo->copy;
500 bool HasPHIKill = ValNo->hasPHIKill;
501 CurrLI->removeValNo(ValNo);
502 VNInfo *BValNo = (Before.empty())
504 : CurrLI->getNextValue(AfterDef, AfterCopy, LIs->getVNInfoAllocator());
506 CurrLI->addKills(BValNo, BeforeKills);
508 VNInfo *AValNo = (After.empty())
510 : CurrLI->getNextValue(RestoreIndex, 0, LIs->getVNInfoAllocator());
512 AValNo->hasPHIKill = HasPHIKill;
513 CurrLI->addKills(AValNo, AfterKills);
516 for (unsigned i = 0, e = Before.size(); i != e; ++i) {
517 unsigned Start = Before[i].first;
518 unsigned End = Before[i].second;
519 CurrLI->addRange(LiveRange(Start, End, BValNo));
521 for (unsigned i = 0, e = After.size(); i != e; ++i) {
522 unsigned Start = After[i].first;
523 unsigned End = After[i].second;
524 CurrLI->addRange(LiveRange(Start, End, AValNo));
530 /// ShrinkWrapToLastUse - There are uses of the current live interval in the
531 /// given block, shrink wrap the live interval to the last use (i.e. remove
532 /// from last use to the end of the mbb). In case mbb is the where the barrier
533 /// is, remove from the last use to the barrier.
535 PreAllocSplitting::ShrinkWrapToLastUse(MachineBasicBlock *MBB, VNInfo *ValNo,
536 SmallVector<MachineOperand*, 4> &Uses,
537 SmallPtrSet<MachineInstr*, 4> &UseMIs) {
538 MachineOperand *LastMO = 0;
539 MachineInstr *LastMI = 0;
540 if (MBB != BarrierMBB && Uses.size() == 1) {
541 // Single use, no need to traverse the block. We can't assume this for the
542 // barrier bb though since the use is probably below the barrier.
544 LastMI = LastMO->getParent();
546 MachineBasicBlock::iterator MEE = MBB->begin();
547 MachineBasicBlock::iterator MII;
548 if (MBB == BarrierMBB)
554 MachineInstr *UseMI = &*MII;
555 if (!UseMIs.count(UseMI))
557 for (unsigned i = 0, e = UseMI->getNumOperands(); i != e; ++i) {
558 MachineOperand &MO = UseMI->getOperand(i);
559 if (MO.isReg() && MO.getReg() == CurrLI->reg) {
569 // Cut off live range from last use (or beginning of the mbb if there
570 // are no uses in it) to the end of the mbb.
571 unsigned RangeStart, RangeEnd = LIs->getMBBEndIdx(MBB)+1;
573 RangeStart = LIs->getUseIndex(LIs->getInstructionIndex(LastMI))+1;
574 assert(!LastMO->isKill() && "Last use already terminates the interval?");
577 assert(MBB == BarrierMBB);
578 RangeStart = LIs->getMBBStartIdx(MBB);
580 if (MBB == BarrierMBB)
581 RangeEnd = LIs->getUseIndex(BarrierIdx)+1;
582 CurrLI->removeRange(RangeStart, RangeEnd);
584 CurrLI->addKill(ValNo, RangeStart);
586 // Return true if the last use becomes a new kill.
590 /// PerformPHIConstruction - From properly set up use and def lists, use a PHI
591 /// construction algorithm to compute the ranges and valnos for an interval.
592 VNInfo* PreAllocSplitting::PerformPHIConstruction(
593 MachineBasicBlock::iterator use,
594 MachineBasicBlock* MBB,
596 DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 2> >& Defs,
597 DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 2> >& Uses,
598 DenseMap<MachineInstr*, VNInfo*>& NewVNs,
599 DenseMap<MachineBasicBlock*, VNInfo*>& LiveOut,
600 DenseMap<MachineBasicBlock*, VNInfo*>& Phis,
601 bool toplevel, bool intrablock) {
602 // Return memoized result if it's available.
603 if (intrablock && NewVNs.count(use))
605 else if (!intrablock && LiveOut.count(MBB))
608 // Insert a sentinel into the map (which also acts as the DFS stack) so that
609 // we won't get stuck in infinite recursion when processing a loop.
613 typedef DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 2> > RegMap;
615 // Check if our block contains any uses or defs.
616 bool ContainsDefs = Defs.count(MBB);
617 bool ContainsUses = Uses.count(MBB);
621 // Enumerate the cases of use/def contaning blocks.
622 if (!ContainsDefs && !ContainsUses) {
624 // NOTE: Because this is the fallback case from other cases, we do NOT
625 // assume that we are not intrablock here.
626 if (Phis.count(MBB)) return Phis[MBB];
628 unsigned StartIndex = LIs->getMBBStartIdx(MBB);
630 if (MBB->pred_size() == 1) {
631 Phis[MBB] = ret = PerformPHIConstruction((*MBB->pred_begin())->end(),
632 *(MBB->pred_begin()), LI, Defs,
633 Uses, NewVNs, LiveOut, Phis,
635 unsigned EndIndex = 0;
637 EndIndex = LIs->getInstructionIndex(use);
638 EndIndex = LiveIntervals::getUseIndex(EndIndex);
640 EndIndex = LIs->getMBBEndIdx(MBB);
642 LI->addRange(LiveRange(StartIndex, EndIndex+1, ret));
644 Phis[MBB] = ret = LI->getNextValue(~0U, /*FIXME*/ 0,
645 LIs->getVNInfoAllocator());
646 if (!intrablock) LiveOut[MBB] = ret;
648 // If there are no uses or defs between our starting point and the
649 // beginning of the block, then recursive perform phi construction
650 // on our predecessors.
651 DenseMap<MachineBasicBlock*, VNInfo*> IncomingVNs;
652 for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
653 PE = MBB->pred_end(); PI != PE; ++PI) {
654 VNInfo* Incoming = PerformPHIConstruction((*PI)->end(), *PI, LI, Defs,
655 Uses, NewVNs, LiveOut, Phis,
658 IncomingVNs[*PI] = Incoming;
661 // Otherwise, merge the incoming VNInfos with a phi join. Create a new
662 // VNInfo to represent the joined value.
663 for (DenseMap<MachineBasicBlock*, VNInfo*>::iterator I =
664 IncomingVNs.begin(), E = IncomingVNs.end(); I != E; ++I) {
665 I->second->hasPHIKill = true;
666 unsigned KillIndex = LIs->getMBBEndIdx(I->first);
667 LI->addKill(I->second, KillIndex);
670 unsigned EndIndex = 0;
672 EndIndex = LIs->getInstructionIndex(use);
673 EndIndex = LiveIntervals::getUseIndex(EndIndex);
675 EndIndex = LIs->getMBBEndIdx(MBB);
676 LI->addRange(LiveRange(StartIndex, EndIndex+1, ret));
678 } else if (ContainsDefs && !ContainsUses) {
679 SmallPtrSet<MachineInstr*, 2>& BlockDefs = Defs[MBB];
681 // Search for the def in this block. If we don't find it before the
682 // instruction we care about, go to the fallback case. Note that that
683 // should never happen: this cannot be intrablock, so use should
684 // always be an end() iterator.
685 assert(use == MBB->end() && "No use marked in intrablock");
687 MachineBasicBlock::iterator walker = use;
689 while (walker != MBB->begin())
690 if (BlockDefs.count(walker)) {
695 // Once we've found it, extend its VNInfo to our instruction.
696 unsigned DefIndex = LIs->getInstructionIndex(walker);
697 DefIndex = LiveIntervals::getDefIndex(DefIndex);
698 unsigned EndIndex = LIs->getMBBEndIdx(MBB);
700 ret = NewVNs[walker];
701 LI->addRange(LiveRange(DefIndex, EndIndex+1, ret));
702 } else if (!ContainsDefs && ContainsUses) {
703 SmallPtrSet<MachineInstr*, 2>& BlockUses = Uses[MBB];
705 // Search for the use in this block that precedes the instruction we care
706 // about, going to the fallback case if we don't find it.
708 if (use == MBB->begin())
711 MachineBasicBlock::iterator walker = use;
714 while (walker != MBB->begin())
715 if (BlockUses.count(walker)) {
721 // Must check begin() too.
723 if (BlockUses.count(walker))
729 unsigned UseIndex = LIs->getInstructionIndex(walker);
730 UseIndex = LiveIntervals::getUseIndex(UseIndex);
731 unsigned EndIndex = 0;
733 EndIndex = LIs->getInstructionIndex(use);
734 EndIndex = LiveIntervals::getUseIndex(EndIndex);
736 EndIndex = LIs->getMBBEndIdx(MBB);
738 // Now, recursively phi construct the VNInfo for the use we found,
739 // and then extend it to include the instruction we care about
740 ret = PerformPHIConstruction(walker, MBB, LI, Defs, Uses,
741 NewVNs, LiveOut, Phis, false, true);
743 // FIXME: Need to set kills properly for inter-block stuff.
744 if (LI->isKill(ret, UseIndex)) LI->removeKill(ret, UseIndex);
746 LI->addKill(ret, EndIndex);
748 LI->addRange(LiveRange(UseIndex, EndIndex+1, ret));
749 } else if (ContainsDefs && ContainsUses){
750 SmallPtrSet<MachineInstr*, 2>& BlockDefs = Defs[MBB];
751 SmallPtrSet<MachineInstr*, 2>& BlockUses = Uses[MBB];
753 // This case is basically a merging of the two preceding case, with the
754 // special note that checking for defs must take precedence over checking
755 // for uses, because of two-address instructions.
757 if (use == MBB->begin())
760 MachineBasicBlock::iterator walker = use;
762 bool foundDef = false;
763 bool foundUse = false;
764 while (walker != MBB->begin())
765 if (BlockDefs.count(walker)) {
768 } else if (BlockUses.count(walker)) {
774 // Must check begin() too.
775 if (!foundDef && !foundUse) {
776 if (BlockDefs.count(walker))
778 else if (BlockUses.count(walker))
784 unsigned StartIndex = LIs->getInstructionIndex(walker);
785 StartIndex = foundDef ? LiveIntervals::getDefIndex(StartIndex) :
786 LiveIntervals::getUseIndex(StartIndex);
787 unsigned EndIndex = 0;
789 EndIndex = LIs->getInstructionIndex(use);
790 EndIndex = LiveIntervals::getUseIndex(EndIndex);
792 EndIndex = LIs->getMBBEndIdx(MBB);
795 ret = NewVNs[walker];
797 ret = PerformPHIConstruction(walker, MBB, LI, Defs, Uses,
798 NewVNs, LiveOut, Phis, false, true);
800 if (foundUse && LI->isKill(ret, StartIndex))
801 LI->removeKill(ret, StartIndex);
803 LI->addKill(ret, EndIndex);
806 LI->addRange(LiveRange(StartIndex, EndIndex+1, ret));
809 // Memoize results so we don't have to recompute them.
810 if (!intrablock) LiveOut[MBB] = ret;
811 else NewVNs[use] = ret;
816 /// ReconstructLiveInterval - Recompute a live interval from scratch.
817 void PreAllocSplitting::ReconstructLiveInterval(LiveInterval* LI) {
818 BumpPtrAllocator& Alloc = LIs->getVNInfoAllocator();
820 // Clear the old ranges and valnos;
823 // Cache the uses and defs of the register
824 typedef DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 2> > RegMap;
827 // Keep track of the new VNs we're creating.
828 DenseMap<MachineInstr*, VNInfo*> NewVNs;
829 SmallPtrSet<VNInfo*, 2> PhiVNs;
831 // Cache defs, and create a new VNInfo for each def.
832 for (MachineRegisterInfo::def_iterator DI = MRI->def_begin(LI->reg),
833 DE = MRI->def_end(); DI != DE; ++DI) {
834 Defs[(*DI).getParent()].insert(&*DI);
836 unsigned DefIdx = LIs->getInstructionIndex(&*DI);
837 DefIdx = LiveIntervals::getDefIndex(DefIdx);
839 VNInfo* NewVN = LI->getNextValue(DefIdx, /*FIXME*/ 0, Alloc);
840 NewVNs[&*DI] = NewVN;
843 // Cache uses as a separate pass from actually processing them.
844 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(LI->reg),
845 UE = MRI->use_end(); UI != UE; ++UI)
846 Uses[(*UI).getParent()].insert(&*UI);
848 // Now, actually process every use and use a phi construction algorithm
849 // to walk from it to its reaching definitions, building VNInfos along
851 DenseMap<MachineBasicBlock*, VNInfo*> LiveOut;
852 DenseMap<MachineBasicBlock*, VNInfo*> Phis;
853 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(LI->reg),
854 UE = MRI->use_end(); UI != UE; ++UI) {
855 PerformPHIConstruction(&*UI, UI->getParent(), LI, Defs,
856 Uses, NewVNs, LiveOut, Phis, true, true);
859 // Add ranges for dead defs
860 for (MachineRegisterInfo::def_iterator DI = MRI->def_begin(LI->reg),
861 DE = MRI->def_end(); DI != DE; ++DI) {
862 unsigned DefIdx = LIs->getInstructionIndex(&*DI);
863 DefIdx = LiveIntervals::getDefIndex(DefIdx);
865 if (LI->liveAt(DefIdx)) continue;
867 VNInfo* DeadVN = NewVNs[&*DI];
868 LI->addRange(LiveRange(DefIdx, DefIdx+1, DeadVN));
869 LI->addKill(DeadVN, DefIdx);
873 /// ShrinkWrapLiveInterval - Recursively traverse the predecessor
874 /// chain to find the new 'kills' and shrink wrap the live interval to the
875 /// new kill indices.
877 PreAllocSplitting::ShrinkWrapLiveInterval(VNInfo *ValNo, MachineBasicBlock *MBB,
878 MachineBasicBlock *SuccMBB, MachineBasicBlock *DefMBB,
879 SmallPtrSet<MachineBasicBlock*, 8> &Visited,
880 DenseMap<MachineBasicBlock*, SmallVector<MachineOperand*, 4> > &Uses,
881 DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 4> > &UseMIs,
882 SmallVector<MachineBasicBlock*, 4> &UseMBBs) {
883 if (Visited.count(MBB))
886 // If live interval is live in another successor path, then we can't process
887 // this block. But we may able to do so after all the successors have been
889 if (MBB != BarrierMBB) {
890 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
891 SE = MBB->succ_end(); SI != SE; ++SI) {
892 MachineBasicBlock *SMBB = *SI;
895 if (CurrLI->liveAt(LIs->getMBBStartIdx(SMBB)))
902 DenseMap<MachineBasicBlock*, SmallVector<MachineOperand*, 4> >::iterator
903 UMII = Uses.find(MBB);
904 if (UMII != Uses.end()) {
905 // At least one use in this mbb, lets look for the kill.
906 DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 4> >::iterator
907 UMII2 = UseMIs.find(MBB);
908 if (ShrinkWrapToLastUse(MBB, ValNo, UMII->second, UMII2->second))
909 // Found a kill, shrink wrapping of this path ends here.
911 } else if (MBB == DefMBB) {
912 // There are no uses after the def.
913 MachineInstr *DefMI = LIs->getInstructionFromIndex(ValNo->def);
914 if (UseMBBs.empty()) {
915 // The only use must be below barrier in the barrier block. It's safe to
917 LIs->RemoveMachineInstrFromMaps(DefMI);
918 DefMI->eraseFromParent();
919 CurrLI->removeRange(ValNo->def, LIs->getMBBEndIdx(MBB)+1);
921 } else if (MBB == BarrierMBB) {
922 // Remove entire live range from start of mbb to barrier.
923 CurrLI->removeRange(LIs->getMBBStartIdx(MBB),
924 LIs->getUseIndex(BarrierIdx)+1);
926 // Remove entire live range of the mbb out of the live interval.
927 CurrLI->removeRange(LIs->getMBBStartIdx(MBB), LIs->getMBBEndIdx(MBB)+1);
931 // Reached the def mbb, stop traversing this path further.
934 // Traverse the pathes up the predecessor chains further.
935 for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
936 PE = MBB->pred_end(); PI != PE; ++PI) {
937 MachineBasicBlock *Pred = *PI;
940 if (Pred == DefMBB && ValNo->hasPHIKill)
941 // Pred is the def bb and the def reaches other val#s, we must
942 // allow the value to be live out of the bb.
944 if (!CurrLI->liveAt(LIs->getMBBEndIdx(Pred)-1))
946 ShrinkWrapLiveInterval(ValNo, Pred, MBB, DefMBB, Visited,
947 Uses, UseMIs, UseMBBs);
954 void PreAllocSplitting::RepairLiveInterval(LiveInterval* CurrLI,
957 unsigned RestoreIdx) {
958 // Shrink wrap the live interval by walking up the CFG and find the
960 // Now let's find all the uses of the val#.
961 DenseMap<MachineBasicBlock*, SmallVector<MachineOperand*, 4> > Uses;
962 DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 4> > UseMIs;
963 SmallPtrSet<MachineBasicBlock*, 4> Seen;
964 SmallVector<MachineBasicBlock*, 4> UseMBBs;
965 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(CurrLI->reg),
966 UE = MRI->use_end(); UI != UE; ++UI) {
967 MachineOperand &UseMO = UI.getOperand();
968 MachineInstr *UseMI = UseMO.getParent();
969 unsigned UseIdx = LIs->getInstructionIndex(UseMI);
970 LiveInterval::iterator ULR = CurrLI->FindLiveRangeContaining(UseIdx);
971 if (ULR->valno != ValNo)
973 MachineBasicBlock *UseMBB = UseMI->getParent();
974 // Remember which other mbb's use this val#.
975 if (Seen.insert(UseMBB) && UseMBB != BarrierMBB)
976 UseMBBs.push_back(UseMBB);
977 DenseMap<MachineBasicBlock*, SmallVector<MachineOperand*, 4> >::iterator
978 UMII = Uses.find(UseMBB);
979 if (UMII != Uses.end()) {
980 DenseMap<MachineBasicBlock*, SmallPtrSet<MachineInstr*, 4> >::iterator
981 UMII2 = UseMIs.find(UseMBB);
982 UMII->second.push_back(&UseMO);
983 UMII2->second.insert(UseMI);
985 SmallVector<MachineOperand*, 4> Ops;
986 Ops.push_back(&UseMO);
987 Uses.insert(std::make_pair(UseMBB, Ops));
988 SmallPtrSet<MachineInstr*, 4> MIs;
990 UseMIs.insert(std::make_pair(UseMBB, MIs));
994 // Walk up the predecessor chains.
995 SmallPtrSet<MachineBasicBlock*, 8> Visited;
996 ShrinkWrapLiveInterval(ValNo, BarrierMBB, NULL, DefMI->getParent(), Visited,
997 Uses, UseMIs, UseMBBs);
999 // Remove live range from barrier to the restore. FIXME: Find a better
1000 // point to re-start the live interval.
1001 VNInfo* AfterValNo = UpdateRegisterInterval(ValNo,
1002 LIs->getUseIndex(BarrierIdx)+1,
1003 LIs->getDefIndex(RestoreIdx));
1005 // Attempt to renumber the new valno into a new vreg.
1006 RenumberValno(AfterValNo);
1009 /// RenumberValno - Split the given valno out into a new vreg, allowing it to
1010 /// be allocated to a different register. This function creates a new vreg,
1011 /// copies the valno and its live ranges over to the new vreg's interval,
1012 /// removes them from the old interval, and rewrites all uses and defs of
1013 /// the original reg to the new vreg within those ranges.
1014 void PreAllocSplitting::RenumberValno(VNInfo* VN) {
1015 SmallVector<VNInfo*, 4> Stack;
1016 SmallVector<VNInfo*, 4> VNsToCopy;
1017 Stack.push_back(VN);
1019 // Walk through and copy the valno we care about, and any other valnos
1020 // that are two-address redefinitions of the one we care about. These
1021 // will need to be rewritten as well. We also check for safety of the
1022 // renumbering here, by making sure that none of the valno involved has
1024 while (!Stack.empty()) {
1025 VNInfo* OldVN = Stack.back();
1028 // Bail out if we ever encounter a valno that has a PHI kill. We can't
1030 if (OldVN->hasPHIKill) return;
1032 VNsToCopy.push_back(OldVN);
1034 // Locate two-address redefinitions
1035 for (SmallVector<unsigned, 4>::iterator KI = OldVN->kills.begin(),
1036 KE = OldVN->kills.end(); KI != KE; ++KI) {
1037 MachineInstr* MI = LIs->getInstructionFromIndex(*KI);
1038 //if (!MI) continue;
1039 unsigned DefIdx = MI->findRegisterDefOperandIdx(CurrLI->reg);
1040 if (DefIdx == ~0U) continue;
1041 if (MI->isRegReDefinedByTwoAddr(DefIdx)) {
1043 CurrLI->findDefinedVNInfo(LiveIntervals::getDefIndex(*KI));
1044 Stack.push_back(NextVN);
1049 // Create the new vreg
1050 unsigned NewVReg = MRI->createVirtualRegister(MRI->getRegClass(CurrLI->reg));
1052 // Create the new live interval
1053 LiveInterval& NewLI = LIs->getOrCreateInterval(NewVReg);
1055 for (SmallVector<VNInfo*, 4>::iterator OI = VNsToCopy.begin(), OE =
1056 VNsToCopy.end(); OI != OE; ++OI) {
1057 VNInfo* OldVN = *OI;
1059 // Copy the valno over
1060 VNInfo* NewVN = NewLI.getNextValue(OldVN->def, OldVN->copy,
1061 LIs->getVNInfoAllocator());
1062 NewLI.copyValNumInfo(NewVN, OldVN);
1063 NewLI.MergeValueInAsValue(*CurrLI, OldVN, NewVN);
1065 // Remove the valno from the old interval
1066 CurrLI->removeValNo(OldVN);
1069 // Rewrite defs and uses. This is done in two stages to avoid invalidating
1070 // the reg_iterator.
1071 SmallVector<std::pair<MachineInstr*, unsigned>, 8> OpsToChange;
1073 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(CurrLI->reg),
1074 E = MRI->reg_end(); I != E; ++I) {
1075 MachineOperand& MO = I.getOperand();
1076 unsigned InstrIdx = LIs->getInstructionIndex(&*I);
1078 if ((MO.isUse() && NewLI.liveAt(LiveIntervals::getUseIndex(InstrIdx))) ||
1079 (MO.isDef() && NewLI.liveAt(LiveIntervals::getDefIndex(InstrIdx))))
1080 OpsToChange.push_back(std::make_pair(&*I, I.getOperandNo()));
1083 for (SmallVector<std::pair<MachineInstr*, unsigned>, 8>::iterator I =
1084 OpsToChange.begin(), E = OpsToChange.end(); I != E; ++I) {
1085 MachineInstr* Inst = I->first;
1086 unsigned OpIdx = I->second;
1087 MachineOperand& MO = Inst->getOperand(OpIdx);
1094 bool PreAllocSplitting::Rematerialize(unsigned vreg, VNInfo* ValNo,
1095 MachineInstr* DefMI,
1096 MachineBasicBlock::iterator RestorePt,
1097 unsigned RestoreIdx,
1098 SmallPtrSet<MachineInstr*, 4>& RefsInMBB) {
1099 MachineBasicBlock& MBB = *RestorePt->getParent();
1101 MachineBasicBlock::iterator KillPt = BarrierMBB->end();
1102 unsigned KillIdx = 0;
1103 if (ValNo->def == ~0U || DefMI->getParent() == BarrierMBB)
1104 KillPt = findSpillPoint(BarrierMBB, Barrier, NULL, RefsInMBB, KillIdx);
1106 KillPt = findNextEmptySlot(DefMI->getParent(), DefMI, KillIdx);
1108 if (KillPt == DefMI->getParent()->end())
1111 TII->reMaterialize(MBB, RestorePt, vreg, DefMI);
1112 LIs->InsertMachineInstrInMaps(prior(RestorePt), RestoreIdx);
1114 if (KillPt->getParent() == BarrierMBB) {
1115 UpdateRegisterInterval(ValNo, LIs->getUseIndex(KillIdx)+1,
1116 LIs->getDefIndex(RestoreIdx));
1123 RepairLiveInterval(CurrLI, ValNo, DefMI, RestoreIdx);
1130 MachineInstr* PreAllocSplitting::FoldSpill(unsigned vreg,
1131 const TargetRegisterClass* RC,
1132 MachineInstr* DefMI,
1133 MachineInstr* Barrier,
1134 MachineBasicBlock* MBB,
1136 SmallPtrSet<MachineInstr*, 4>& RefsInMBB) {
1137 MachineBasicBlock::iterator Pt = MBB->begin();
1139 // Go top down if RefsInMBB is empty.
1140 if (RefsInMBB.empty())
1143 MachineBasicBlock::iterator FoldPt = Barrier;
1144 while (&*FoldPt != DefMI && FoldPt != MBB->begin() &&
1145 !RefsInMBB.count(FoldPt))
1148 int OpIdx = FoldPt->findRegisterDefOperandIdx(vreg, false);
1152 SmallVector<unsigned, 1> Ops;
1153 Ops.push_back(OpIdx);
1155 if (!TII->canFoldMemoryOperand(FoldPt, Ops))
1158 DenseMap<unsigned, int>::iterator I = IntervalSSMap.find(vreg);
1159 if (I != IntervalSSMap.end()) {
1162 SS = MFI->CreateStackObject(RC->getSize(), RC->getAlignment());
1166 MachineInstr* FMI = TII->foldMemoryOperand(*MBB->getParent(),
1170 LIs->ReplaceMachineInstrInMaps(FoldPt, FMI);
1171 FMI = MBB->insert(MBB->erase(FoldPt), FMI);
1174 IntervalSSMap[vreg] = SS;
1175 CurrSLI = &LSs->getOrCreateInterval(SS);
1176 if (CurrSLI->hasAtLeastOneValue())
1177 CurrSValNo = CurrSLI->getValNumInfo(0);
1179 CurrSValNo = CurrSLI->getNextValue(~0U, 0, LSs->getVNInfoAllocator());
1185 /// SplitRegLiveInterval - Split (spill and restore) the given live interval
1186 /// so it would not cross the barrier that's being processed. Shrink wrap
1187 /// (minimize) the live interval to the last uses.
1188 bool PreAllocSplitting::SplitRegLiveInterval(LiveInterval *LI) {
1191 // Find live range where current interval cross the barrier.
1192 LiveInterval::iterator LR =
1193 CurrLI->FindLiveRangeContaining(LIs->getUseIndex(BarrierIdx));
1194 VNInfo *ValNo = LR->valno;
1196 if (ValNo->def == ~1U) {
1197 // Defined by a dead def? How can this be?
1198 assert(0 && "Val# is defined by a dead def?");
1202 MachineInstr *DefMI = (ValNo->def != ~0U)
1203 ? LIs->getInstructionFromIndex(ValNo->def) : NULL;
1205 // If this would create a new join point, do not split.
1206 if (DefMI && createsNewJoin(LR, DefMI->getParent(), Barrier->getParent()))
1209 // Find all references in the barrier mbb.
1210 SmallPtrSet<MachineInstr*, 4> RefsInMBB;
1211 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(CurrLI->reg),
1212 E = MRI->reg_end(); I != E; ++I) {
1213 MachineInstr *RefMI = &*I;
1214 if (RefMI->getParent() == BarrierMBB)
1215 RefsInMBB.insert(RefMI);
1218 // Find a point to restore the value after the barrier.
1219 unsigned RestoreIndex;
1220 MachineBasicBlock::iterator RestorePt =
1221 findRestorePoint(BarrierMBB, Barrier, LR->end, RefsInMBB, RestoreIndex);
1222 if (RestorePt == BarrierMBB->end())
1225 if (DefMI && LIs->isReMaterializable(*LI, ValNo, DefMI))
1226 if (Rematerialize(LI->reg, ValNo, DefMI, RestorePt,
1227 RestoreIndex, RefsInMBB))
1230 // Add a spill either before the barrier or after the definition.
1231 MachineBasicBlock *DefMBB = DefMI ? DefMI->getParent() : NULL;
1232 const TargetRegisterClass *RC = MRI->getRegClass(CurrLI->reg);
1233 unsigned SpillIndex = 0;
1234 MachineInstr *SpillMI = NULL;
1236 if (ValNo->def == ~0U) {
1237 // If it's defined by a phi, we must split just before the barrier.
1238 if ((SpillMI = FoldSpill(LI->reg, RC, 0, Barrier,
1239 BarrierMBB, SS, RefsInMBB))) {
1240 SpillIndex = LIs->getInstructionIndex(SpillMI);
1242 MachineBasicBlock::iterator SpillPt =
1243 findSpillPoint(BarrierMBB, Barrier, NULL, RefsInMBB, SpillIndex);
1244 if (SpillPt == BarrierMBB->begin())
1245 return false; // No gap to insert spill.
1248 SS = CreateSpillStackSlot(CurrLI->reg, RC);
1249 TII->storeRegToStackSlot(*BarrierMBB, SpillPt, CurrLI->reg, true, SS, RC);
1250 SpillMI = prior(SpillPt);
1251 LIs->InsertMachineInstrInMaps(SpillMI, SpillIndex);
1253 } else if (!IsAvailableInStack(DefMBB, CurrLI->reg, ValNo->def,
1254 RestoreIndex, SpillIndex, SS)) {
1255 // If it's already split, just restore the value. There is no need to spill
1258 return false; // Def is dead. Do nothing.
1260 if ((SpillMI = FoldSpill(LI->reg, RC, DefMI, Barrier,
1261 BarrierMBB, SS, RefsInMBB))) {
1262 SpillIndex = LIs->getInstructionIndex(SpillMI);
1264 // Check if it's possible to insert a spill after the def MI.
1265 MachineBasicBlock::iterator SpillPt;
1266 if (DefMBB == BarrierMBB) {
1267 // Add spill after the def and the last use before the barrier.
1268 SpillPt = findSpillPoint(BarrierMBB, Barrier, DefMI,
1269 RefsInMBB, SpillIndex);
1270 if (SpillPt == DefMBB->begin())
1271 return false; // No gap to insert spill.
1273 SpillPt = findNextEmptySlot(DefMBB, DefMI, SpillIndex);
1274 if (SpillPt == DefMBB->end())
1275 return false; // No gap to insert spill.
1277 // Add spill. The store instruction kills the register if def is before
1278 // the barrier in the barrier block.
1279 SS = CreateSpillStackSlot(CurrLI->reg, RC);
1280 TII->storeRegToStackSlot(*DefMBB, SpillPt, CurrLI->reg,
1281 DefMBB == BarrierMBB, SS, RC);
1282 SpillMI = prior(SpillPt);
1283 LIs->InsertMachineInstrInMaps(SpillMI, SpillIndex);
1287 // Remember def instruction index to spill index mapping.
1288 if (DefMI && SpillMI)
1289 Def2SpillMap[ValNo->def] = SpillIndex;
1292 TII->loadRegFromStackSlot(*BarrierMBB, RestorePt, CurrLI->reg, SS, RC);
1293 MachineInstr *LoadMI = prior(RestorePt);
1294 LIs->InsertMachineInstrInMaps(LoadMI, RestoreIndex);
1296 // If live interval is spilled in the same block as the barrier, just
1297 // create a hole in the interval.
1299 (SpillMI && SpillMI->getParent() == BarrierMBB)) {
1300 // Update spill stack slot live interval.
1301 UpdateSpillSlotInterval(ValNo, LIs->getUseIndex(SpillIndex)+1,
1302 LIs->getDefIndex(RestoreIndex));
1304 UpdateRegisterInterval(ValNo, LIs->getUseIndex(SpillIndex)+1,
1305 LIs->getDefIndex(RestoreIndex));
1311 // Update spill stack slot live interval.
1312 UpdateSpillSlotInterval(ValNo, LIs->getUseIndex(SpillIndex)+1,
1313 LIs->getDefIndex(RestoreIndex));
1315 RepairLiveInterval(CurrLI, ValNo, DefMI, RestoreIndex);
1321 /// SplitRegLiveIntervals - Split all register live intervals that cross the
1322 /// barrier that's being processed.
1324 PreAllocSplitting::SplitRegLiveIntervals(const TargetRegisterClass **RCs) {
1325 // First find all the virtual registers whose live intervals are intercepted
1326 // by the current barrier.
1327 SmallVector<LiveInterval*, 8> Intervals;
1328 for (const TargetRegisterClass **RC = RCs; *RC; ++RC) {
1329 if (TII->IgnoreRegisterClassBarriers(*RC))
1331 std::vector<unsigned> &VRs = MRI->getRegClassVirtRegs(*RC);
1332 for (unsigned i = 0, e = VRs.size(); i != e; ++i) {
1333 unsigned Reg = VRs[i];
1334 if (!LIs->hasInterval(Reg))
1336 LiveInterval *LI = &LIs->getInterval(Reg);
1337 if (LI->liveAt(BarrierIdx) && !Barrier->readsRegister(Reg))
1338 // Virtual register live interval is intercepted by the barrier. We
1339 // should split and shrink wrap its interval if possible.
1340 Intervals.push_back(LI);
1344 // Process the affected live intervals.
1345 bool Change = false;
1346 while (!Intervals.empty()) {
1347 if (PreSplitLimit != -1 && (int)NumSplits == PreSplitLimit)
1349 LiveInterval *LI = Intervals.back();
1350 Intervals.pop_back();
1351 Change |= SplitRegLiveInterval(LI);
1357 bool PreAllocSplitting::createsNewJoin(LiveRange* LR,
1358 MachineBasicBlock* DefMBB,
1359 MachineBasicBlock* BarrierMBB) {
1360 if (DefMBB == BarrierMBB)
1363 if (LR->valno->hasPHIKill)
1366 unsigned MBBEnd = LIs->getMBBEndIdx(BarrierMBB);
1367 if (LR->end < MBBEnd)
1370 MachineLoopInfo& MLI = getAnalysis<MachineLoopInfo>();
1371 if (MLI.getLoopFor(DefMBB) != MLI.getLoopFor(BarrierMBB))
1374 MachineDominatorTree& MDT = getAnalysis<MachineDominatorTree>();
1375 SmallPtrSet<MachineBasicBlock*, 4> Visited;
1376 typedef std::pair<MachineBasicBlock*,
1377 MachineBasicBlock::succ_iterator> ItPair;
1378 SmallVector<ItPair, 4> Stack;
1379 Stack.push_back(std::make_pair(BarrierMBB, BarrierMBB->succ_begin()));
1381 while (!Stack.empty()) {
1382 ItPair P = Stack.back();
1385 MachineBasicBlock* PredMBB = P.first;
1386 MachineBasicBlock::succ_iterator S = P.second;
1388 if (S == PredMBB->succ_end())
1390 else if (Visited.count(*S)) {
1391 Stack.push_back(std::make_pair(PredMBB, ++S));
1394 Stack.push_back(std::make_pair(PredMBB, S+1));
1396 MachineBasicBlock* MBB = *S;
1397 Visited.insert(MBB);
1399 if (MBB == BarrierMBB)
1402 MachineDomTreeNode* DefMDTN = MDT.getNode(DefMBB);
1403 MachineDomTreeNode* BarrierMDTN = MDT.getNode(BarrierMBB);
1404 MachineDomTreeNode* MDTN = MDT.getNode(MBB)->getIDom();
1406 if (MDTN == DefMDTN)
1408 else if (MDTN == BarrierMDTN)
1410 MDTN = MDTN->getIDom();
1413 MBBEnd = LIs->getMBBEndIdx(MBB);
1414 if (LR->end > MBBEnd)
1415 Stack.push_back(std::make_pair(MBB, MBB->succ_begin()));
1422 bool PreAllocSplitting::runOnMachineFunction(MachineFunction &MF) {
1424 TM = &MF.getTarget();
1425 TII = TM->getInstrInfo();
1426 MFI = MF.getFrameInfo();
1427 MRI = &MF.getRegInfo();
1428 LIs = &getAnalysis<LiveIntervals>();
1429 LSs = &getAnalysis<LiveStacks>();
1431 bool MadeChange = false;
1433 // Make sure blocks are numbered in order.
1434 MF.RenumberBlocks();
1436 MachineBasicBlock *Entry = MF.begin();
1437 SmallPtrSet<MachineBasicBlock*,16> Visited;
1439 for (df_ext_iterator<MachineBasicBlock*, SmallPtrSet<MachineBasicBlock*,16> >
1440 DFI = df_ext_begin(Entry, Visited), E = df_ext_end(Entry, Visited);
1443 for (MachineBasicBlock::iterator I = BarrierMBB->begin(),
1444 E = BarrierMBB->end(); I != E; ++I) {
1446 const TargetRegisterClass **BarrierRCs =
1447 Barrier->getDesc().getRegClassBarriers();
1450 BarrierIdx = LIs->getInstructionIndex(Barrier);
1451 MadeChange |= SplitRegLiveIntervals(BarrierRCs);