1 //===----- SchedulePostRAList.cpp - list scheduler ------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements a top-down list scheduler, using standard algorithms.
11 // The basic approach uses a priority queue of available nodes to schedule.
12 // One at a time, nodes are taken from the priority queue (thus in priority
13 // order), checked for legality to schedule, and emitted if legal.
15 // Nodes may not be legal to schedule either due to structural hazards (e.g.
16 // pipeline or resource constraints) or because an input to the instruction has
17 // not completed execution.
19 //===----------------------------------------------------------------------===//
21 #define DEBUG_TYPE "post-RA-sched"
22 #include "ExactHazardRecognizer.h"
23 #include "SimpleHazardRecognizer.h"
24 #include "ScheduleDAGInstrs.h"
25 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/CodeGen/LatencyPriorityQueue.h"
27 #include "llvm/CodeGen/SchedulerRegistry.h"
28 #include "llvm/CodeGen/MachineDominators.h"
29 #include "llvm/CodeGen/MachineFunctionPass.h"
30 #include "llvm/CodeGen/MachineLoopInfo.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
33 #include "llvm/Target/TargetLowering.h"
34 #include "llvm/Target/TargetMachine.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetRegisterInfo.h"
37 #include "llvm/Support/Compiler.h"
38 #include "llvm/Support/Debug.h"
39 #include "llvm/Support/ErrorHandling.h"
40 #include "llvm/Support/raw_ostream.h"
41 #include "llvm/ADT/Statistic.h"
46 STATISTIC(NumNoops, "Number of noops inserted");
47 STATISTIC(NumStalls, "Number of pipeline stalls");
50 EnableAntiDepBreaking("break-anti-dependencies",
51 cl::desc("Break post-RA scheduling anti-dependencies"),
52 cl::init(true), cl::Hidden);
55 EnablePostRAHazardAvoidance("avoid-hazards",
56 cl::desc("Enable exact hazard avoidance"),
57 cl::init(false), cl::Hidden);
59 // If DebugDiv > 0 then only schedule MBB with (ID % DebugDiv) == DebugMod
61 DebugDiv("postra-sched-debugdiv",
62 cl::desc("Debug control MBBs that are scheduled"),
63 cl::init(0), cl::Hidden);
65 DebugMod("postra-sched-debugmod",
66 cl::desc("Debug control MBBs that are scheduled"),
67 cl::init(0), cl::Hidden);
70 class VISIBILITY_HIDDEN PostRAScheduler : public MachineFunctionPass {
73 PostRAScheduler() : MachineFunctionPass(&ID) {}
75 void getAnalysisUsage(AnalysisUsage &AU) const {
77 AU.addRequired<MachineDominatorTree>();
78 AU.addPreserved<MachineDominatorTree>();
79 AU.addRequired<MachineLoopInfo>();
80 AU.addPreserved<MachineLoopInfo>();
81 MachineFunctionPass::getAnalysisUsage(AU);
84 const char *getPassName() const {
85 return "Post RA top-down list latency scheduler";
88 bool runOnMachineFunction(MachineFunction &Fn);
90 char PostRAScheduler::ID = 0;
92 class VISIBILITY_HIDDEN SchedulePostRATDList : public ScheduleDAGInstrs {
93 /// AvailableQueue - The priority queue to use for the available SUnits.
95 LatencyPriorityQueue AvailableQueue;
97 /// PendingQueue - This contains all of the instructions whose operands have
98 /// been issued, but their results are not ready yet (due to the latency of
99 /// the operation). Once the operands becomes available, the instruction is
100 /// added to the AvailableQueue.
101 std::vector<SUnit*> PendingQueue;
103 /// Topo - A topological ordering for SUnits.
104 ScheduleDAGTopologicalSort Topo;
106 /// AllocatableSet - The set of allocatable registers.
107 /// We'll be ignoring anti-dependencies on non-allocatable registers,
108 /// because they may not be safe to break.
109 const BitVector AllocatableSet;
111 /// HazardRec - The hazard recognizer to use.
112 ScheduleHazardRecognizer *HazardRec;
114 /// Classes - For live regs that are only used in one register class in a
115 /// live range, the register class. If the register is not live, the
116 /// corresponding value is null. If the register is live but used in
117 /// multiple register classes, the corresponding value is -1 casted to a
119 const TargetRegisterClass *
120 Classes[TargetRegisterInfo::FirstVirtualRegister];
122 /// RegRegs - Map registers to all their references within a live range.
123 std::multimap<unsigned, MachineOperand *> RegRefs;
125 /// The index of the most recent kill (proceding bottom-up), or ~0u if
126 /// the register is not live.
127 unsigned KillIndices[TargetRegisterInfo::FirstVirtualRegister];
129 /// The index of the most recent complete def (proceding bottom up), or ~0u
130 /// if the register is live.
131 unsigned DefIndices[TargetRegisterInfo::FirstVirtualRegister];
134 SchedulePostRATDList(MachineFunction &MF,
135 const MachineLoopInfo &MLI,
136 const MachineDominatorTree &MDT,
137 ScheduleHazardRecognizer *HR)
138 : ScheduleDAGInstrs(MF, MLI, MDT), Topo(SUnits),
139 AllocatableSet(TRI->getAllocatableSet(MF)),
142 ~SchedulePostRATDList() {
146 /// StartBlock - Initialize register live-range state for scheduling in
149 void StartBlock(MachineBasicBlock *BB);
151 /// Schedule - Schedule the instruction range using list scheduling.
155 /// FixupKills - Fix register kill flags that have been made
156 /// invalid due to scheduling
158 void FixupKills(MachineBasicBlock *MBB);
160 /// Observe - Update liveness information to account for the current
161 /// instruction, which will not be scheduled.
163 void Observe(MachineInstr *MI, unsigned Count);
165 /// FinishBlock - Clean up register live-range state.
169 /// GenerateLivenessForKills - If true then generate Def/Kill
170 /// information for use in updating register kill. If false then
171 /// generate Def/Kill information for anti-dependence breaking.
172 bool GenerateLivenessForKills;
175 void PrescanInstruction(MachineInstr *MI);
176 void ScanInstruction(MachineInstr *MI, unsigned Count);
177 void ReleaseSucc(SUnit *SU, SDep *SuccEdge);
178 void ReleaseSuccessors(SUnit *SU);
179 void ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle);
180 void ListScheduleTopDown();
181 bool BreakAntiDependencies();
182 unsigned findSuitableFreeRegister(unsigned AntiDepReg,
184 const TargetRegisterClass *);
188 /// isSchedulingBoundary - Test if the given instruction should be
189 /// considered a scheduling boundary. This primarily includes labels
192 static bool isSchedulingBoundary(const MachineInstr *MI,
193 const MachineFunction &MF) {
194 // Terminators and labels can't be scheduled around.
195 if (MI->getDesc().isTerminator() || MI->isLabel())
198 // Don't attempt to schedule around any instruction that modifies
199 // a stack-oriented pointer, as it's unlikely to be profitable. This
200 // saves compile time, because it doesn't require every single
201 // stack slot reference to depend on the instruction that does the
203 const TargetLowering &TLI = *MF.getTarget().getTargetLowering();
204 if (MI->modifiesRegister(TLI.getStackPointerRegisterToSaveRestore()))
210 bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) {
211 DEBUG(errs() << "PostRAScheduler\n");
213 const MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>();
214 const MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>();
215 const InstrItineraryData &InstrItins = Fn.getTarget().getInstrItineraryData();
216 ScheduleHazardRecognizer *HR = EnablePostRAHazardAvoidance ?
217 (ScheduleHazardRecognizer *)new ExactHazardRecognizer(InstrItins) :
218 (ScheduleHazardRecognizer *)new SimpleHazardRecognizer();
220 SchedulePostRATDList Scheduler(Fn, MLI, MDT, HR);
222 // Loop over all of the basic blocks
223 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
224 MBB != MBBe; ++MBB) {
226 // If DebugDiv > 0 then only schedule MBB with (ID % DebugDiv) == DebugMod
228 static int bbcnt = 0;
229 if (bbcnt++ % DebugDiv != DebugMod)
231 errs() << "*** DEBUG scheduling " << Fn.getFunction()->getNameStr() <<
232 ":MBB ID#" << MBB->getNumber() << " ***\n";
236 // Initialize register live-range state for scheduling in this block.
237 Scheduler.GenerateLivenessForKills = false;
238 Scheduler.StartBlock(MBB);
240 // Schedule each sequence of instructions not interrupted by a label
241 // or anything else that effectively needs to shut down scheduling.
242 MachineBasicBlock::iterator Current = MBB->end();
243 unsigned Count = MBB->size(), CurrentCount = Count;
244 for (MachineBasicBlock::iterator I = Current; I != MBB->begin(); ) {
245 MachineInstr *MI = prior(I);
246 if (isSchedulingBoundary(MI, Fn)) {
247 Scheduler.Run(MBB, I, Current, CurrentCount);
248 Scheduler.EmitSchedule();
250 CurrentCount = Count - 1;
251 Scheduler.Observe(MI, CurrentCount);
256 assert(Count == 0 && "Instruction count mismatch!");
257 assert((MBB->begin() == Current || CurrentCount != 0) &&
258 "Instruction count mismatch!");
259 Scheduler.Run(MBB, MBB->begin(), Current, CurrentCount);
260 Scheduler.EmitSchedule();
262 // Clean up register live-range state.
263 Scheduler.FinishBlock();
265 // Initialize register live-range state again and update register kills
266 Scheduler.GenerateLivenessForKills = true;
267 Scheduler.StartBlock(MBB);
268 Scheduler.FixupKills(MBB);
269 Scheduler.FinishBlock();
275 /// StartBlock - Initialize register live-range state for scheduling in
278 void SchedulePostRATDList::StartBlock(MachineBasicBlock *BB) {
279 // Call the superclass.
280 ScheduleDAGInstrs::StartBlock(BB);
282 // Reset the hazard recognizer.
285 // Clear out the register class data.
286 std::fill(Classes, array_endof(Classes),
287 static_cast<const TargetRegisterClass *>(0));
289 // Initialize the indices to indicate that no registers are live.
290 std::fill(KillIndices, array_endof(KillIndices), ~0u);
291 std::fill(DefIndices, array_endof(DefIndices), BB->size());
293 // Determine the live-out physregs for this block.
294 if (!BB->empty() && BB->back().getDesc().isReturn())
295 // In a return block, examine the function live-out regs.
296 for (MachineRegisterInfo::liveout_iterator I = MRI.liveout_begin(),
297 E = MRI.liveout_end(); I != E; ++I) {
299 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
300 KillIndices[Reg] = BB->size();
301 DefIndices[Reg] = ~0u;
302 // Repeat, for all aliases.
303 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
304 unsigned AliasReg = *Alias;
305 Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1);
306 KillIndices[AliasReg] = BB->size();
307 DefIndices[AliasReg] = ~0u;
311 // In a non-return block, examine the live-in regs of all successors.
312 for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
313 SE = BB->succ_end(); SI != SE; ++SI)
314 for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
315 E = (*SI)->livein_end(); I != E; ++I) {
317 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
318 KillIndices[Reg] = BB->size();
319 DefIndices[Reg] = ~0u;
320 // Repeat, for all aliases.
321 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
322 unsigned AliasReg = *Alias;
323 Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1);
324 KillIndices[AliasReg] = BB->size();
325 DefIndices[AliasReg] = ~0u;
329 if (!GenerateLivenessForKills) {
330 // Consider callee-saved registers as live-out, since we're running after
331 // prologue/epilogue insertion so there's no way to add additional
334 // TODO: there is a new method
335 // MachineFrameInfo::getPristineRegs(MBB). It gives you a list of
336 // CSRs that have not been saved when entering the MBB. The
337 // remaining CSRs have been saved and can be treated like call
338 // clobbered registers.
339 for (const unsigned *I = TRI->getCalleeSavedRegs(); *I; ++I) {
341 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
342 KillIndices[Reg] = BB->size();
343 DefIndices[Reg] = ~0u;
344 // Repeat, for all aliases.
345 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
346 unsigned AliasReg = *Alias;
347 Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1);
348 KillIndices[AliasReg] = BB->size();
349 DefIndices[AliasReg] = ~0u;
355 /// Schedule - Schedule the instruction range using list scheduling.
357 void SchedulePostRATDList::Schedule() {
358 DEBUG(errs() << "********** List Scheduling **********\n");
360 // Build the scheduling graph.
363 if (EnableAntiDepBreaking) {
364 if (BreakAntiDependencies()) {
365 // We made changes. Update the dependency graph.
366 // Theoretically we could update the graph in place:
367 // When a live range is changed to use a different register, remove
368 // the def's anti-dependence *and* output-dependence edges due to
369 // that register, and add new anti-dependence and output-dependence
370 // edges based on the next live range of the register.
378 DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
379 SUnits[su].dumpAll(this));
381 AvailableQueue.initNodes(SUnits);
383 ListScheduleTopDown();
385 AvailableQueue.releaseState();
388 /// Observe - Update liveness information to account for the current
389 /// instruction, which will not be scheduled.
391 void SchedulePostRATDList::Observe(MachineInstr *MI, unsigned Count) {
392 assert(Count < InsertPosIndex && "Instruction index out of expected range!");
394 // Any register which was defined within the previous scheduling region
395 // may have been rescheduled and its lifetime may overlap with registers
396 // in ways not reflected in our current liveness state. For each such
397 // register, adjust the liveness state to be conservatively correct.
398 for (unsigned Reg = 0; Reg != TargetRegisterInfo::FirstVirtualRegister; ++Reg)
399 if (DefIndices[Reg] < InsertPosIndex && DefIndices[Reg] >= Count) {
400 assert(KillIndices[Reg] == ~0u && "Clobbered register is live!");
401 // Mark this register to be non-renamable.
402 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
403 // Move the def index to the end of the previous region, to reflect
404 // that the def could theoretically have been scheduled at the end.
405 DefIndices[Reg] = InsertPosIndex;
408 PrescanInstruction(MI);
409 ScanInstruction(MI, Count);
412 /// FinishBlock - Clean up register live-range state.
414 void SchedulePostRATDList::FinishBlock() {
417 // Call the superclass.
418 ScheduleDAGInstrs::FinishBlock();
421 /// CriticalPathStep - Return the next SUnit after SU on the bottom-up
423 static SDep *CriticalPathStep(SUnit *SU) {
425 unsigned NextDepth = 0;
426 // Find the predecessor edge with the greatest depth.
427 for (SUnit::pred_iterator P = SU->Preds.begin(), PE = SU->Preds.end();
429 SUnit *PredSU = P->getSUnit();
430 unsigned PredLatency = P->getLatency();
431 unsigned PredTotalLatency = PredSU->getDepth() + PredLatency;
432 // In the case of a latency tie, prefer an anti-dependency edge over
433 // other types of edges.
434 if (NextDepth < PredTotalLatency ||
435 (NextDepth == PredTotalLatency && P->getKind() == SDep::Anti)) {
436 NextDepth = PredTotalLatency;
443 void SchedulePostRATDList::PrescanInstruction(MachineInstr *MI) {
444 // Scan the register operands for this instruction and update
445 // Classes and RegRefs.
446 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
447 MachineOperand &MO = MI->getOperand(i);
448 if (!MO.isReg()) continue;
449 unsigned Reg = MO.getReg();
450 if (Reg == 0) continue;
451 const TargetRegisterClass *NewRC = 0;
453 if (i < MI->getDesc().getNumOperands())
454 NewRC = MI->getDesc().OpInfo[i].getRegClass(TRI);
456 // For now, only allow the register to be changed if its register
457 // class is consistent across all uses.
458 if (!Classes[Reg] && NewRC)
459 Classes[Reg] = NewRC;
460 else if (!NewRC || Classes[Reg] != NewRC)
461 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
463 // Now check for aliases.
464 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
465 // If an alias of the reg is used during the live range, give up.
466 // Note that this allows us to skip checking if AntiDepReg
467 // overlaps with any of the aliases, among other things.
468 unsigned AliasReg = *Alias;
469 if (Classes[AliasReg]) {
470 Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1);
471 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
475 // If we're still willing to consider this register, note the reference.
476 if (Classes[Reg] != reinterpret_cast<TargetRegisterClass *>(-1))
477 RegRefs.insert(std::make_pair(Reg, &MO));
481 void SchedulePostRATDList::ScanInstruction(MachineInstr *MI,
484 // Proceding upwards, registers that are defed but not used in this
485 // instruction are now dead.
486 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
487 MachineOperand &MO = MI->getOperand(i);
488 if (!MO.isReg()) continue;
489 unsigned Reg = MO.getReg();
490 if (Reg == 0) continue;
491 if (!MO.isDef()) continue;
492 // Ignore two-addr defs.
493 if (MI->isRegTiedToUseOperand(i)) continue;
495 DefIndices[Reg] = Count;
496 KillIndices[Reg] = ~0u;
497 assert(((KillIndices[Reg] == ~0u) !=
498 (DefIndices[Reg] == ~0u)) &&
499 "Kill and Def maps aren't consistent for Reg!");
502 // Repeat, for all subregs.
503 for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
505 unsigned SubregReg = *Subreg;
506 DefIndices[SubregReg] = Count;
507 KillIndices[SubregReg] = ~0u;
508 Classes[SubregReg] = 0;
509 RegRefs.erase(SubregReg);
511 // Conservatively mark super-registers as unusable.
512 for (const unsigned *Super = TRI->getSuperRegisters(Reg);
514 unsigned SuperReg = *Super;
515 Classes[SuperReg] = reinterpret_cast<TargetRegisterClass *>(-1);
518 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
519 MachineOperand &MO = MI->getOperand(i);
520 if (!MO.isReg()) continue;
521 unsigned Reg = MO.getReg();
522 if (Reg == 0) continue;
523 if (!MO.isUse()) continue;
525 const TargetRegisterClass *NewRC = 0;
526 if (i < MI->getDesc().getNumOperands())
527 NewRC = MI->getDesc().OpInfo[i].getRegClass(TRI);
529 // For now, only allow the register to be changed if its register
530 // class is consistent across all uses.
531 if (!Classes[Reg] && NewRC)
532 Classes[Reg] = NewRC;
533 else if (!NewRC || Classes[Reg] != NewRC)
534 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
536 RegRefs.insert(std::make_pair(Reg, &MO));
538 // It wasn't previously live but now it is, this is a kill.
539 if (KillIndices[Reg] == ~0u) {
540 KillIndices[Reg] = Count;
541 DefIndices[Reg] = ~0u;
542 assert(((KillIndices[Reg] == ~0u) !=
543 (DefIndices[Reg] == ~0u)) &&
544 "Kill and Def maps aren't consistent for Reg!");
546 // Repeat, for all aliases.
547 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
548 unsigned AliasReg = *Alias;
549 if (KillIndices[AliasReg] == ~0u) {
550 KillIndices[AliasReg] = Count;
551 DefIndices[AliasReg] = ~0u;
558 SchedulePostRATDList::findSuitableFreeRegister(unsigned AntiDepReg,
560 const TargetRegisterClass *RC) {
561 for (TargetRegisterClass::iterator R = RC->allocation_order_begin(MF),
562 RE = RC->allocation_order_end(MF); R != RE; ++R) {
563 unsigned NewReg = *R;
564 // Don't replace a register with itself.
565 if (NewReg == AntiDepReg) continue;
566 // Don't replace a register with one that was recently used to repair
567 // an anti-dependence with this AntiDepReg, because that would
568 // re-introduce that anti-dependence.
569 if (NewReg == LastNewReg) continue;
570 // If NewReg is dead and NewReg's most recent def is not before
571 // AntiDepReg's kill, it's safe to replace AntiDepReg with NewReg.
572 assert(((KillIndices[AntiDepReg] == ~0u) != (DefIndices[AntiDepReg] == ~0u)) &&
573 "Kill and Def maps aren't consistent for AntiDepReg!");
574 assert(((KillIndices[NewReg] == ~0u) != (DefIndices[NewReg] == ~0u)) &&
575 "Kill and Def maps aren't consistent for NewReg!");
576 if (KillIndices[NewReg] != ~0u ||
577 Classes[NewReg] == reinterpret_cast<TargetRegisterClass *>(-1) ||
578 KillIndices[AntiDepReg] > DefIndices[NewReg])
583 // No registers are free and available!
587 /// BreakAntiDependencies - Identifiy anti-dependencies along the critical path
588 /// of the ScheduleDAG and break them by renaming registers.
590 bool SchedulePostRATDList::BreakAntiDependencies() {
591 // The code below assumes that there is at least one instruction,
592 // so just duck out immediately if the block is empty.
593 if (SUnits.empty()) return false;
595 // Find the node at the bottom of the critical path.
597 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
598 SUnit *SU = &SUnits[i];
599 if (!Max || SU->getDepth() + SU->Latency > Max->getDepth() + Max->Latency)
603 DEBUG(errs() << "Critical path has total latency "
604 << (Max->getDepth() + Max->Latency) << "\n");
606 // Track progress along the critical path through the SUnit graph as we walk
608 SUnit *CriticalPathSU = Max;
609 MachineInstr *CriticalPathMI = CriticalPathSU->getInstr();
611 // Consider this pattern:
620 // There are three anti-dependencies here, and without special care,
621 // we'd break all of them using the same register:
630 // because at each anti-dependence, B is the first register that
631 // isn't A which is free. This re-introduces anti-dependencies
632 // at all but one of the original anti-dependencies that we were
633 // trying to break. To avoid this, keep track of the most recent
634 // register that each register was replaced with, avoid
635 // using it to repair an anti-dependence on the same register.
636 // This lets us produce this:
645 // This still has an anti-dependence on B, but at least it isn't on the
646 // original critical path.
648 // TODO: If we tracked more than one register here, we could potentially
649 // fix that remaining critical edge too. This is a little more involved,
650 // because unlike the most recent register, less recent registers should
651 // still be considered, though only if no other registers are available.
652 unsigned LastNewReg[TargetRegisterInfo::FirstVirtualRegister] = {};
654 // Attempt to break anti-dependence edges on the critical path. Walk the
655 // instructions from the bottom up, tracking information about liveness
656 // as we go to help determine which registers are available.
657 bool Changed = false;
658 unsigned Count = InsertPosIndex - 1;
659 for (MachineBasicBlock::iterator I = InsertPos, E = Begin;
661 MachineInstr *MI = --I;
663 // After regalloc, IMPLICIT_DEF instructions aren't safe to treat as
664 // dependence-breaking. In the case of an INSERT_SUBREG, the IMPLICIT_DEF
665 // is left behind appearing to clobber the super-register, while the
666 // subregister needs to remain live. So we just ignore them.
667 if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF)
670 // Check if this instruction has a dependence on the critical path that
671 // is an anti-dependence that we may be able to break. If it is, set
672 // AntiDepReg to the non-zero register associated with the anti-dependence.
674 // We limit our attention to the critical path as a heuristic to avoid
675 // breaking anti-dependence edges that aren't going to significantly
676 // impact the overall schedule. There are a limited number of registers
677 // and we want to save them for the important edges.
679 // TODO: Instructions with multiple defs could have multiple
680 // anti-dependencies. The current code here only knows how to break one
681 // edge per instruction. Note that we'd have to be able to break all of
682 // the anti-dependencies in an instruction in order to be effective.
683 unsigned AntiDepReg = 0;
684 if (MI == CriticalPathMI) {
685 if (SDep *Edge = CriticalPathStep(CriticalPathSU)) {
686 SUnit *NextSU = Edge->getSUnit();
688 // Only consider anti-dependence edges.
689 if (Edge->getKind() == SDep::Anti) {
690 AntiDepReg = Edge->getReg();
691 assert(AntiDepReg != 0 && "Anti-dependence on reg0?");
692 // Don't break anti-dependencies on non-allocatable registers.
693 if (!AllocatableSet.test(AntiDepReg))
696 // If the SUnit has other dependencies on the SUnit that it
697 // anti-depends on, don't bother breaking the anti-dependency
698 // since those edges would prevent such units from being
699 // scheduled past each other regardless.
701 // Also, if there are dependencies on other SUnits with the
702 // same register as the anti-dependency, don't attempt to
704 for (SUnit::pred_iterator P = CriticalPathSU->Preds.begin(),
705 PE = CriticalPathSU->Preds.end(); P != PE; ++P)
706 if (P->getSUnit() == NextSU ?
707 (P->getKind() != SDep::Anti || P->getReg() != AntiDepReg) :
708 (P->getKind() == SDep::Data && P->getReg() == AntiDepReg)) {
714 CriticalPathSU = NextSU;
715 CriticalPathMI = CriticalPathSU->getInstr();
717 // We've reached the end of the critical path.
723 PrescanInstruction(MI);
725 // If this instruction has a use of AntiDepReg, breaking it
727 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
728 MachineOperand &MO = MI->getOperand(i);
729 if (!MO.isReg()) continue;
730 unsigned Reg = MO.getReg();
731 if (Reg == 0) continue;
732 if (MO.isUse() && AntiDepReg == Reg) {
738 // Determine AntiDepReg's register class, if it is live and is
739 // consistently used within a single class.
740 const TargetRegisterClass *RC = AntiDepReg != 0 ? Classes[AntiDepReg] : 0;
741 assert((AntiDepReg == 0 || RC != NULL) &&
742 "Register should be live if it's causing an anti-dependence!");
743 if (RC == reinterpret_cast<TargetRegisterClass *>(-1))
746 // Look for a suitable register to use to break the anti-depenence.
748 // TODO: Instead of picking the first free register, consider which might
750 if (AntiDepReg != 0) {
751 if (unsigned NewReg = findSuitableFreeRegister(AntiDepReg,
752 LastNewReg[AntiDepReg],
754 DEBUG(errs() << "Breaking anti-dependence edge on "
755 << TRI->getName(AntiDepReg)
756 << " with " << RegRefs.count(AntiDepReg) << " references"
757 << " using " << TRI->getName(NewReg) << "!\n");
759 // Update the references to the old register to refer to the new
761 std::pair<std::multimap<unsigned, MachineOperand *>::iterator,
762 std::multimap<unsigned, MachineOperand *>::iterator>
763 Range = RegRefs.equal_range(AntiDepReg);
764 for (std::multimap<unsigned, MachineOperand *>::iterator
765 Q = Range.first, QE = Range.second; Q != QE; ++Q)
766 Q->second->setReg(NewReg);
768 // We just went back in time and modified history; the
769 // liveness information for the anti-depenence reg is now
770 // inconsistent. Set the state as if it were dead.
771 Classes[NewReg] = Classes[AntiDepReg];
772 DefIndices[NewReg] = DefIndices[AntiDepReg];
773 KillIndices[NewReg] = KillIndices[AntiDepReg];
774 assert(((KillIndices[NewReg] == ~0u) !=
775 (DefIndices[NewReg] == ~0u)) &&
776 "Kill and Def maps aren't consistent for NewReg!");
778 Classes[AntiDepReg] = 0;
779 DefIndices[AntiDepReg] = KillIndices[AntiDepReg];
780 KillIndices[AntiDepReg] = ~0u;
781 assert(((KillIndices[AntiDepReg] == ~0u) !=
782 (DefIndices[AntiDepReg] == ~0u)) &&
783 "Kill and Def maps aren't consistent for AntiDepReg!");
785 RegRefs.erase(AntiDepReg);
787 LastNewReg[AntiDepReg] = NewReg;
791 ScanInstruction(MI, Count);
797 /// FixupKills - Fix the register kill flags, they may have been made
798 /// incorrect by instruction reordering.
800 void SchedulePostRATDList::FixupKills(MachineBasicBlock *MBB) {
801 DEBUG(errs() << "Fixup kills for BB ID#" << MBB->getNumber() << '\n');
803 std::set<unsigned> killedRegs;
804 BitVector ReservedRegs = TRI->getReservedRegs(MF);
806 // Examine block from end to start...
807 unsigned Count = MBB->size();
808 for (MachineBasicBlock::iterator I = MBB->end(), E = MBB->begin();
810 MachineInstr *MI = --I;
812 // Update liveness. Registers that are defed but not used in this
813 // instruction are now dead. Mark register and all subregs as they
814 // are completely defined.
815 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
816 MachineOperand &MO = MI->getOperand(i);
817 if (!MO.isReg()) continue;
818 unsigned Reg = MO.getReg();
819 if (Reg == 0) continue;
820 if (!MO.isDef()) continue;
821 // Ignore two-addr defs.
822 if (MI->isRegTiedToUseOperand(i)) continue;
824 KillIndices[Reg] = ~0u;
826 // Repeat for all subregs.
827 for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
829 KillIndices[*Subreg] = ~0u;
833 // Examine all used registers and set kill flag. When a register
834 // is used multiple times we only set the kill flag on the first
837 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
838 MachineOperand &MO = MI->getOperand(i);
839 if (!MO.isReg() || !MO.isUse()) continue;
840 unsigned Reg = MO.getReg();
841 if ((Reg == 0) || ReservedRegs.test(Reg)) continue;
844 if (killedRegs.find(Reg) == killedRegs.end()) {
846 // A register is not killed if any subregs are live...
847 for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
849 if (KillIndices[*Subreg] != ~0u) {
855 // If subreg is not live, then register is killed if it became
856 // live in this instruction
858 kill = (KillIndices[Reg] == ~0u);
861 if (MO.isKill() != kill) {
863 DEBUG(errs() << "Fixed " << MO << " in ");
867 killedRegs.insert(Reg);
870 // Mark any used register (that is not using undef) and subregs as
872 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
873 MachineOperand &MO = MI->getOperand(i);
874 if (!MO.isReg() || !MO.isUse() || MO.isUndef()) continue;
875 unsigned Reg = MO.getReg();
876 if ((Reg == 0) || ReservedRegs.test(Reg)) continue;
878 KillIndices[Reg] = Count;
880 for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
882 KillIndices[*Subreg] = Count;
888 //===----------------------------------------------------------------------===//
889 // Top-Down Scheduling
890 //===----------------------------------------------------------------------===//
892 /// ReleaseSucc - Decrement the NumPredsLeft count of a successor. Add it to
893 /// the PendingQueue if the count reaches zero. Also update its cycle bound.
894 void SchedulePostRATDList::ReleaseSucc(SUnit *SU, SDep *SuccEdge) {
895 SUnit *SuccSU = SuccEdge->getSUnit();
896 --SuccSU->NumPredsLeft;
899 if (SuccSU->NumPredsLeft < 0) {
900 errs() << "*** Scheduling failed! ***\n";
902 errs() << " has been released too many times!\n";
907 // Compute how many cycles it will be before this actually becomes
908 // available. This is the max of the start time of all predecessors plus
910 SuccSU->setDepthToAtLeast(SU->getDepth() + SuccEdge->getLatency());
912 // If all the node's predecessors are scheduled, this node is ready
913 // to be scheduled. Ignore the special ExitSU node.
914 if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU)
915 PendingQueue.push_back(SuccSU);
918 /// ReleaseSuccessors - Call ReleaseSucc on each of SU's successors.
919 void SchedulePostRATDList::ReleaseSuccessors(SUnit *SU) {
920 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
922 ReleaseSucc(SU, &*I);
925 /// ScheduleNodeTopDown - Add the node to the schedule. Decrement the pending
926 /// count of its successors. If a successor pending count is zero, add it to
927 /// the Available queue.
928 void SchedulePostRATDList::ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle) {
929 DEBUG(errs() << "*** Scheduling [" << CurCycle << "]: ");
930 DEBUG(SU->dump(this));
932 Sequence.push_back(SU);
933 assert(CurCycle >= SU->getDepth() && "Node scheduled above its depth!");
934 SU->setDepthToAtLeast(CurCycle);
936 ReleaseSuccessors(SU);
937 SU->isScheduled = true;
938 AvailableQueue.ScheduledNode(SU);
941 /// ListScheduleTopDown - The main loop of list scheduling for top-down
943 void SchedulePostRATDList::ListScheduleTopDown() {
944 unsigned CurCycle = 0;
946 // Release any successors of the special Entry node.
947 ReleaseSuccessors(&EntrySU);
949 // All leaves to Available queue.
950 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
951 // It is available if it has no predecessors.
952 if (SUnits[i].Preds.empty()) {
953 AvailableQueue.push(&SUnits[i]);
954 SUnits[i].isAvailable = true;
958 // In any cycle where we can't schedule any instructions, we must
959 // stall or emit a noop, depending on the target.
960 bool CycleInstCnt = 0;
962 // While Available queue is not empty, grab the node with the highest
963 // priority. If it is not ready put it back. Schedule the node.
964 std::vector<SUnit*> NotReady;
965 Sequence.reserve(SUnits.size());
966 while (!AvailableQueue.empty() || !PendingQueue.empty()) {
967 // Check to see if any of the pending instructions are ready to issue. If
968 // so, add them to the available queue.
969 unsigned MinDepth = ~0u;
970 for (unsigned i = 0, e = PendingQueue.size(); i != e; ++i) {
971 if (PendingQueue[i]->getDepth() <= CurCycle) {
972 AvailableQueue.push(PendingQueue[i]);
973 PendingQueue[i]->isAvailable = true;
974 PendingQueue[i] = PendingQueue.back();
975 PendingQueue.pop_back();
977 } else if (PendingQueue[i]->getDepth() < MinDepth)
978 MinDepth = PendingQueue[i]->getDepth();
981 DEBUG(errs() << "\n*** Examining Available\n";
982 LatencyPriorityQueue q = AvailableQueue;
985 errs() << "Height " << su->getHeight() << ": ";
989 SUnit *FoundSUnit = 0;
991 bool HasNoopHazards = false;
992 while (!AvailableQueue.empty()) {
993 SUnit *CurSUnit = AvailableQueue.pop();
995 ScheduleHazardRecognizer::HazardType HT =
996 HazardRec->getHazardType(CurSUnit);
997 if (HT == ScheduleHazardRecognizer::NoHazard) {
998 FoundSUnit = CurSUnit;
1002 // Remember if this is a noop hazard.
1003 HasNoopHazards |= HT == ScheduleHazardRecognizer::NoopHazard;
1005 NotReady.push_back(CurSUnit);
1008 // Add the nodes that aren't ready back onto the available list.
1009 if (!NotReady.empty()) {
1010 AvailableQueue.push_all(NotReady);
1014 // If we found a node to schedule, do it now.
1016 ScheduleNodeTopDown(FoundSUnit, CurCycle);
1017 HazardRec->EmitInstruction(FoundSUnit);
1020 // If we are using the target-specific hazards, then don't
1021 // advance the cycle time just because we schedule a node. If
1022 // the target allows it we can schedule multiple nodes in the
1024 if (!EnablePostRAHazardAvoidance) {
1025 if (FoundSUnit->Latency) // Don't increment CurCycle for pseudo-ops!
1029 if (CycleInstCnt > 0) {
1030 DEBUG(errs() << "*** Finished cycle " << CurCycle << '\n');
1031 HazardRec->AdvanceCycle();
1032 } else if (!HasNoopHazards) {
1033 // Otherwise, we have a pipeline stall, but no other problem,
1034 // just advance the current cycle and try again.
1035 DEBUG(errs() << "*** Stall in cycle " << CurCycle << '\n');
1036 HazardRec->AdvanceCycle();
1039 // Otherwise, we have no instructions to issue and we have instructions
1040 // that will fault if we don't do this right. This is the case for
1041 // processors without pipeline interlocks and other cases.
1042 DEBUG(errs() << "*** Emitting noop in cycle " << CurCycle << '\n');
1043 HazardRec->EmitNoop();
1044 Sequence.push_back(0); // NULL here means noop
1054 VerifySchedule(/*isBottomUp=*/false);
1058 //===----------------------------------------------------------------------===//
1059 // Public Constructor Functions
1060 //===----------------------------------------------------------------------===//
1062 FunctionPass *llvm::createPostRAScheduler() {
1063 return new PostRAScheduler();