1 //===----- SchedulePostRAList.cpp - list scheduler ------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements a top-down list scheduler, using standard algorithms.
11 // The basic approach uses a priority queue of available nodes to schedule.
12 // One at a time, nodes are taken from the priority queue (thus in priority
13 // order), checked for legality to schedule, and emitted if legal.
15 // Nodes may not be legal to schedule either due to structural hazards (e.g.
16 // pipeline or resource constraints) or because an input to the instruction has
17 // not completed execution.
19 //===----------------------------------------------------------------------===//
21 #include "llvm/CodeGen/Passes.h"
22 #include "AggressiveAntiDepBreaker.h"
23 #include "AntiDepBreaker.h"
24 #include "CriticalAntiDepBreaker.h"
25 #include "llvm/ADT/BitVector.h"
26 #include "llvm/ADT/Statistic.h"
27 #include "llvm/Analysis/AliasAnalysis.h"
28 #include "llvm/CodeGen/LatencyPriorityQueue.h"
29 #include "llvm/CodeGen/MachineDominators.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunctionPass.h"
32 #include "llvm/CodeGen/MachineLoopInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/CodeGen/RegisterClassInfo.h"
35 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
36 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
37 #include "llvm/CodeGen/SchedulerRegistry.h"
38 #include "llvm/Support/CommandLine.h"
39 #include "llvm/Support/Debug.h"
40 #include "llvm/Support/ErrorHandling.h"
41 #include "llvm/Support/raw_ostream.h"
42 #include "llvm/Target/TargetInstrInfo.h"
43 #include "llvm/Target/TargetLowering.h"
44 #include "llvm/Target/TargetRegisterInfo.h"
45 #include "llvm/Target/TargetSubtargetInfo.h"
48 #define DEBUG_TYPE "post-RA-sched"
50 STATISTIC(NumNoops, "Number of noops inserted");
51 STATISTIC(NumStalls, "Number of pipeline stalls");
52 STATISTIC(NumFixedAnti, "Number of fixed anti-dependencies");
54 // Post-RA scheduling is enabled with
55 // TargetSubtargetInfo.enablePostRAScheduler(). This flag can be used to
56 // override the target.
58 EnablePostRAScheduler("post-RA-scheduler",
59 cl::desc("Enable scheduling after register allocation"),
60 cl::init(false), cl::Hidden);
61 static cl::opt<std::string>
62 EnableAntiDepBreaking("break-anti-dependencies",
63 cl::desc("Break post-RA scheduling anti-dependencies: "
64 "\"critical\", \"all\", or \"none\""),
65 cl::init("none"), cl::Hidden);
67 // If DebugDiv > 0 then only schedule MBB with (ID % DebugDiv) == DebugMod
69 DebugDiv("postra-sched-debugdiv",
70 cl::desc("Debug control MBBs that are scheduled"),
71 cl::init(0), cl::Hidden);
73 DebugMod("postra-sched-debugmod",
74 cl::desc("Debug control MBBs that are scheduled"),
75 cl::init(0), cl::Hidden);
77 AntiDepBreaker::~AntiDepBreaker() { }
80 class PostRAScheduler : public MachineFunctionPass {
81 const TargetInstrInfo *TII;
82 RegisterClassInfo RegClassInfo;
86 PostRAScheduler() : MachineFunctionPass(ID) {}
88 void getAnalysisUsage(AnalysisUsage &AU) const override {
90 AU.addRequired<AAResultsWrapperPass>();
91 AU.addRequired<TargetPassConfig>();
92 AU.addRequired<MachineDominatorTree>();
93 AU.addPreserved<MachineDominatorTree>();
94 AU.addRequired<MachineLoopInfo>();
95 AU.addPreserved<MachineLoopInfo>();
96 MachineFunctionPass::getAnalysisUsage(AU);
99 bool runOnMachineFunction(MachineFunction &Fn) override;
101 bool enablePostRAScheduler(
102 const TargetSubtargetInfo &ST, CodeGenOpt::Level OptLevel,
103 TargetSubtargetInfo::AntiDepBreakMode &Mode,
104 TargetSubtargetInfo::RegClassVector &CriticalPathRCs) const;
106 char PostRAScheduler::ID = 0;
108 class SchedulePostRATDList : public ScheduleDAGInstrs {
109 /// AvailableQueue - The priority queue to use for the available SUnits.
111 LatencyPriorityQueue AvailableQueue;
113 /// PendingQueue - This contains all of the instructions whose operands have
114 /// been issued, but their results are not ready yet (due to the latency of
115 /// the operation). Once the operands becomes available, the instruction is
116 /// added to the AvailableQueue.
117 std::vector<SUnit*> PendingQueue;
119 /// HazardRec - The hazard recognizer to use.
120 ScheduleHazardRecognizer *HazardRec;
122 /// AntiDepBreak - Anti-dependence breaking object, or NULL if none
123 AntiDepBreaker *AntiDepBreak;
125 /// AA - AliasAnalysis for making memory reference queries.
128 /// The schedule. Null SUnit*'s represent noop instructions.
129 std::vector<SUnit*> Sequence;
131 /// The index in BB of RegionEnd.
133 /// This is the instruction number from the top of the current block, not
134 /// the SlotIndex. It is only used by the AntiDepBreaker.
138 SchedulePostRATDList(
139 MachineFunction &MF, MachineLoopInfo &MLI, AliasAnalysis *AA,
140 const RegisterClassInfo &,
141 TargetSubtargetInfo::AntiDepBreakMode AntiDepMode,
142 SmallVectorImpl<const TargetRegisterClass *> &CriticalPathRCs);
144 ~SchedulePostRATDList() override;
146 /// startBlock - Initialize register live-range state for scheduling in
149 void startBlock(MachineBasicBlock *BB) override;
151 // Set the index of RegionEnd within the current BB.
152 void setEndIndex(unsigned EndIdx) { EndIndex = EndIdx; }
154 /// Initialize the scheduler state for the next scheduling region.
155 void enterRegion(MachineBasicBlock *bb,
156 MachineBasicBlock::iterator begin,
157 MachineBasicBlock::iterator end,
158 unsigned regioninstrs) override;
160 /// Notify that the scheduler has finished scheduling the current region.
161 void exitRegion() override;
163 /// Schedule - Schedule the instruction range using list scheduling.
165 void schedule() override;
169 /// Observe - Update liveness information to account for the current
170 /// instruction, which will not be scheduled.
172 void Observe(MachineInstr *MI, unsigned Count);
174 /// finishBlock - Clean up register live-range state.
176 void finishBlock() override;
179 void ReleaseSucc(SUnit *SU, SDep *SuccEdge);
180 void ReleaseSuccessors(SUnit *SU);
181 void ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle);
182 void ListScheduleTopDown();
184 void dumpSchedule() const;
185 void emitNoop(unsigned CurCycle);
189 char &llvm::PostRASchedulerID = PostRAScheduler::ID;
191 INITIALIZE_PASS(PostRAScheduler, "post-RA-sched",
192 "Post RA top-down list latency scheduler", false, false)
194 SchedulePostRATDList::SchedulePostRATDList(
195 MachineFunction &MF, MachineLoopInfo &MLI, AliasAnalysis *AA,
196 const RegisterClassInfo &RCI,
197 TargetSubtargetInfo::AntiDepBreakMode AntiDepMode,
198 SmallVectorImpl<const TargetRegisterClass *> &CriticalPathRCs)
199 : ScheduleDAGInstrs(MF, &MLI, /*IsPostRA=*/true), AA(AA), EndIndex(0) {
201 const InstrItineraryData *InstrItins =
202 MF.getSubtarget().getInstrItineraryData();
204 MF.getSubtarget().getInstrInfo()->CreateTargetPostRAHazardRecognizer(
207 assert((AntiDepMode == TargetSubtargetInfo::ANTIDEP_NONE ||
208 MRI.tracksLiveness()) &&
209 "Live-ins must be accurate for anti-dependency breaking");
211 ((AntiDepMode == TargetSubtargetInfo::ANTIDEP_ALL) ?
212 (AntiDepBreaker *)new AggressiveAntiDepBreaker(MF, RCI, CriticalPathRCs) :
213 ((AntiDepMode == TargetSubtargetInfo::ANTIDEP_CRITICAL) ?
214 (AntiDepBreaker *)new CriticalAntiDepBreaker(MF, RCI) : nullptr));
217 SchedulePostRATDList::~SchedulePostRATDList() {
222 /// Initialize state associated with the next scheduling region.
223 void SchedulePostRATDList::enterRegion(MachineBasicBlock *bb,
224 MachineBasicBlock::iterator begin,
225 MachineBasicBlock::iterator end,
226 unsigned regioninstrs) {
227 ScheduleDAGInstrs::enterRegion(bb, begin, end, regioninstrs);
231 /// Print the schedule before exiting the region.
232 void SchedulePostRATDList::exitRegion() {
234 dbgs() << "*** Final schedule ***\n";
238 ScheduleDAGInstrs::exitRegion();
241 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
242 /// dumpSchedule - dump the scheduled Sequence.
243 void SchedulePostRATDList::dumpSchedule() const {
244 for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
245 if (SUnit *SU = Sequence[i])
248 dbgs() << "**** NOOP ****\n";
253 bool PostRAScheduler::enablePostRAScheduler(
254 const TargetSubtargetInfo &ST,
255 CodeGenOpt::Level OptLevel,
256 TargetSubtargetInfo::AntiDepBreakMode &Mode,
257 TargetSubtargetInfo::RegClassVector &CriticalPathRCs) const {
258 Mode = ST.getAntiDepBreakMode();
259 ST.getCriticalPathRCs(CriticalPathRCs);
260 return ST.enablePostRAScheduler() &&
261 OptLevel >= ST.getOptLevelToEnablePostRAScheduler();
264 bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) {
265 if (skipOptnoneFunction(*Fn.getFunction()))
268 TII = Fn.getSubtarget().getInstrInfo();
269 MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>();
270 AliasAnalysis *AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
271 TargetPassConfig *PassConfig = &getAnalysis<TargetPassConfig>();
273 RegClassInfo.runOnMachineFunction(Fn);
275 // Check for explicit enable/disable of post-ra scheduling.
276 TargetSubtargetInfo::AntiDepBreakMode AntiDepMode =
277 TargetSubtargetInfo::ANTIDEP_NONE;
278 SmallVector<const TargetRegisterClass*, 4> CriticalPathRCs;
279 if (EnablePostRAScheduler.getPosition() > 0) {
280 if (!EnablePostRAScheduler)
283 // Check that post-RA scheduling is enabled for this target.
284 // This may upgrade the AntiDepMode.
285 if (!enablePostRAScheduler(Fn.getSubtarget(), PassConfig->getOptLevel(),
286 AntiDepMode, CriticalPathRCs))
290 // Check for antidep breaking override...
291 if (EnableAntiDepBreaking.getPosition() > 0) {
292 AntiDepMode = (EnableAntiDepBreaking == "all")
293 ? TargetSubtargetInfo::ANTIDEP_ALL
294 : ((EnableAntiDepBreaking == "critical")
295 ? TargetSubtargetInfo::ANTIDEP_CRITICAL
296 : TargetSubtargetInfo::ANTIDEP_NONE);
299 DEBUG(dbgs() << "PostRAScheduler\n");
301 SchedulePostRATDList Scheduler(Fn, MLI, AA, RegClassInfo, AntiDepMode,
304 // Loop over all of the basic blocks
305 for (auto &MBB : Fn) {
307 // If DebugDiv > 0 then only schedule MBB with (ID % DebugDiv) == DebugMod
309 static int bbcnt = 0;
310 if (bbcnt++ % DebugDiv != DebugMod)
312 dbgs() << "*** DEBUG scheduling " << Fn.getName()
313 << ":BB#" << MBB.getNumber() << " ***\n";
317 // Initialize register live-range state for scheduling in this block.
318 Scheduler.startBlock(&MBB);
320 // Schedule each sequence of instructions not interrupted by a label
321 // or anything else that effectively needs to shut down scheduling.
322 MachineBasicBlock::iterator Current = MBB.end();
323 unsigned Count = MBB.size(), CurrentCount = Count;
324 for (MachineBasicBlock::iterator I = Current; I != MBB.begin();) {
325 MachineInstr *MI = std::prev(I);
327 // Calls are not scheduling boundaries before register allocation, but
328 // post-ra we don't gain anything by scheduling across calls since we
329 // don't need to worry about register pressure.
330 if (MI->isCall() || TII->isSchedulingBoundary(MI, &MBB, Fn)) {
331 Scheduler.enterRegion(&MBB, I, Current, CurrentCount - Count);
332 Scheduler.setEndIndex(CurrentCount);
333 Scheduler.schedule();
334 Scheduler.exitRegion();
335 Scheduler.EmitSchedule();
337 CurrentCount = Count;
338 Scheduler.Observe(MI, CurrentCount);
342 Count -= MI->getBundleSize();
344 assert(Count == 0 && "Instruction count mismatch!");
345 assert((MBB.begin() == Current || CurrentCount != 0) &&
346 "Instruction count mismatch!");
347 Scheduler.enterRegion(&MBB, MBB.begin(), Current, CurrentCount);
348 Scheduler.setEndIndex(CurrentCount);
349 Scheduler.schedule();
350 Scheduler.exitRegion();
351 Scheduler.EmitSchedule();
353 // Clean up register live-range state.
354 Scheduler.finishBlock();
356 // Update register kills
357 Scheduler.fixupKills(&MBB);
363 /// StartBlock - Initialize register live-range state for scheduling in
366 void SchedulePostRATDList::startBlock(MachineBasicBlock *BB) {
367 // Call the superclass.
368 ScheduleDAGInstrs::startBlock(BB);
370 // Reset the hazard recognizer and anti-dep breaker.
373 AntiDepBreak->StartBlock(BB);
376 /// Schedule - Schedule the instruction range using list scheduling.
378 void SchedulePostRATDList::schedule() {
379 // Build the scheduling graph.
384 AntiDepBreak->BreakAntiDependencies(SUnits, RegionBegin, RegionEnd,
385 EndIndex, DbgValues);
388 // We made changes. Update the dependency graph.
389 // Theoretically we could update the graph in place:
390 // When a live range is changed to use a different register, remove
391 // the def's anti-dependence *and* output-dependence edges due to
392 // that register, and add new anti-dependence and output-dependence
393 // edges based on the next live range of the register.
394 ScheduleDAG::clearDAG();
397 NumFixedAnti += Broken;
401 DEBUG(dbgs() << "********** List Scheduling **********\n");
402 DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
403 SUnits[su].dumpAll(this));
405 AvailableQueue.initNodes(SUnits);
406 ListScheduleTopDown();
407 AvailableQueue.releaseState();
410 /// Observe - Update liveness information to account for the current
411 /// instruction, which will not be scheduled.
413 void SchedulePostRATDList::Observe(MachineInstr *MI, unsigned Count) {
415 AntiDepBreak->Observe(MI, Count, EndIndex);
418 /// FinishBlock - Clean up register live-range state.
420 void SchedulePostRATDList::finishBlock() {
422 AntiDepBreak->FinishBlock();
424 // Call the superclass.
425 ScheduleDAGInstrs::finishBlock();
428 //===----------------------------------------------------------------------===//
429 // Top-Down Scheduling
430 //===----------------------------------------------------------------------===//
432 /// ReleaseSucc - Decrement the NumPredsLeft count of a successor. Add it to
433 /// the PendingQueue if the count reaches zero.
434 void SchedulePostRATDList::ReleaseSucc(SUnit *SU, SDep *SuccEdge) {
435 SUnit *SuccSU = SuccEdge->getSUnit();
437 if (SuccEdge->isWeak()) {
438 --SuccSU->WeakPredsLeft;
442 if (SuccSU->NumPredsLeft == 0) {
443 dbgs() << "*** Scheduling failed! ***\n";
445 dbgs() << " has been released too many times!\n";
446 llvm_unreachable(nullptr);
449 --SuccSU->NumPredsLeft;
451 // Standard scheduler algorithms will recompute the depth of the successor
453 // SuccSU->setDepthToAtLeast(SU->getDepth() + SuccEdge->getLatency());
455 // However, we lazily compute node depth instead. Note that
456 // ScheduleNodeTopDown has already updated the depth of this node which causes
457 // all descendents to be marked dirty. Setting the successor depth explicitly
458 // here would cause depth to be recomputed for all its ancestors. If the
459 // successor is not yet ready (because of a transitively redundant edge) then
460 // this causes depth computation to be quadratic in the size of the DAG.
462 // If all the node's predecessors are scheduled, this node is ready
463 // to be scheduled. Ignore the special ExitSU node.
464 if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU)
465 PendingQueue.push_back(SuccSU);
468 /// ReleaseSuccessors - Call ReleaseSucc on each of SU's successors.
469 void SchedulePostRATDList::ReleaseSuccessors(SUnit *SU) {
470 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
472 ReleaseSucc(SU, &*I);
476 /// ScheduleNodeTopDown - Add the node to the schedule. Decrement the pending
477 /// count of its successors. If a successor pending count is zero, add it to
478 /// the Available queue.
479 void SchedulePostRATDList::ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle) {
480 DEBUG(dbgs() << "*** Scheduling [" << CurCycle << "]: ");
481 DEBUG(SU->dump(this));
483 Sequence.push_back(SU);
484 assert(CurCycle >= SU->getDepth() &&
485 "Node scheduled above its depth!");
486 SU->setDepthToAtLeast(CurCycle);
488 ReleaseSuccessors(SU);
489 SU->isScheduled = true;
490 AvailableQueue.scheduledNode(SU);
493 /// emitNoop - Add a noop to the current instruction sequence.
494 void SchedulePostRATDList::emitNoop(unsigned CurCycle) {
495 DEBUG(dbgs() << "*** Emitting noop in cycle " << CurCycle << '\n');
496 HazardRec->EmitNoop();
497 Sequence.push_back(nullptr); // NULL here means noop
501 /// ListScheduleTopDown - The main loop of list scheduling for top-down
503 void SchedulePostRATDList::ListScheduleTopDown() {
504 unsigned CurCycle = 0;
506 // We're scheduling top-down but we're visiting the regions in
507 // bottom-up order, so we don't know the hazards at the start of a
508 // region. So assume no hazards (this should usually be ok as most
509 // blocks are a single region).
512 // Release any successors of the special Entry node.
513 ReleaseSuccessors(&EntrySU);
515 // Add all leaves to Available queue.
516 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
517 // It is available if it has no predecessors.
518 if (!SUnits[i].NumPredsLeft && !SUnits[i].isAvailable) {
519 AvailableQueue.push(&SUnits[i]);
520 SUnits[i].isAvailable = true;
524 // In any cycle where we can't schedule any instructions, we must
525 // stall or emit a noop, depending on the target.
526 bool CycleHasInsts = false;
528 // While Available queue is not empty, grab the node with the highest
529 // priority. If it is not ready put it back. Schedule the node.
530 std::vector<SUnit*> NotReady;
531 Sequence.reserve(SUnits.size());
532 while (!AvailableQueue.empty() || !PendingQueue.empty()) {
533 // Check to see if any of the pending instructions are ready to issue. If
534 // so, add them to the available queue.
535 unsigned MinDepth = ~0u;
536 for (unsigned i = 0, e = PendingQueue.size(); i != e; ++i) {
537 if (PendingQueue[i]->getDepth() <= CurCycle) {
538 AvailableQueue.push(PendingQueue[i]);
539 PendingQueue[i]->isAvailable = true;
540 PendingQueue[i] = PendingQueue.back();
541 PendingQueue.pop_back();
543 } else if (PendingQueue[i]->getDepth() < MinDepth)
544 MinDepth = PendingQueue[i]->getDepth();
547 DEBUG(dbgs() << "\n*** Examining Available\n"; AvailableQueue.dump(this));
549 SUnit *FoundSUnit = nullptr, *NotPreferredSUnit = nullptr;
550 bool HasNoopHazards = false;
551 while (!AvailableQueue.empty()) {
552 SUnit *CurSUnit = AvailableQueue.pop();
554 ScheduleHazardRecognizer::HazardType HT =
555 HazardRec->getHazardType(CurSUnit, 0/*no stalls*/);
556 if (HT == ScheduleHazardRecognizer::NoHazard) {
557 if (HazardRec->ShouldPreferAnother(CurSUnit)) {
558 if (!NotPreferredSUnit) {
559 // If this is the first non-preferred node for this cycle, then
560 // record it and continue searching for a preferred node. If this
561 // is not the first non-preferred node, then treat it as though
562 // there had been a hazard.
563 NotPreferredSUnit = CurSUnit;
567 FoundSUnit = CurSUnit;
572 // Remember if this is a noop hazard.
573 HasNoopHazards |= HT == ScheduleHazardRecognizer::NoopHazard;
575 NotReady.push_back(CurSUnit);
578 // If we have a non-preferred node, push it back onto the available list.
579 // If we did not find a preferred node, then schedule this first
580 // non-preferred node.
581 if (NotPreferredSUnit) {
583 DEBUG(dbgs() << "*** Will schedule a non-preferred instruction...\n");
584 FoundSUnit = NotPreferredSUnit;
586 AvailableQueue.push(NotPreferredSUnit);
589 NotPreferredSUnit = nullptr;
592 // Add the nodes that aren't ready back onto the available list.
593 if (!NotReady.empty()) {
594 AvailableQueue.push_all(NotReady);
598 // If we found a node to schedule...
600 // If we need to emit noops prior to this instruction, then do so.
601 unsigned NumPreNoops = HazardRec->PreEmitNoops(FoundSUnit);
602 for (unsigned i = 0; i != NumPreNoops; ++i)
605 // ... schedule the node...
606 ScheduleNodeTopDown(FoundSUnit, CurCycle);
607 HazardRec->EmitInstruction(FoundSUnit);
608 CycleHasInsts = true;
609 if (HazardRec->atIssueLimit()) {
610 DEBUG(dbgs() << "*** Max instructions per cycle " << CurCycle << '\n');
611 HazardRec->AdvanceCycle();
613 CycleHasInsts = false;
617 DEBUG(dbgs() << "*** Finished cycle " << CurCycle << '\n');
618 HazardRec->AdvanceCycle();
619 } else if (!HasNoopHazards) {
620 // Otherwise, we have a pipeline stall, but no other problem,
621 // just advance the current cycle and try again.
622 DEBUG(dbgs() << "*** Stall in cycle " << CurCycle << '\n');
623 HazardRec->AdvanceCycle();
626 // Otherwise, we have no instructions to issue and we have instructions
627 // that will fault if we don't do this right. This is the case for
628 // processors without pipeline interlocks and other cases.
633 CycleHasInsts = false;
638 unsigned ScheduledNodes = VerifyScheduledDAG(/*isBottomUp=*/false);
640 for (unsigned i = 0, e = Sequence.size(); i != e; ++i)
643 assert(Sequence.size() - Noops == ScheduledNodes &&
644 "The number of nodes scheduled doesn't match the expected number!");
648 // EmitSchedule - Emit the machine code in scheduled order.
649 void SchedulePostRATDList::EmitSchedule() {
650 RegionBegin = RegionEnd;
652 // If first instruction was a DBG_VALUE then put it back.
654 BB->splice(RegionEnd, BB, FirstDbgValue);
656 // Then re-insert them according to the given schedule.
657 for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
658 if (SUnit *SU = Sequence[i])
659 BB->splice(RegionEnd, BB, SU->getInstr());
661 // Null SUnit* is a noop.
662 TII->insertNoop(*BB, RegionEnd);
664 // Update the Begin iterator, as the first instruction in the block
665 // may have been scheduled later.
667 RegionBegin = std::prev(RegionEnd);
670 // Reinsert any remaining debug_values.
671 for (std::vector<std::pair<MachineInstr *, MachineInstr *> >::iterator
672 DI = DbgValues.end(), DE = DbgValues.begin(); DI != DE; --DI) {
673 std::pair<MachineInstr *, MachineInstr *> P = *std::prev(DI);
674 MachineInstr *DbgValue = P.first;
675 MachineBasicBlock::iterator OrigPrivMI = P.second;
676 BB->splice(++OrigPrivMI, BB, DbgValue);
679 FirstDbgValue = nullptr;