1 //===-- Passes.cpp - Target independent code generation passes ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines interfaces to access the target independent code
11 // generation passes provided by the LLVM backend.
13 //===---------------------------------------------------------------------===//
15 #include "llvm/Analysis/Passes.h"
16 #include "llvm/Analysis/Verifier.h"
17 #include "llvm/Transforms/Scalar.h"
18 #include "llvm/PassManager.h"
19 #include "llvm/CodeGen/GCStrategy.h"
20 #include "llvm/CodeGen/MachineFunctionPass.h"
21 #include "llvm/CodeGen/Passes.h"
22 #include "llvm/CodeGen/RegAllocRegistry.h"
23 #include "llvm/Target/TargetLowering.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/Assembly/PrintModulePass.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/ErrorHandling.h"
32 static cl::opt<bool> DisablePostRA("disable-post-ra", cl::Hidden,
33 cl::desc("Disable Post Regalloc"));
34 static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
35 cl::desc("Disable branch folding"));
36 static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
37 cl::desc("Disable tail duplication"));
38 static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
39 cl::desc("Disable pre-register allocation tail duplication"));
40 static cl::opt<bool> EnableBlockPlacement("enable-block-placement",
41 cl::Hidden, cl::desc("Enable probability-driven block placement"));
42 static cl::opt<bool> EnableBlockPlacementStats("enable-block-placement-stats",
43 cl::Hidden, cl::desc("Collect probability-driven block placement stats"));
44 static cl::opt<bool> DisableCodePlace("disable-code-place", cl::Hidden,
45 cl::desc("Disable code placement"));
46 static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
47 cl::desc("Disable Stack Slot Coloring"));
48 static cl::opt<bool> DisableMachineDCE("disable-machine-dce", cl::Hidden,
49 cl::desc("Disable Machine Dead Code Elimination"));
50 static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
51 cl::desc("Disable Machine LICM"));
52 static cl::opt<bool> DisableMachineCSE("disable-machine-cse", cl::Hidden,
53 cl::desc("Disable Machine Common Subexpression Elimination"));
54 static cl::opt<cl::boolOrDefault>
55 OptimizeRegAlloc("optimize-regalloc", cl::Hidden,
56 cl::desc("Enable optimized register allocation compilation path."));
57 static cl::opt<cl::boolOrDefault>
58 EnableMachineSched("enable-misched", cl::Hidden,
59 cl::desc("Enable the machine instruction scheduling pass."));
60 static cl::opt<bool> EnableStrongPHIElim("strong-phi-elim", cl::Hidden,
61 cl::desc("Use strong PHI elimination."));
62 static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm",
64 cl::desc("Disable Machine LICM"));
65 static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
66 cl::desc("Disable Machine Sinking"));
67 static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
68 cl::desc("Disable Loop Strength Reduction Pass"));
69 static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
70 cl::desc("Disable Codegen Prepare"));
71 static cl::opt<bool> DisableCopyProp("disable-copyprop", cl::Hidden,
72 cl::desc("Disable Copy Propagation pass"));
73 static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
74 cl::desc("Print LLVM IR produced by the loop-reduce pass"));
75 static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
76 cl::desc("Print LLVM IR input to isel pass"));
77 static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
78 cl::desc("Dump garbage collector data"));
79 static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
80 cl::desc("Verify generated machine code"),
81 cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=NULL));
83 /// Allow standard passes to be disabled by command line options. This supports
84 /// simple binary flags that either suppress the pass or do nothing.
85 /// i.e. -disable-mypass=false has no effect.
86 /// These should be converted to boolOrDefault in order to use applyOverride.
87 static AnalysisID applyDisable(AnalysisID ID, bool Override) {
93 /// Allow Pass selection to be overriden by command line options. This supports
94 /// flags with ternary conditions. TargetID is passed through by default. The
95 /// pass is suppressed when the option is false. When the option is true, the
96 /// StandardID is selected if the target provides no default.
97 static AnalysisID applyOverride(AnalysisID TargetID, cl::boolOrDefault Override,
98 AnalysisID StandardID) {
103 if (TargetID != &NoPassID)
105 if (StandardID == &NoPassID)
106 report_fatal_error("Target cannot enable pass");
111 llvm_unreachable("Invalid command line option state");
114 /// Allow standard passes to be disabled by the command line, regardless of who
115 /// is adding the pass.
117 /// StandardID is the pass identified in the standard pass pipeline and provided
118 /// to addPass(). It may be a target-specific ID in the case that the target
119 /// directly adds its own pass, but in that case we harmlessly fall through.
121 /// TargetID is the pass that the target has configured to override StandardID.
123 /// StandardID may be a pseudo ID. In that case TargetID is the name of the real
124 /// pass to run. This allows multiple options to control a single pass depending
125 /// on where in the pipeline that pass is added.
126 static AnalysisID overridePass(AnalysisID StandardID, AnalysisID TargetID) {
127 if (StandardID == &PostRASchedulerID)
128 return applyDisable(TargetID, DisablePostRA);
130 if (StandardID == &BranchFolderPassID)
131 return applyDisable(TargetID, DisableBranchFold);
133 if (StandardID == &TailDuplicateID)
134 return applyDisable(TargetID, DisableTailDuplicate);
136 if (StandardID == &TargetPassConfig::EarlyTailDuplicateID)
137 return applyDisable(TargetID, DisableEarlyTailDup);
139 if (StandardID == &MachineBlockPlacementID)
140 return applyDisable(TargetID, DisableCodePlace);
142 if (StandardID == &CodePlacementOptID)
143 return applyDisable(TargetID, DisableCodePlace);
145 if (StandardID == &StackSlotColoringID)
146 return applyDisable(TargetID, DisableSSC);
148 if (StandardID == &DeadMachineInstructionElimID)
149 return applyDisable(TargetID, DisableMachineDCE);
151 if (StandardID == &MachineLICMID)
152 return applyDisable(TargetID, DisableMachineLICM);
154 if (StandardID == &MachineCSEID)
155 return applyDisable(TargetID, DisableMachineCSE);
157 if (StandardID == &MachineSchedulerID)
158 return applyOverride(TargetID, EnableMachineSched, StandardID);
160 if (StandardID == &TargetPassConfig::PostRAMachineLICMID)
161 return applyDisable(TargetID, DisablePostRAMachineLICM);
163 if (StandardID == &MachineSinkingID)
164 return applyDisable(TargetID, DisableMachineSink);
166 if (StandardID == &MachineCopyPropagationID)
167 return applyDisable(TargetID, DisableCopyProp);
172 //===---------------------------------------------------------------------===//
174 //===---------------------------------------------------------------------===//
176 INITIALIZE_PASS(TargetPassConfig, "targetpassconfig",
177 "Target Pass Configuration", false, false)
178 char TargetPassConfig::ID = 0;
180 static char NoPassIDAnchor = 0;
181 char &llvm::NoPassID = NoPassIDAnchor;
184 char TargetPassConfig::EarlyTailDuplicateID = 0;
185 char TargetPassConfig::PostRAMachineLICMID = 0;
188 class PassConfigImpl {
190 // List of passes explicitly substituted by this target. Normally this is
191 // empty, but it is a convenient way to suppress or replace specific passes
192 // that are part of a standard pass pipeline without overridding the entire
193 // pipeline. This mechanism allows target options to inherit a standard pass's
194 // user interface. For example, a target may disable a standard pass by
195 // default by substituting NoPass, and the user may still enable that standard
196 // pass with an explicit command line option.
197 DenseMap<AnalysisID,AnalysisID> TargetPasses;
201 // Out of line virtual method.
202 TargetPassConfig::~TargetPassConfig() {
206 // Out of line constructor provides default values for pass options and
207 // registers all common codegen passes.
208 TargetPassConfig::TargetPassConfig(TargetMachine *tm, PassManagerBase &pm)
209 : ImmutablePass(ID), TM(tm), PM(pm), Impl(0), Initialized(false),
210 DisableVerify(false),
211 EnableTailMerge(true) {
213 Impl = new PassConfigImpl();
215 // Register all target independent codegen passes to activate their PassIDs,
216 // including this pass itself.
217 initializeCodeGen(*PassRegistry::getPassRegistry());
219 // Substitute Pseudo Pass IDs for real ones.
220 substitutePass(EarlyTailDuplicateID, TailDuplicateID);
221 substitutePass(PostRAMachineLICMID, MachineLICMID);
223 // Temporarily disable experimental passes.
224 substitutePass(MachineSchedulerID, NoPassID);
227 /// createPassConfig - Create a pass configuration object to be used by
228 /// addPassToEmitX methods for generating a pipeline of CodeGen passes.
230 /// Targets may override this to extend TargetPassConfig.
231 TargetPassConfig *LLVMTargetMachine::createPassConfig(PassManagerBase &PM) {
232 return new TargetPassConfig(this, PM);
235 TargetPassConfig::TargetPassConfig()
236 : ImmutablePass(ID), PM(*(PassManagerBase*)0) {
237 llvm_unreachable("TargetPassConfig should not be constructed on-the-fly");
240 // Helper to verify the analysis is really immutable.
241 void TargetPassConfig::setOpt(bool &Opt, bool Val) {
242 assert(!Initialized && "PassConfig is immutable");
246 void TargetPassConfig::substitutePass(char &StandardID, char &TargetID) {
247 Impl->TargetPasses[&StandardID] = &TargetID;
250 AnalysisID TargetPassConfig::getPassSubstitution(AnalysisID ID) const {
251 DenseMap<AnalysisID, AnalysisID>::const_iterator
252 I = Impl->TargetPasses.find(ID);
253 if (I == Impl->TargetPasses.end())
258 /// Add a CodeGen pass at this point in the pipeline after checking for target
259 /// and command line overrides.
260 AnalysisID TargetPassConfig::addPass(char &ID) {
261 assert(!Initialized && "PassConfig is immutable");
263 AnalysisID TargetID = getPassSubstitution(&ID);
264 AnalysisID FinalID = overridePass(&ID, TargetID);
265 if (FinalID == &NoPassID)
268 Pass *P = Pass::createPass(FinalID);
270 llvm_unreachable("Pass ID not registered");
275 void TargetPassConfig::printNoVerify(const char *Banner) const {
276 if (TM->shouldPrintMachineCode())
277 PM.add(createMachineFunctionPrinterPass(dbgs(), Banner));
280 void TargetPassConfig::printAndVerify(const char *Banner) const {
281 if (TM->shouldPrintMachineCode())
282 PM.add(createMachineFunctionPrinterPass(dbgs(), Banner));
284 if (VerifyMachineCode)
285 PM.add(createMachineVerifierPass(Banner));
288 /// Add common target configurable passes that perform LLVM IR to IR transforms
289 /// following machine independent optimization.
290 void TargetPassConfig::addIRPasses() {
291 // Basic AliasAnalysis support.
292 // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that
293 // BasicAliasAnalysis wins if they disagree. This is intended to help
294 // support "obvious" type-punning idioms.
295 PM.add(createTypeBasedAliasAnalysisPass());
296 PM.add(createBasicAliasAnalysisPass());
298 // Before running any passes, run the verifier to determine if the input
299 // coming from the front-end and/or optimizer is valid.
301 PM.add(createVerifierPass());
303 // Run loop strength reduction before anything else.
304 if (getOptLevel() != CodeGenOpt::None && !DisableLSR) {
305 PM.add(createLoopStrengthReducePass(getTargetLowering()));
307 PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &dbgs()));
310 PM.add(createGCLoweringPass());
312 // Make sure that no unreachable blocks are instruction selected.
313 PM.add(createUnreachableBlockEliminationPass());
316 /// Add common passes that perform LLVM IR to IR transforms in preparation for
317 /// instruction selection.
318 void TargetPassConfig::addISelPrepare() {
319 if (getOptLevel() != CodeGenOpt::None && !DisableCGP)
320 PM.add(createCodeGenPreparePass(getTargetLowering()));
322 PM.add(createStackProtectorPass(getTargetLowering()));
327 PM.add(createPrintFunctionPass("\n\n"
328 "*** Final LLVM Code input to ISel ***\n",
331 // All passes which modify the LLVM IR are now complete; run the verifier
332 // to ensure that the IR is valid.
334 PM.add(createVerifierPass());
337 /// Add the complete set of target-independent postISel code generator passes.
339 /// This can be read as the standard order of major LLVM CodeGen stages. Stages
340 /// with nontrivial configuration or multiple passes are broken out below in
341 /// add%Stage routines.
343 /// Any TargetPassConfig::addXX routine may be overriden by the Target. The
344 /// addPre/Post methods with empty header implementations allow injecting
345 /// target-specific fixups just before or after major stages. Additionally,
346 /// targets have the flexibility to change pass order within a stage by
347 /// overriding default implementation of add%Stage routines below. Each
348 /// technique has maintainability tradeoffs because alternate pass orders are
349 /// not well supported. addPre/Post works better if the target pass is easily
350 /// tied to a common pass. But if it has subtle dependencies on multiple passes,
351 /// the target should override the stage instead.
353 /// TODO: We could use a single addPre/Post(ID) hook to allow pass injection
354 /// before/after any target-independent pass. But it's currently overkill.
355 void TargetPassConfig::addMachinePasses() {
356 // Print the instruction selected machine code...
357 printAndVerify("After Instruction Selection");
359 // Expand pseudo-instructions emitted by ISel.
360 addPass(ExpandISelPseudosID);
362 // Add passes that optimize machine instructions in SSA form.
363 if (getOptLevel() != CodeGenOpt::None) {
364 addMachineSSAOptimization();
367 // If the target requests it, assign local variables to stack slots relative
368 // to one another and simplify frame index references where possible.
369 addPass(LocalStackSlotAllocationID);
372 // Run pre-ra passes.
373 if (addPreRegAlloc())
374 printAndVerify("After PreRegAlloc passes");
376 // Run register allocation and passes that are tightly coupled with it,
377 // including phi elimination and scheduling.
378 if (getOptimizeRegAlloc())
379 addOptimizedRegAlloc(createRegAllocPass(true));
381 addFastRegAlloc(createRegAllocPass(false));
383 // Run post-ra passes.
384 if (addPostRegAlloc())
385 printAndVerify("After PostRegAlloc passes");
387 // Insert prolog/epilog code. Eliminate abstract frame index references...
388 addPass(PrologEpilogCodeInserterID);
389 printAndVerify("After PrologEpilogCodeInserter");
391 /// Add passes that optimize machine instructions after register allocation.
392 if (getOptLevel() != CodeGenOpt::None)
393 addMachineLateOptimization();
395 // Expand pseudo instructions before second scheduling pass.
396 addPass(ExpandPostRAPseudosID);
397 printNoVerify("After ExpandPostRAPseudos");
399 // Run pre-sched2 passes.
401 printNoVerify("After PreSched2 passes");
403 // Second pass scheduler.
404 if (getOptLevel() != CodeGenOpt::None) {
405 addPass(PostRASchedulerID);
406 printNoVerify("After PostRAScheduler");
410 addPass(GCMachineCodeAnalysisID);
412 PM.add(createGCInfoPrinter(dbgs()));
414 // Basic block placement.
415 if (getOptLevel() != CodeGenOpt::None)
418 if (addPreEmitPass())
419 printNoVerify("After PreEmit passes");
422 /// Add passes that optimize machine instructions in SSA form.
423 void TargetPassConfig::addMachineSSAOptimization() {
424 // Pre-ra tail duplication.
425 if (addPass(EarlyTailDuplicateID) != &NoPassID)
426 printAndVerify("After Pre-RegAlloc TailDuplicate");
428 // Optimize PHIs before DCE: removing dead PHI cycles may make more
429 // instructions dead.
430 addPass(OptimizePHIsID);
432 // If the target requests it, assign local variables to stack slots relative
433 // to one another and simplify frame index references where possible.
434 addPass(LocalStackSlotAllocationID);
436 // With optimization, dead code should already be eliminated. However
437 // there is one known exception: lowered code for arguments that are only
438 // used by tail calls, where the tail calls reuse the incoming stack
439 // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
440 addPass(DeadMachineInstructionElimID);
441 printAndVerify("After codegen DCE pass");
443 addPass(MachineLICMID);
444 addPass(MachineCSEID);
445 addPass(MachineSinkingID);
446 printAndVerify("After Machine LICM, CSE and Sinking passes");
448 addPass(PeepholeOptimizerID);
449 printAndVerify("After codegen peephole optimization pass");
452 //===---------------------------------------------------------------------===//
453 /// Register Allocation Pass Configuration
454 //===---------------------------------------------------------------------===//
456 bool TargetPassConfig::getOptimizeRegAlloc() const {
457 switch (OptimizeRegAlloc) {
458 case cl::BOU_UNSET: return getOptLevel() != CodeGenOpt::None;
459 case cl::BOU_TRUE: return true;
460 case cl::BOU_FALSE: return false;
462 llvm_unreachable("Invalid optimize-regalloc state");
465 /// RegisterRegAlloc's global Registry tracks allocator registration.
466 MachinePassRegistry RegisterRegAlloc::Registry;
468 /// A dummy default pass factory indicates whether the register allocator is
469 /// overridden on the command line.
470 static FunctionPass *useDefaultRegisterAllocator() { return 0; }
471 static RegisterRegAlloc
472 defaultRegAlloc("default",
473 "pick register allocator based on -O option",
474 useDefaultRegisterAllocator);
476 /// -regalloc=... command line option.
477 static cl::opt<RegisterRegAlloc::FunctionPassCtor, false,
478 RegisterPassParser<RegisterRegAlloc> >
480 cl::init(&useDefaultRegisterAllocator),
481 cl::desc("Register allocator to use"));
484 /// Instantiate the default register allocator pass for this target for either
485 /// the optimized or unoptimized allocation path. This will be added to the pass
486 /// manager by addFastRegAlloc in the unoptimized case or addOptimizedRegAlloc
487 /// in the optimized case.
489 /// A target that uses the standard regalloc pass order for fast or optimized
490 /// allocation may still override this for per-target regalloc
491 /// selection. But -regalloc=... always takes precedence.
492 FunctionPass *TargetPassConfig::createTargetRegisterAllocator(bool Optimized) {
494 return createGreedyRegisterAllocator();
496 return createFastRegisterAllocator();
499 /// Find and instantiate the register allocation pass requested by this target
500 /// at the current optimization level. Different register allocators are
501 /// defined as separate passes because they may require different analysis.
503 /// This helper ensures that the regalloc= option is always available,
504 /// even for targets that override the default allocator.
506 /// FIXME: When MachinePassRegistry register pass IDs instead of function ptrs,
507 /// this can be folded into addPass.
508 FunctionPass *TargetPassConfig::createRegAllocPass(bool Optimized) {
509 RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault();
511 // Initialize the global default.
514 RegisterRegAlloc::setDefault(RegAlloc);
516 if (Ctor != useDefaultRegisterAllocator)
519 // With no -regalloc= override, ask the target for a regalloc pass.
520 return createTargetRegisterAllocator(Optimized);
523 /// Add the minimum set of target-independent passes that are required for
524 /// register allocation. No coalescing or scheduling.
525 void TargetPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
526 addPass(PHIEliminationID);
527 addPass(TwoAddressInstructionPassID);
529 PM.add(RegAllocPass);
530 printAndVerify("After Register Allocation");
533 /// Add standard target-independent passes that are tightly coupled with
534 /// optimized register allocation, including coalescing, machine instruction
535 /// scheduling, and register allocation itself.
536 void TargetPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
537 // LiveVariables currently requires pure SSA form.
539 // FIXME: Once TwoAddressInstruction pass no longer uses kill flags,
540 // LiveVariables can be removed completely, and LiveIntervals can be directly
541 // computed. (We still either need to regenerate kill flags after regalloc, or
542 // preferably fix the scavenger to not depend on them).
543 addPass(LiveVariablesID);
545 // Add passes that move from transformed SSA into conventional SSA. This is a
546 // "copy coalescing" problem.
548 if (!EnableStrongPHIElim) {
549 // Edge splitting is smarter with machine loop info.
550 addPass(MachineLoopInfoID);
551 addPass(PHIEliminationID);
553 addPass(TwoAddressInstructionPassID);
555 // FIXME: Either remove this pass completely, or fix it so that it works on
556 // SSA form. We could modify LiveIntervals to be independent of this pass, But
557 // it would be even better to simply eliminate *all* IMPLICIT_DEFs before
559 addPass(ProcessImplicitDefsID);
561 if (EnableStrongPHIElim)
562 addPass(StrongPHIEliminationID);
564 addPass(RegisterCoalescerID);
566 // PreRA instruction scheduling.
567 addPass(MachineSchedulerID);
569 // Add the selected register allocation pass.
570 PM.add(RegAllocPass);
571 printAndVerify("After Register Allocation");
573 // FinalizeRegAlloc is convenient until MachineInstrBundles is more mature,
574 // but eventually, all users of it should probably be moved to addPostRA and
575 // it can go away. Currently, it's the intended place for targets to run
576 // FinalizeMachineBundles, because passes other than MachineScheduling an
577 // RegAlloc itself may not be aware of bundles.
578 if (addFinalizeRegAlloc())
579 printAndVerify("After RegAlloc finalization");
581 // Perform stack slot coloring and post-ra machine LICM.
583 // FIXME: Re-enable coloring with register when it's capable of adding
585 addPass(StackSlotColoringID);
587 // Run post-ra machine LICM to hoist reloads / remats.
589 // FIXME: can this move into MachineLateOptimization?
590 addPass(PostRAMachineLICMID);
592 printAndVerify("After StackSlotColoring and postra Machine LICM");
595 //===---------------------------------------------------------------------===//
596 /// Post RegAlloc Pass Configuration
597 //===---------------------------------------------------------------------===//
599 /// Add passes that optimize machine instructions after register allocation.
600 void TargetPassConfig::addMachineLateOptimization() {
601 // Branch folding must be run after regalloc and prolog/epilog insertion.
602 if (addPass(BranchFolderPassID) != &NoPassID)
603 printNoVerify("After BranchFolding");
606 if (addPass(TailDuplicateID) != &NoPassID)
607 printNoVerify("After TailDuplicate");
610 if (addPass(MachineCopyPropagationID) != &NoPassID)
611 printNoVerify("After copy propagation pass");
614 /// Add standard basic block placement passes.
615 void TargetPassConfig::addBlockPlacement() {
616 AnalysisID ID = &NoPassID;
617 if (EnableBlockPlacement) {
618 // MachineBlockPlacement is an experimental pass which is disabled by
619 // default currently. Eventually it should subsume CodePlacementOpt, so
620 // when enabled, the other is disabled.
621 ID = addPass(MachineBlockPlacementID);
623 ID = addPass(CodePlacementOptID);
625 if (ID != &NoPassID) {
626 // Run a separate pass to collect block placement statistics.
627 if (EnableBlockPlacementStats)
628 addPass(MachineBlockPlacementStatsID);
630 printNoVerify("After machine block placement.");