1 //===-- PhiElimination.cpp - Eliminate PHI nodes by inserting copies ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass eliminates machine instruction PHI nodes by inserting copy
11 // instructions. This destroys SSA information, but is the desired input for
12 // some register allocators.
14 //===----------------------------------------------------------------------===//
16 #include "llvm/CodeGen/Passes.h"
17 #include "PHIEliminationUtils.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/SmallPtrSet.h"
20 #include "llvm/ADT/Statistic.h"
21 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
22 #include "llvm/CodeGen/LiveVariables.h"
23 #include "llvm/CodeGen/MachineDominators.h"
24 #include "llvm/CodeGen/MachineInstr.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineLoopInfo.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Compiler.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Target/TargetInstrInfo.h"
33 #include "llvm/Target/TargetSubtargetInfo.h"
37 #define DEBUG_TYPE "phielim"
40 DisableEdgeSplitting("disable-phi-elim-edge-splitting", cl::init(false),
41 cl::Hidden, cl::desc("Disable critical edge splitting "
42 "during PHI elimination"));
45 SplitAllCriticalEdges("phi-elim-split-all-critical-edges", cl::init(false),
46 cl::Hidden, cl::desc("Split all critical edges during "
50 class PHIElimination : public MachineFunctionPass {
51 MachineRegisterInfo *MRI; // Machine register information
56 static char ID; // Pass identification, replacement for typeid
57 PHIElimination() : MachineFunctionPass(ID) {
58 initializePHIEliminationPass(*PassRegistry::getPassRegistry());
61 bool runOnMachineFunction(MachineFunction &Fn) override;
62 void getAnalysisUsage(AnalysisUsage &AU) const override;
65 /// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions
66 /// in predecessor basic blocks.
68 bool EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB);
69 void LowerPHINode(MachineBasicBlock &MBB,
70 MachineBasicBlock::iterator LastPHIIt);
72 /// analyzePHINodes - Gather information about the PHI nodes in
73 /// here. In particular, we want to map the number of uses of a virtual
74 /// register which is used in a PHI node. We map that to the BB the
75 /// vreg is coming from. This is used later to determine when the vreg
76 /// is killed in the BB.
78 void analyzePHINodes(const MachineFunction& Fn);
80 /// Split critical edges where necessary for good coalescer performance.
81 bool SplitPHIEdges(MachineFunction &MF, MachineBasicBlock &MBB,
82 MachineLoopInfo *MLI);
84 // These functions are temporary abstractions around LiveVariables and
85 // LiveIntervals, so they can go away when LiveVariables does.
86 bool isLiveIn(unsigned Reg, MachineBasicBlock *MBB);
87 bool isLiveOutPastPHIs(unsigned Reg, MachineBasicBlock *MBB);
89 typedef std::pair<unsigned, unsigned> BBVRegPair;
90 typedef DenseMap<BBVRegPair, unsigned> VRegPHIUse;
92 VRegPHIUse VRegPHIUseCount;
94 // Defs of PHI sources which are implicit_def.
95 SmallPtrSet<MachineInstr*, 4> ImpDefs;
97 // Map reusable lowered PHI node -> incoming join register.
98 typedef DenseMap<MachineInstr*, unsigned,
99 MachineInstrExpressionTrait> LoweredPHIMap;
100 LoweredPHIMap LoweredPHIs;
104 STATISTIC(NumLowered, "Number of phis lowered");
105 STATISTIC(NumCriticalEdgesSplit, "Number of critical edges split");
106 STATISTIC(NumReused, "Number of reused lowered phis");
108 char PHIElimination::ID = 0;
109 char& llvm::PHIEliminationID = PHIElimination::ID;
111 INITIALIZE_PASS_BEGIN(PHIElimination, "phi-node-elimination",
112 "Eliminate PHI nodes for register allocation",
114 INITIALIZE_PASS_DEPENDENCY(LiveVariables)
115 INITIALIZE_PASS_END(PHIElimination, "phi-node-elimination",
116 "Eliminate PHI nodes for register allocation", false, false)
118 void PHIElimination::getAnalysisUsage(AnalysisUsage &AU) const {
119 AU.addPreserved<LiveVariables>();
120 AU.addPreserved<SlotIndexes>();
121 AU.addPreserved<LiveIntervals>();
122 AU.addPreserved<MachineDominatorTree>();
123 AU.addPreserved<MachineLoopInfo>();
124 MachineFunctionPass::getAnalysisUsage(AU);
127 bool PHIElimination::runOnMachineFunction(MachineFunction &MF) {
128 MRI = &MF.getRegInfo();
129 LV = getAnalysisIfAvailable<LiveVariables>();
130 LIS = getAnalysisIfAvailable<LiveIntervals>();
132 bool Changed = false;
134 // This pass takes the function out of SSA form.
137 // Split critical edges to help the coalescer. This does not yet support
138 // updating LiveIntervals, so we disable it.
139 if (!DisableEdgeSplitting && (LV || LIS)) {
140 MachineLoopInfo *MLI = getAnalysisIfAvailable<MachineLoopInfo>();
141 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
142 Changed |= SplitPHIEdges(MF, *I, MLI);
145 // Populate VRegPHIUseCount
148 // Eliminate PHI instructions by inserting copies into predecessor blocks.
149 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
150 Changed |= EliminatePHINodes(MF, *I);
152 // Remove dead IMPLICIT_DEF instructions.
153 for (MachineInstr *DefMI : ImpDefs) {
154 unsigned DefReg = DefMI->getOperand(0).getReg();
155 if (MRI->use_nodbg_empty(DefReg)) {
157 LIS->RemoveMachineInstrFromMaps(DefMI);
158 DefMI->eraseFromParent();
162 // Clean up the lowered PHI instructions.
163 for (LoweredPHIMap::iterator I = LoweredPHIs.begin(), E = LoweredPHIs.end();
166 LIS->RemoveMachineInstrFromMaps(I->first);
167 MF.DeleteMachineInstr(I->first);
172 VRegPHIUseCount.clear();
177 /// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions in
178 /// predecessor basic blocks.
180 bool PHIElimination::EliminatePHINodes(MachineFunction &MF,
181 MachineBasicBlock &MBB) {
182 if (MBB.empty() || !MBB.front().isPHI())
183 return false; // Quick exit for basic blocks without PHIs.
185 // Get an iterator to the first instruction after the last PHI node (this may
186 // also be the end of the basic block).
187 MachineBasicBlock::iterator LastPHIIt =
188 std::prev(MBB.SkipPHIsAndLabels(MBB.begin()));
190 while (MBB.front().isPHI())
191 LowerPHINode(MBB, LastPHIIt);
196 /// isImplicitlyDefined - Return true if all defs of VirtReg are implicit-defs.
197 /// This includes registers with no defs.
198 static bool isImplicitlyDefined(unsigned VirtReg,
199 const MachineRegisterInfo *MRI) {
200 for (MachineInstr &DI : MRI->def_instructions(VirtReg))
201 if (!DI.isImplicitDef())
206 /// isSourceDefinedByImplicitDef - Return true if all sources of the phi node
207 /// are implicit_def's.
208 static bool isSourceDefinedByImplicitDef(const MachineInstr *MPhi,
209 const MachineRegisterInfo *MRI) {
210 for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2)
211 if (!isImplicitlyDefined(MPhi->getOperand(i).getReg(), MRI))
217 /// LowerPHINode - Lower the PHI node at the top of the specified block,
219 void PHIElimination::LowerPHINode(MachineBasicBlock &MBB,
220 MachineBasicBlock::iterator LastPHIIt) {
223 MachineBasicBlock::iterator AfterPHIsIt = std::next(LastPHIIt);
225 // Unlink the PHI node from the basic block, but don't delete the PHI yet.
226 MachineInstr *MPhi = MBB.remove(MBB.begin());
228 unsigned NumSrcs = (MPhi->getNumOperands() - 1) / 2;
229 unsigned DestReg = MPhi->getOperand(0).getReg();
230 assert(MPhi->getOperand(0).getSubReg() == 0 && "Can't handle sub-reg PHIs");
231 bool isDead = MPhi->getOperand(0).isDead();
233 // Create a new register for the incoming PHI arguments.
234 MachineFunction &MF = *MBB.getParent();
235 unsigned IncomingReg = 0;
236 bool reusedIncoming = false; // Is IncomingReg reused from an earlier PHI?
238 // Insert a register to register copy at the top of the current block (but
239 // after any remaining phi nodes) which copies the new incoming register
240 // into the phi node destination.
241 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
242 if (isSourceDefinedByImplicitDef(MPhi, MRI))
243 // If all sources of a PHI node are implicit_def, just emit an
244 // implicit_def instead of a copy.
245 BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(),
246 TII->get(TargetOpcode::IMPLICIT_DEF), DestReg);
248 // Can we reuse an earlier PHI node? This only happens for critical edges,
249 // typically those created by tail duplication.
250 unsigned &entry = LoweredPHIs[MPhi];
252 // An identical PHI node was already lowered. Reuse the incoming register.
254 reusedIncoming = true;
256 DEBUG(dbgs() << "Reusing " << PrintReg(IncomingReg) << " for " << *MPhi);
258 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg);
259 entry = IncomingReg = MF.getRegInfo().createVirtualRegister(RC);
261 BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(),
262 TII->get(TargetOpcode::COPY), DestReg)
263 .addReg(IncomingReg);
266 // Update live variable information if there is any.
268 MachineInstr *PHICopy = std::prev(AfterPHIsIt);
271 LiveVariables::VarInfo &VI = LV->getVarInfo(IncomingReg);
273 // Increment use count of the newly created virtual register.
274 LV->setPHIJoin(IncomingReg);
276 // When we are reusing the incoming register, it may already have been
277 // killed in this block. The old kill will also have been inserted at
278 // AfterPHIsIt, so it appears before the current PHICopy.
280 if (MachineInstr *OldKill = VI.findKill(&MBB)) {
281 DEBUG(dbgs() << "Remove old kill from " << *OldKill);
282 LV->removeVirtualRegisterKilled(IncomingReg, OldKill);
286 // Add information to LiveVariables to know that the incoming value is
287 // killed. Note that because the value is defined in several places (once
288 // each for each incoming block), the "def" block and instruction fields
289 // for the VarInfo is not filled in.
290 LV->addVirtualRegisterKilled(IncomingReg, PHICopy);
293 // Since we are going to be deleting the PHI node, if it is the last use of
294 // any registers, or if the value itself is dead, we need to move this
295 // information over to the new copy we just inserted.
296 LV->removeVirtualRegistersKilled(MPhi);
298 // If the result is dead, update LV.
300 LV->addVirtualRegisterDead(DestReg, PHICopy);
301 LV->removeVirtualRegisterDead(DestReg, MPhi);
305 // Update LiveIntervals for the new copy or implicit def.
307 MachineInstr *NewInstr = std::prev(AfterPHIsIt);
308 SlotIndex DestCopyIndex = LIS->InsertMachineInstrInMaps(NewInstr);
310 SlotIndex MBBStartIndex = LIS->getMBBStartIdx(&MBB);
312 // Add the region from the beginning of MBB to the copy instruction to
313 // IncomingReg's live interval.
314 LiveInterval &IncomingLI = LIS->createEmptyInterval(IncomingReg);
315 VNInfo *IncomingVNI = IncomingLI.getVNInfoAt(MBBStartIndex);
317 IncomingVNI = IncomingLI.getNextValue(MBBStartIndex,
318 LIS->getVNInfoAllocator());
319 IncomingLI.addSegment(LiveInterval::Segment(MBBStartIndex,
320 DestCopyIndex.getRegSlot(),
324 LiveInterval &DestLI = LIS->getInterval(DestReg);
325 assert(DestLI.begin() != DestLI.end() &&
326 "PHIs should have nonempty LiveIntervals.");
327 if (DestLI.endIndex().isDead()) {
328 // A dead PHI's live range begins and ends at the start of the MBB, but
329 // the lowered copy, which will still be dead, needs to begin and end at
330 // the copy instruction.
331 VNInfo *OrigDestVNI = DestLI.getVNInfoAt(MBBStartIndex);
332 assert(OrigDestVNI && "PHI destination should be live at block entry.");
333 DestLI.removeSegment(MBBStartIndex, MBBStartIndex.getDeadSlot());
334 DestLI.createDeadDef(DestCopyIndex.getRegSlot(),
335 LIS->getVNInfoAllocator());
336 DestLI.removeValNo(OrigDestVNI);
338 // Otherwise, remove the region from the beginning of MBB to the copy
339 // instruction from DestReg's live interval.
340 DestLI.removeSegment(MBBStartIndex, DestCopyIndex.getRegSlot());
341 VNInfo *DestVNI = DestLI.getVNInfoAt(DestCopyIndex.getRegSlot());
342 assert(DestVNI && "PHI destination should be live at its definition.");
343 DestVNI->def = DestCopyIndex.getRegSlot();
347 // Adjust the VRegPHIUseCount map to account for the removal of this PHI node.
348 for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2)
349 --VRegPHIUseCount[BBVRegPair(MPhi->getOperand(i+1).getMBB()->getNumber(),
350 MPhi->getOperand(i).getReg())];
352 // Now loop over all of the incoming arguments, changing them to copy into the
353 // IncomingReg register in the corresponding predecessor basic block.
354 SmallPtrSet<MachineBasicBlock*, 8> MBBsInsertedInto;
355 for (int i = NumSrcs - 1; i >= 0; --i) {
356 unsigned SrcReg = MPhi->getOperand(i*2+1).getReg();
357 unsigned SrcSubReg = MPhi->getOperand(i*2+1).getSubReg();
358 bool SrcUndef = MPhi->getOperand(i*2+1).isUndef() ||
359 isImplicitlyDefined(SrcReg, MRI);
360 assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
361 "Machine PHI Operands must all be virtual registers!");
363 // Get the MachineBasicBlock equivalent of the BasicBlock that is the source
365 MachineBasicBlock &opBlock = *MPhi->getOperand(i*2+2).getMBB();
367 // Check to make sure we haven't already emitted the copy for this block.
368 // This can happen because PHI nodes may have multiple entries for the same
370 if (!MBBsInsertedInto.insert(&opBlock).second)
371 continue; // If the copy has already been emitted, we're done.
373 // Find a safe location to insert the copy, this may be the first terminator
374 // in the block (or end()).
375 MachineBasicBlock::iterator InsertPos =
376 findPHICopyInsertPoint(&opBlock, &MBB, SrcReg);
379 MachineInstr *NewSrcInstr = nullptr;
380 if (!reusedIncoming && IncomingReg) {
382 // The source register is undefined, so there is no need for a real
383 // COPY, but we still need to ensure joint dominance by defs.
384 // Insert an IMPLICIT_DEF instruction.
385 NewSrcInstr = BuildMI(opBlock, InsertPos, MPhi->getDebugLoc(),
386 TII->get(TargetOpcode::IMPLICIT_DEF),
389 // Clean up the old implicit-def, if there even was one.
390 if (MachineInstr *DefMI = MRI->getVRegDef(SrcReg))
391 if (DefMI->isImplicitDef())
392 ImpDefs.insert(DefMI);
394 NewSrcInstr = BuildMI(opBlock, InsertPos, MPhi->getDebugLoc(),
395 TII->get(TargetOpcode::COPY), IncomingReg)
396 .addReg(SrcReg, 0, SrcSubReg);
400 // We only need to update the LiveVariables kill of SrcReg if this was the
401 // last PHI use of SrcReg to be lowered on this CFG edge and it is not live
402 // out of the predecessor. We can also ignore undef sources.
403 if (LV && !SrcUndef &&
404 !VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)] &&
405 !LV->isLiveOut(SrcReg, opBlock)) {
406 // We want to be able to insert a kill of the register if this PHI (aka,
407 // the copy we just inserted) is the last use of the source value. Live
408 // variable analysis conservatively handles this by saying that the value
409 // is live until the end of the block the PHI entry lives in. If the value
410 // really is dead at the PHI copy, there will be no successor blocks which
411 // have the value live-in.
413 // Okay, if we now know that the value is not live out of the block, we
414 // can add a kill marker in this block saying that it kills the incoming
417 // In our final twist, we have to decide which instruction kills the
418 // register. In most cases this is the copy, however, terminator
419 // instructions at the end of the block may also use the value. In this
420 // case, we should mark the last such terminator as being the killing
421 // block, not the copy.
422 MachineBasicBlock::iterator KillInst = opBlock.end();
423 MachineBasicBlock::iterator FirstTerm = opBlock.getFirstTerminator();
424 for (MachineBasicBlock::iterator Term = FirstTerm;
425 Term != opBlock.end(); ++Term) {
426 if (Term->readsRegister(SrcReg))
430 if (KillInst == opBlock.end()) {
431 // No terminator uses the register.
433 if (reusedIncoming || !IncomingReg) {
434 // We may have to rewind a bit if we didn't insert a copy this time.
435 KillInst = FirstTerm;
436 while (KillInst != opBlock.begin()) {
438 if (KillInst->isDebugValue())
440 if (KillInst->readsRegister(SrcReg))
444 // We just inserted this copy.
445 KillInst = std::prev(InsertPos);
448 assert(KillInst->readsRegister(SrcReg) && "Cannot find kill instruction");
450 // Finally, mark it killed.
451 LV->addVirtualRegisterKilled(SrcReg, KillInst);
453 // This vreg no longer lives all of the way through opBlock.
454 unsigned opBlockNum = opBlock.getNumber();
455 LV->getVarInfo(SrcReg).AliveBlocks.reset(opBlockNum);
460 LIS->InsertMachineInstrInMaps(NewSrcInstr);
461 LIS->addSegmentToEndOfBlock(IncomingReg, NewSrcInstr);
465 !VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)]) {
466 LiveInterval &SrcLI = LIS->getInterval(SrcReg);
468 bool isLiveOut = false;
469 for (MachineBasicBlock::succ_iterator SI = opBlock.succ_begin(),
470 SE = opBlock.succ_end(); SI != SE; ++SI) {
471 SlotIndex startIdx = LIS->getMBBStartIdx(*SI);
472 VNInfo *VNI = SrcLI.getVNInfoAt(startIdx);
474 // Definitions by other PHIs are not truly live-in for our purposes.
475 if (VNI && VNI->def != startIdx) {
482 MachineBasicBlock::iterator KillInst = opBlock.end();
483 MachineBasicBlock::iterator FirstTerm = opBlock.getFirstTerminator();
484 for (MachineBasicBlock::iterator Term = FirstTerm;
485 Term != opBlock.end(); ++Term) {
486 if (Term->readsRegister(SrcReg))
490 if (KillInst == opBlock.end()) {
491 // No terminator uses the register.
493 if (reusedIncoming || !IncomingReg) {
494 // We may have to rewind a bit if we didn't just insert a copy.
495 KillInst = FirstTerm;
496 while (KillInst != opBlock.begin()) {
498 if (KillInst->isDebugValue())
500 if (KillInst->readsRegister(SrcReg))
504 // We just inserted this copy.
505 KillInst = std::prev(InsertPos);
508 assert(KillInst->readsRegister(SrcReg) &&
509 "Cannot find kill instruction");
511 SlotIndex LastUseIndex = LIS->getInstructionIndex(KillInst);
512 SrcLI.removeSegment(LastUseIndex.getRegSlot(),
513 LIS->getMBBEndIdx(&opBlock));
519 // Really delete the PHI instruction now, if it is not in the LoweredPHIs map.
520 if (reusedIncoming || !IncomingReg) {
522 LIS->RemoveMachineInstrFromMaps(MPhi);
523 MF.DeleteMachineInstr(MPhi);
527 /// analyzePHINodes - Gather information about the PHI nodes in here. In
528 /// particular, we want to map the number of uses of a virtual register which is
529 /// used in a PHI node. We map that to the BB the vreg is coming from. This is
530 /// used later to determine when the vreg is killed in the BB.
532 void PHIElimination::analyzePHINodes(const MachineFunction& MF) {
533 for (const auto &MBB : MF)
534 for (const auto &BBI : MBB) {
537 for (unsigned i = 1, e = BBI.getNumOperands(); i != e; i += 2)
538 ++VRegPHIUseCount[BBVRegPair(BBI.getOperand(i+1).getMBB()->getNumber(),
539 BBI.getOperand(i).getReg())];
543 bool PHIElimination::SplitPHIEdges(MachineFunction &MF,
544 MachineBasicBlock &MBB,
545 MachineLoopInfo *MLI) {
546 if (MBB.empty() || !MBB.front().isPHI() || MBB.isLandingPad())
547 return false; // Quick exit for basic blocks without PHIs.
549 const MachineLoop *CurLoop = MLI ? MLI->getLoopFor(&MBB) : nullptr;
550 bool IsLoopHeader = CurLoop && &MBB == CurLoop->getHeader();
552 bool Changed = false;
553 for (MachineBasicBlock::iterator BBI = MBB.begin(), BBE = MBB.end();
554 BBI != BBE && BBI->isPHI(); ++BBI) {
555 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
556 unsigned Reg = BBI->getOperand(i).getReg();
557 MachineBasicBlock *PreMBB = BBI->getOperand(i+1).getMBB();
558 // Is there a critical edge from PreMBB to MBB?
559 if (PreMBB->succ_size() == 1)
562 // Avoid splitting backedges of loops. It would introduce small
563 // out-of-line blocks into the loop which is very bad for code placement.
564 if (PreMBB == &MBB && !SplitAllCriticalEdges)
566 const MachineLoop *PreLoop = MLI ? MLI->getLoopFor(PreMBB) : nullptr;
567 if (IsLoopHeader && PreLoop == CurLoop && !SplitAllCriticalEdges)
570 // LV doesn't consider a phi use live-out, so isLiveOut only returns true
571 // when the source register is live-out for some other reason than a phi
572 // use. That means the copy we will insert in PreMBB won't be a kill, and
573 // there is a risk it may not be coalesced away.
575 // If the copy would be a kill, there is no need to split the edge.
576 if (!isLiveOutPastPHIs(Reg, PreMBB) && !SplitAllCriticalEdges)
579 DEBUG(dbgs() << PrintReg(Reg) << " live-out before critical edge BB#"
580 << PreMBB->getNumber() << " -> BB#" << MBB.getNumber()
583 // If Reg is not live-in to MBB, it means it must be live-in to some
584 // other PreMBB successor, and we can avoid the interference by splitting
587 // If Reg *is* live-in to MBB, the interference is inevitable and a copy
588 // is likely to be left after coalescing. If we are looking at a loop
589 // exiting edge, split it so we won't insert code in the loop, otherwise
591 bool ShouldSplit = !isLiveIn(Reg, &MBB) || SplitAllCriticalEdges;
593 // Check for a loop exiting edge.
594 if (!ShouldSplit && CurLoop != PreLoop) {
596 dbgs() << "Split wouldn't help, maybe avoid loop copies?\n";
597 if (PreLoop) dbgs() << "PreLoop: " << *PreLoop;
598 if (CurLoop) dbgs() << "CurLoop: " << *CurLoop;
600 // This edge could be entering a loop, exiting a loop, or it could be
601 // both: Jumping directly form one loop to the header of a sibling
603 // Split unless this edge is entering CurLoop from an outer loop.
604 ShouldSplit = PreLoop && !PreLoop->contains(CurLoop);
608 if (!PreMBB->SplitCriticalEdge(&MBB, this)) {
609 DEBUG(dbgs() << "Failed to split critical edge.\n");
613 ++NumCriticalEdgesSplit;
619 bool PHIElimination::isLiveIn(unsigned Reg, MachineBasicBlock *MBB) {
620 assert((LV || LIS) &&
621 "isLiveIn() requires either LiveVariables or LiveIntervals");
623 return LIS->isLiveInToMBB(LIS->getInterval(Reg), MBB);
625 return LV->isLiveIn(Reg, *MBB);
628 bool PHIElimination::isLiveOutPastPHIs(unsigned Reg, MachineBasicBlock *MBB) {
629 assert((LV || LIS) &&
630 "isLiveOutPastPHIs() requires either LiveVariables or LiveIntervals");
631 // LiveVariables considers uses in PHIs to be in the predecessor basic block,
632 // so that a register used only in a PHI is not live out of the block. In
633 // contrast, LiveIntervals considers uses in PHIs to be on the edge rather than
634 // in the predecessor basic block, so that a register used only in a PHI is live
637 const LiveInterval &LI = LIS->getInterval(Reg);
638 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
639 SE = MBB->succ_end(); SI != SE; ++SI) {
640 if (LI.liveAt(LIS->getMBBStartIdx(*SI)))
645 return LV->isLiveOut(Reg, *MBB);