1 //===-- PhiElimination.cpp - Eliminate PHI nodes by inserting copies ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass eliminates machine instruction PHI nodes by inserting copy
11 // instructions. This destroys SSA information, but is the desired input for
12 // some register allocators.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "phielim"
17 #include "llvm/CodeGen/Passes.h"
18 #include "PHIEliminationUtils.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/SmallPtrSet.h"
21 #include "llvm/ADT/Statistic.h"
22 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
23 #include "llvm/CodeGen/LiveVariables.h"
24 #include "llvm/CodeGen/MachineDominators.h"
25 #include "llvm/CodeGen/MachineInstr.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineLoopInfo.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Compiler.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Target/TargetInstrInfo.h"
34 #include "llvm/Target/TargetMachine.h"
39 DisableEdgeSplitting("disable-phi-elim-edge-splitting", cl::init(false),
40 cl::Hidden, cl::desc("Disable critical edge splitting "
41 "during PHI elimination"));
44 class PHIElimination : public MachineFunctionPass {
45 MachineRegisterInfo *MRI; // Machine register information
50 static char ID; // Pass identification, replacement for typeid
51 PHIElimination() : MachineFunctionPass(ID) {
52 initializePHIEliminationPass(*PassRegistry::getPassRegistry());
55 virtual bool runOnMachineFunction(MachineFunction &Fn);
56 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
59 /// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions
60 /// in predecessor basic blocks.
62 bool EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB);
63 void LowerPHINode(MachineBasicBlock &MBB,
64 MachineBasicBlock::iterator AfterPHIsIt);
66 /// analyzePHINodes - Gather information about the PHI nodes in
67 /// here. In particular, we want to map the number of uses of a virtual
68 /// register which is used in a PHI node. We map that to the BB the
69 /// vreg is coming from. This is used later to determine when the vreg
70 /// is killed in the BB.
72 void analyzePHINodes(const MachineFunction& Fn);
74 /// Split critical edges where necessary for good coalescer performance.
75 bool SplitPHIEdges(MachineFunction &MF, MachineBasicBlock &MBB,
76 MachineLoopInfo *MLI);
78 typedef std::pair<unsigned, unsigned> BBVRegPair;
79 typedef DenseMap<BBVRegPair, unsigned> VRegPHIUse;
81 VRegPHIUse VRegPHIUseCount;
83 // Defs of PHI sources which are implicit_def.
84 SmallPtrSet<MachineInstr*, 4> ImpDefs;
86 // Map reusable lowered PHI node -> incoming join register.
87 typedef DenseMap<MachineInstr*, unsigned,
88 MachineInstrExpressionTrait> LoweredPHIMap;
89 LoweredPHIMap LoweredPHIs;
93 STATISTIC(NumLowered, "Number of phis lowered");
94 STATISTIC(NumCriticalEdgesSplit, "Number of critical edges split");
95 STATISTIC(NumReused, "Number of reused lowered phis");
97 char PHIElimination::ID = 0;
98 char& llvm::PHIEliminationID = PHIElimination::ID;
100 INITIALIZE_PASS_BEGIN(PHIElimination, "phi-node-elimination",
101 "Eliminate PHI nodes for register allocation",
103 INITIALIZE_PASS_DEPENDENCY(LiveVariables)
104 INITIALIZE_PASS_END(PHIElimination, "phi-node-elimination",
105 "Eliminate PHI nodes for register allocation", false, false)
107 void PHIElimination::getAnalysisUsage(AnalysisUsage &AU) const {
108 AU.addPreserved<LiveVariables>();
109 AU.addPreserved<LiveIntervals>();
110 AU.addPreserved<MachineDominatorTree>();
111 AU.addPreserved<MachineLoopInfo>();
112 MachineFunctionPass::getAnalysisUsage(AU);
115 bool PHIElimination::runOnMachineFunction(MachineFunction &MF) {
116 MRI = &MF.getRegInfo();
117 LV = getAnalysisIfAvailable<LiveVariables>();
118 LIS = getAnalysisIfAvailable<LiveIntervals>();
120 bool Changed = false;
122 // This pass takes the function out of SSA form.
125 // Split critical edges to help the coalescer. This does not yet support
126 // updating LiveIntervals, so we disable it.
127 if (!DisableEdgeSplitting && LV && !LIS) {
128 MachineLoopInfo *MLI = getAnalysisIfAvailable<MachineLoopInfo>();
129 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
130 Changed |= SplitPHIEdges(MF, *I, MLI);
133 // Populate VRegPHIUseCount
136 // Eliminate PHI instructions by inserting copies into predecessor blocks.
137 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
138 Changed |= EliminatePHINodes(MF, *I);
140 // Remove dead IMPLICIT_DEF instructions.
141 for (SmallPtrSet<MachineInstr*, 4>::iterator I = ImpDefs.begin(),
142 E = ImpDefs.end(); I != E; ++I) {
143 MachineInstr *DefMI = *I;
144 unsigned DefReg = DefMI->getOperand(0).getReg();
145 if (MRI->use_nodbg_empty(DefReg)) {
147 LIS->RemoveMachineInstrFromMaps(DefMI);
148 DefMI->eraseFromParent();
152 // Clean up the lowered PHI instructions.
153 for (LoweredPHIMap::iterator I = LoweredPHIs.begin(), E = LoweredPHIs.end();
156 LIS->RemoveMachineInstrFromMaps(I->first);
157 MF.DeleteMachineInstr(I->first);
162 VRegPHIUseCount.clear();
165 MF.verify(this, "After PHI elimination");
170 /// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions in
171 /// predecessor basic blocks.
173 bool PHIElimination::EliminatePHINodes(MachineFunction &MF,
174 MachineBasicBlock &MBB) {
175 if (MBB.empty() || !MBB.front().isPHI())
176 return false; // Quick exit for basic blocks without PHIs.
178 // Get an iterator to the first instruction after the last PHI node (this may
179 // also be the end of the basic block).
180 MachineBasicBlock::iterator AfterPHIsIt = MBB.SkipPHIsAndLabels(MBB.begin());
182 while (MBB.front().isPHI())
183 LowerPHINode(MBB, AfterPHIsIt);
188 /// isImplicitlyDefined - Return true if all defs of VirtReg are implicit-defs.
189 /// This includes registers with no defs.
190 static bool isImplicitlyDefined(unsigned VirtReg,
191 const MachineRegisterInfo *MRI) {
192 for (MachineRegisterInfo::def_iterator DI = MRI->def_begin(VirtReg),
193 DE = MRI->def_end(); DI != DE; ++DI)
194 if (!DI->isImplicitDef())
199 /// isSourceDefinedByImplicitDef - Return true if all sources of the phi node
200 /// are implicit_def's.
201 static bool isSourceDefinedByImplicitDef(const MachineInstr *MPhi,
202 const MachineRegisterInfo *MRI) {
203 for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2)
204 if (!isImplicitlyDefined(MPhi->getOperand(i).getReg(), MRI))
210 /// LowerPHINode - Lower the PHI node at the top of the specified block,
212 void PHIElimination::LowerPHINode(MachineBasicBlock &MBB,
213 MachineBasicBlock::iterator AfterPHIsIt) {
215 // Unlink the PHI node from the basic block, but don't delete the PHI yet.
216 MachineInstr *MPhi = MBB.remove(MBB.begin());
218 unsigned NumSrcs = (MPhi->getNumOperands() - 1) / 2;
219 unsigned DestReg = MPhi->getOperand(0).getReg();
220 assert(MPhi->getOperand(0).getSubReg() == 0 && "Can't handle sub-reg PHIs");
221 bool isDead = MPhi->getOperand(0).isDead();
223 // Create a new register for the incoming PHI arguments.
224 MachineFunction &MF = *MBB.getParent();
225 unsigned IncomingReg = 0;
226 bool reusedIncoming = false; // Is IncomingReg reused from an earlier PHI?
228 // Insert a register to register copy at the top of the current block (but
229 // after any remaining phi nodes) which copies the new incoming register
230 // into the phi node destination.
231 const TargetInstrInfo *TII = MF.getTarget().getInstrInfo();
232 if (isSourceDefinedByImplicitDef(MPhi, MRI))
233 // If all sources of a PHI node are implicit_def, just emit an
234 // implicit_def instead of a copy.
235 BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(),
236 TII->get(TargetOpcode::IMPLICIT_DEF), DestReg);
238 // Can we reuse an earlier PHI node? This only happens for critical edges,
239 // typically those created by tail duplication.
240 unsigned &entry = LoweredPHIs[MPhi];
242 // An identical PHI node was already lowered. Reuse the incoming register.
244 reusedIncoming = true;
246 DEBUG(dbgs() << "Reusing " << PrintReg(IncomingReg) << " for " << *MPhi);
248 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg);
249 entry = IncomingReg = MF.getRegInfo().createVirtualRegister(RC);
251 BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(),
252 TII->get(TargetOpcode::COPY), DestReg)
253 .addReg(IncomingReg);
256 // Update live variable information if there is any.
258 MachineInstr *PHICopy = prior(AfterPHIsIt);
261 LiveVariables::VarInfo &VI = LV->getVarInfo(IncomingReg);
263 // Increment use count of the newly created virtual register.
264 LV->setPHIJoin(IncomingReg);
266 // When we are reusing the incoming register, it may already have been
267 // killed in this block. The old kill will also have been inserted at
268 // AfterPHIsIt, so it appears before the current PHICopy.
270 if (MachineInstr *OldKill = VI.findKill(&MBB)) {
271 DEBUG(dbgs() << "Remove old kill from " << *OldKill);
272 LV->removeVirtualRegisterKilled(IncomingReg, OldKill);
276 // Add information to LiveVariables to know that the incoming value is
277 // killed. Note that because the value is defined in several places (once
278 // each for each incoming block), the "def" block and instruction fields
279 // for the VarInfo is not filled in.
280 LV->addVirtualRegisterKilled(IncomingReg, PHICopy);
283 // Since we are going to be deleting the PHI node, if it is the last use of
284 // any registers, or if the value itself is dead, we need to move this
285 // information over to the new copy we just inserted.
286 LV->removeVirtualRegistersKilled(MPhi);
288 // If the result is dead, update LV.
290 LV->addVirtualRegisterDead(DestReg, PHICopy);
291 LV->removeVirtualRegisterDead(DestReg, MPhi);
295 // Update LiveIntervals for the new copy or implicit def.
297 MachineInstr *NewInstr = prior(AfterPHIsIt);
298 LIS->InsertMachineInstrInMaps(NewInstr);
300 SlotIndex MBBStartIndex = LIS->getMBBStartIdx(&MBB);
301 SlotIndex DestCopyIndex = LIS->getInstructionIndex(NewInstr);
303 // Add the region from the beginning of MBB to the copy instruction to
304 // IncomingReg's live interval.
305 LiveInterval &IncomingLI = LIS->getOrCreateInterval(IncomingReg);
306 VNInfo *IncomingVNI = IncomingLI.getVNInfoAt(MBBStartIndex);
308 IncomingVNI = IncomingLI.getNextValue(MBBStartIndex,
309 LIS->getVNInfoAllocator());
310 IncomingLI.addRange(LiveRange(MBBStartIndex,
311 DestCopyIndex.getRegSlot(),
315 LiveInterval &DestLI = LIS->getOrCreateInterval(DestReg);
316 if (NewInstr->getOperand(0).isDead()) {
317 // A dead PHI's live range begins and ends at the start of the MBB, but
318 // the lowered copy, which will still be dead, needs to begin and end at
319 // the copy instruction.
320 VNInfo *OrigDestVNI = DestLI.getVNInfoAt(MBBStartIndex);
321 assert(OrigDestVNI && "PHI destination should be live at block entry.");
322 DestLI.removeRange(MBBStartIndex, MBBStartIndex.getDeadSlot());
323 DestLI.createDeadDef(DestCopyIndex.getRegSlot(),
324 LIS->getVNInfoAllocator());
325 DestLI.removeValNo(OrigDestVNI);
327 // Otherwise, remove the region from the beginning of MBB to the copy
328 // instruction from DestReg's live interval.
329 DestLI.removeRange(MBBStartIndex, DestCopyIndex.getRegSlot());
330 VNInfo *DestVNI = DestLI.getVNInfoAt(DestCopyIndex.getRegSlot());
331 assert(DestVNI && "PHI destination should be live at its definition.");
332 DestVNI->def = DestCopyIndex.getRegSlot();
336 // Adjust the VRegPHIUseCount map to account for the removal of this PHI node.
337 for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2)
338 --VRegPHIUseCount[BBVRegPair(MPhi->getOperand(i+1).getMBB()->getNumber(),
339 MPhi->getOperand(i).getReg())];
341 // Now loop over all of the incoming arguments, changing them to copy into the
342 // IncomingReg register in the corresponding predecessor basic block.
343 SmallPtrSet<MachineBasicBlock*, 8> MBBsInsertedInto;
344 for (int i = NumSrcs - 1; i >= 0; --i) {
345 unsigned SrcReg = MPhi->getOperand(i*2+1).getReg();
346 unsigned SrcSubReg = MPhi->getOperand(i*2+1).getSubReg();
347 bool SrcUndef = MPhi->getOperand(i*2+1).isUndef() ||
348 isImplicitlyDefined(SrcReg, MRI);
349 assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
350 "Machine PHI Operands must all be virtual registers!");
352 // Get the MachineBasicBlock equivalent of the BasicBlock that is the source
354 MachineBasicBlock &opBlock = *MPhi->getOperand(i*2+2).getMBB();
356 // Check to make sure we haven't already emitted the copy for this block.
357 // This can happen because PHI nodes may have multiple entries for the same
359 if (!MBBsInsertedInto.insert(&opBlock))
360 continue; // If the copy has already been emitted, we're done.
362 // Find a safe location to insert the copy, this may be the first terminator
363 // in the block (or end()).
364 MachineBasicBlock::iterator InsertPos =
365 findPHICopyInsertPoint(&opBlock, &MBB, SrcReg);
368 MachineInstr *NewSrcInstr = 0;
369 if (!reusedIncoming && IncomingReg) {
371 // The source register is undefined, so there is no need for a real
372 // COPY, but we still need to ensure joint dominance by defs.
373 // Insert an IMPLICIT_DEF instruction.
374 NewSrcInstr = BuildMI(opBlock, InsertPos, MPhi->getDebugLoc(),
375 TII->get(TargetOpcode::IMPLICIT_DEF),
378 // Clean up the old implicit-def, if there even was one.
379 if (MachineInstr *DefMI = MRI->getVRegDef(SrcReg))
380 if (DefMI->isImplicitDef())
381 ImpDefs.insert(DefMI);
383 NewSrcInstr = BuildMI(opBlock, InsertPos, MPhi->getDebugLoc(),
384 TII->get(TargetOpcode::COPY), IncomingReg)
385 .addReg(SrcReg, 0, SrcSubReg);
389 // We only need to update the LiveVariables kill of SrcReg if this was the
390 // last PHI use of SrcReg to be lowered on this CFG edge and it is not live
391 // out of the predecessor. We can also ignore undef sources.
392 if (LV && !SrcUndef &&
393 !VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)] &&
394 !LV->isLiveOut(SrcReg, opBlock)) {
395 // We want to be able to insert a kill of the register if this PHI (aka,
396 // the copy we just inserted) is the last use of the source value. Live
397 // variable analysis conservatively handles this by saying that the value
398 // is live until the end of the block the PHI entry lives in. If the value
399 // really is dead at the PHI copy, there will be no successor blocks which
400 // have the value live-in.
402 // Okay, if we now know that the value is not live out of the block, we
403 // can add a kill marker in this block saying that it kills the incoming
406 // In our final twist, we have to decide which instruction kills the
407 // register. In most cases this is the copy, however, terminator
408 // instructions at the end of the block may also use the value. In this
409 // case, we should mark the last such terminator as being the killing
410 // block, not the copy.
411 MachineBasicBlock::iterator KillInst = opBlock.end();
412 MachineBasicBlock::iterator FirstTerm = opBlock.getFirstTerminator();
413 for (MachineBasicBlock::iterator Term = FirstTerm;
414 Term != opBlock.end(); ++Term) {
415 if (Term->readsRegister(SrcReg))
419 if (KillInst == opBlock.end()) {
420 // No terminator uses the register.
422 if (reusedIncoming || !IncomingReg) {
423 // We may have to rewind a bit if we didn't insert a copy this time.
424 KillInst = FirstTerm;
425 while (KillInst != opBlock.begin()) {
427 if (KillInst->isDebugValue())
429 if (KillInst->readsRegister(SrcReg))
433 // We just inserted this copy.
434 KillInst = prior(InsertPos);
437 assert(KillInst->readsRegister(SrcReg) && "Cannot find kill instruction");
439 // Finally, mark it killed.
440 LV->addVirtualRegisterKilled(SrcReg, KillInst);
442 // This vreg no longer lives all of the way through opBlock.
443 unsigned opBlockNum = opBlock.getNumber();
444 LV->getVarInfo(SrcReg).AliveBlocks.reset(opBlockNum);
449 LIS->InsertMachineInstrInMaps(NewSrcInstr);
450 LIS->addLiveRangeToEndOfBlock(IncomingReg, NewSrcInstr);
454 !VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)]) {
455 LiveInterval &SrcLI = LIS->getInterval(SrcReg);
457 bool isLiveOut = false;
458 for (MachineBasicBlock::succ_iterator SI = opBlock.succ_begin(),
459 SE = opBlock.succ_end(); SI != SE; ++SI) {
460 if (SrcLI.liveAt(LIS->getMBBStartIdx(*SI))) {
467 MachineBasicBlock::iterator KillInst = opBlock.end();
468 MachineBasicBlock::iterator FirstTerm = opBlock.getFirstTerminator();
469 for (MachineBasicBlock::iterator Term = FirstTerm;
470 Term != opBlock.end(); ++Term) {
471 if (Term->readsRegister(SrcReg))
475 if (KillInst == opBlock.end()) {
476 // No terminator uses the register.
478 if (reusedIncoming || !IncomingReg) {
479 // We may have to rewind a bit if we didn't just insert a copy.
480 KillInst = FirstTerm;
481 while (KillInst != opBlock.begin()) {
483 if (KillInst->isDebugValue())
485 if (KillInst->readsRegister(SrcReg))
489 // We just inserted this copy.
490 KillInst = prior(InsertPos);
493 assert(KillInst->readsRegister(SrcReg) &&
494 "Cannot find kill instruction");
496 SlotIndex LastUseIndex = LIS->getInstructionIndex(KillInst);
497 SrcLI.removeRange(LastUseIndex.getRegSlot(),
498 LIS->getMBBEndIdx(&opBlock));
504 // Really delete the PHI instruction now, if it is not in the LoweredPHIs map.
505 if (reusedIncoming || !IncomingReg) {
507 LIS->RemoveMachineInstrFromMaps(MPhi);
508 MF.DeleteMachineInstr(MPhi);
512 /// analyzePHINodes - Gather information about the PHI nodes in here. In
513 /// particular, we want to map the number of uses of a virtual register which is
514 /// used in a PHI node. We map that to the BB the vreg is coming from. This is
515 /// used later to determine when the vreg is killed in the BB.
517 void PHIElimination::analyzePHINodes(const MachineFunction& MF) {
518 for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
520 for (MachineBasicBlock::const_iterator BBI = I->begin(), BBE = I->end();
521 BBI != BBE && BBI->isPHI(); ++BBI)
522 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
523 ++VRegPHIUseCount[BBVRegPair(BBI->getOperand(i+1).getMBB()->getNumber(),
524 BBI->getOperand(i).getReg())];
527 bool PHIElimination::SplitPHIEdges(MachineFunction &MF,
528 MachineBasicBlock &MBB,
529 MachineLoopInfo *MLI) {
530 if (MBB.empty() || !MBB.front().isPHI() || MBB.isLandingPad())
531 return false; // Quick exit for basic blocks without PHIs.
533 const MachineLoop *CurLoop = MLI ? MLI->getLoopFor(&MBB) : 0;
534 bool IsLoopHeader = CurLoop && &MBB == CurLoop->getHeader();
536 bool Changed = false;
537 for (MachineBasicBlock::iterator BBI = MBB.begin(), BBE = MBB.end();
538 BBI != BBE && BBI->isPHI(); ++BBI) {
539 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
540 unsigned Reg = BBI->getOperand(i).getReg();
541 MachineBasicBlock *PreMBB = BBI->getOperand(i+1).getMBB();
542 // Is there a critical edge from PreMBB to MBB?
543 if (PreMBB->succ_size() == 1)
546 // Avoid splitting backedges of loops. It would introduce small
547 // out-of-line blocks into the loop which is very bad for code placement.
550 const MachineLoop *PreLoop = MLI ? MLI->getLoopFor(PreMBB) : 0;
551 if (IsLoopHeader && PreLoop == CurLoop)
554 // LV doesn't consider a phi use live-out, so isLiveOut only returns true
555 // when the source register is live-out for some other reason than a phi
556 // use. That means the copy we will insert in PreMBB won't be a kill, and
557 // there is a risk it may not be coalesced away.
559 // If the copy would be a kill, there is no need to split the edge.
560 if (!LV->isLiveOut(Reg, *PreMBB))
563 DEBUG(dbgs() << PrintReg(Reg) << " live-out before critical edge BB#"
564 << PreMBB->getNumber() << " -> BB#" << MBB.getNumber()
567 // If Reg is not live-in to MBB, it means it must be live-in to some
568 // other PreMBB successor, and we can avoid the interference by splitting
571 // If Reg *is* live-in to MBB, the interference is inevitable and a copy
572 // is likely to be left after coalescing. If we are looking at a loop
573 // exiting edge, split it so we won't insert code in the loop, otherwise
575 bool ShouldSplit = !LV->isLiveIn(Reg, MBB);
577 // Check for a loop exiting edge.
578 if (!ShouldSplit && CurLoop != PreLoop) {
580 dbgs() << "Split wouldn't help, maybe avoid loop copies?\n";
581 if (PreLoop) dbgs() << "PreLoop: " << *PreLoop;
582 if (CurLoop) dbgs() << "CurLoop: " << *CurLoop;
584 // This edge could be entering a loop, exiting a loop, or it could be
585 // both: Jumping directly form one loop to the header of a sibling
587 // Split unless this edge is entering CurLoop from an outer loop.
588 ShouldSplit = PreLoop && !PreLoop->contains(CurLoop);
592 if (!PreMBB->SplitCriticalEdge(&MBB, this)) {
593 DEBUG(dbgs() << "Failed to split ciritcal edge.\n");
597 ++NumCriticalEdgesSplit;