1 //===-- MachineVerifier.cpp - Machine Code Verifier -------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Pass to verify generated machine code. The following is checked:
12 // Operand counts: All explicit operands must be present.
14 // Register classes: All physical and virtual register operands must be
15 // compatible with the register class required by the instruction descriptor.
17 // Register live intervals: Registers must be defined only once, and must be
18 // defined before use.
20 // The machine code verifier is enabled from LLVMTargetMachine.cpp with the
21 // command-line option -verify-machineinstrs, or by defining the environment
22 // variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive
23 // the verifier errors.
24 //===----------------------------------------------------------------------===//
26 #include "llvm/ADT/DenseSet.h"
27 #include "llvm/ADT/SetOperations.h"
28 #include "llvm/ADT/SmallVector.h"
29 #include "llvm/Function.h"
30 #include "llvm/CodeGen/LiveVariables.h"
31 #include "llvm/CodeGen/MachineFunctionPass.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/Passes.h"
34 #include "llvm/Target/TargetMachine.h"
35 #include "llvm/Target/TargetRegisterInfo.h"
36 #include "llvm/Target/TargetInstrInfo.h"
37 #include "llvm/Support/Compiler.h"
38 #include "llvm/Support/Debug.h"
39 #include "llvm/Support/ErrorHandling.h"
40 #include "llvm/Support/raw_ostream.h"
46 struct VISIBILITY_HIDDEN MachineVerifier : public MachineFunctionPass {
47 static char ID; // Pass ID, replacement for typeid
49 MachineVerifier(bool allowDoubleDefs = false) :
50 MachineFunctionPass(&ID),
51 allowVirtDoubleDefs(allowDoubleDefs),
52 allowPhysDoubleDefs(allowDoubleDefs),
53 OutFileName(getenv("LLVM_VERIFY_MACHINEINSTRS"))
56 void getAnalysisUsage(AnalysisUsage &AU) const {
60 bool runOnMachineFunction(MachineFunction &MF);
62 const bool allowVirtDoubleDefs;
63 const bool allowPhysDoubleDefs;
65 const char *const OutFileName;
67 const MachineFunction *MF;
68 const TargetMachine *TM;
69 const TargetRegisterInfo *TRI;
70 const MachineRegisterInfo *MRI;
74 typedef SmallVector<unsigned, 16> RegVector;
75 typedef DenseSet<unsigned> RegSet;
76 typedef DenseMap<unsigned, const MachineInstr*> RegMap;
78 BitVector regsReserved;
80 RegVector regsDefined, regsImpDefined, regsDead, regsKilled;
82 // Add Reg and any sub-registers to RV
83 void addRegWithSubRegs(RegVector &RV, unsigned Reg) {
85 if (TargetRegisterInfo::isPhysicalRegister(Reg))
86 for (const unsigned *R = TRI->getSubRegisters(Reg); *R; R++)
90 // Does RS contain any super-registers of Reg?
91 bool anySuperRegisters(const RegSet &RS, unsigned Reg) {
92 for (const unsigned *R = TRI->getSuperRegisters(Reg); *R; R++)
99 // Is this MBB reachable from the MF entry point?
102 // Vregs that must be live in because they are used without being
103 // defined. Map value is the user.
106 // Vregs that must be dead in because they are defined without being
107 // killed first. Map value is the defining instruction.
110 // Regs killed in MBB. They may be defined again, and will then be in both
111 // regsKilled and regsLiveOut.
114 // Regs defined in MBB and live out. Note that vregs passing through may
115 // be live out without being mentioned here.
118 // Vregs that pass through MBB untouched. This set is disjoint from
119 // regsKilled and regsLiveOut.
122 BBInfo() : reachable(false) {}
124 // Add register to vregsPassed if it belongs there. Return true if
126 bool addPassed(unsigned Reg) {
127 if (!TargetRegisterInfo::isVirtualRegister(Reg))
129 if (regsKilled.count(Reg) || regsLiveOut.count(Reg))
131 return vregsPassed.insert(Reg).second;
134 // Same for a full set.
135 bool addPassed(const RegSet &RS) {
136 bool changed = false;
137 for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
143 // Live-out registers are either in regsLiveOut or vregsPassed.
144 bool isLiveOut(unsigned Reg) const {
145 return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
149 // Extra register info per MBB.
150 DenseMap<const MachineBasicBlock*, BBInfo> MBBInfoMap;
152 bool isReserved(unsigned Reg) {
153 return Reg < regsReserved.size() && regsReserved[Reg];
156 void visitMachineFunctionBefore();
157 void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);
158 void visitMachineInstrBefore(const MachineInstr *MI);
159 void visitMachineOperand(const MachineOperand *MO, unsigned MONum);
160 void visitMachineInstrAfter(const MachineInstr *MI);
161 void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB);
162 void visitMachineFunctionAfter();
164 void report(const char *msg, const MachineFunction *MF);
165 void report(const char *msg, const MachineBasicBlock *MBB);
166 void report(const char *msg, const MachineInstr *MI);
167 void report(const char *msg, const MachineOperand *MO, unsigned MONum);
169 void markReachable(const MachineBasicBlock *MBB);
170 void calcMaxRegsPassed();
171 void calcMinRegsPassed();
172 void checkPHIOps(const MachineBasicBlock *MBB);
176 char MachineVerifier::ID = 0;
177 static RegisterPass<MachineVerifier>
178 MachineVer("machineverifier", "Verify generated machine code");
179 static const PassInfo *const MachineVerifyID = &MachineVer;
182 llvm::createMachineVerifierPass(bool allowPhysDoubleDefs)
184 return new MachineVerifier(allowPhysDoubleDefs);
188 MachineVerifier::runOnMachineFunction(MachineFunction &MF)
190 std::ofstream OutFile;
192 OutFile.open(OutFileName, std::ios::out | std::ios::app);
201 TM = &MF.getTarget();
202 TRI = TM->getRegisterInfo();
203 MRI = &MF.getRegInfo();
205 visitMachineFunctionBefore();
206 for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end();
208 visitMachineBasicBlockBefore(MFI);
209 for (MachineBasicBlock::const_iterator MBBI = MFI->begin(),
210 MBBE = MFI->end(); MBBI != MBBE; ++MBBI) {
211 visitMachineInstrBefore(MBBI);
212 for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I)
213 visitMachineOperand(&MBBI->getOperand(I), I);
214 visitMachineInstrAfter(MBBI);
216 visitMachineBasicBlockAfter(MFI);
218 visitMachineFunctionAfter();
222 else if (foundErrors) {
224 raw_string_ostream Msg(msg);
225 Msg << "Found " << foundErrors << " machine code errors.";
226 llvm_report_error(Msg.str());
229 return false; // no changes
233 MachineVerifier::report(const char *msg, const MachineFunction *MF)
239 *OS << "*** Bad machine code: " << msg << " ***\n"
240 << "- function: " << MF->getFunction()->getNameStr() << "\n";
244 MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB)
247 report(msg, MBB->getParent());
248 *OS << "- basic block: " << MBB->getBasicBlock()->getNameStr()
250 << " (#" << MBB->getNumber() << ")\n";
254 MachineVerifier::report(const char *msg, const MachineInstr *MI)
257 report(msg, MI->getParent());
258 *OS << "- instruction: ";
263 MachineVerifier::report(const char *msg,
264 const MachineOperand *MO, unsigned MONum)
267 report(msg, MO->getParent());
268 *OS << "- operand " << MONum << ": ";
274 MachineVerifier::markReachable(const MachineBasicBlock *MBB)
276 BBInfo &MInfo = MBBInfoMap[MBB];
277 if (!MInfo.reachable) {
278 MInfo.reachable = true;
279 for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
280 SuE = MBB->succ_end(); SuI != SuE; ++SuI)
286 MachineVerifier::visitMachineFunctionBefore()
288 regsReserved = TRI->getReservedRegs(*MF);
289 markReachable(&MF->front());
293 MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB)
296 for (MachineBasicBlock::const_livein_iterator I = MBB->livein_begin(),
297 E = MBB->livein_end(); I != E; ++I) {
298 if (!TargetRegisterInfo::isPhysicalRegister(*I)) {
299 report("MBB live-in list contains non-physical register", MBB);
303 for (const unsigned *R = TRI->getSubRegisters(*I); *R; R++)
308 regsImpDefined.clear();
312 MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI)
314 const TargetInstrDesc &TI = MI->getDesc();
315 if (MI->getNumExplicitOperands() < TI.getNumOperands()) {
316 report("Too few operands", MI);
317 *OS << TI.getNumOperands() << " operands expected, but "
318 << MI->getNumExplicitOperands() << " given.\n";
320 if (!TI.isVariadic()) {
321 if (MI->getNumExplicitOperands() > TI.getNumOperands()) {
322 report("Too many operands", MI);
323 *OS << TI.getNumOperands() << " operands expected, but "
324 << MI->getNumExplicitOperands() << " given.\n";
330 MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum)
332 const MachineInstr *MI = MO->getParent();
333 const TargetInstrDesc &TI = MI->getDesc();
335 // The first TI.NumDefs operands must be explicit register defines
336 if (MONum < TI.getNumDefs()) {
338 report("Explicit definition must be a register", MO, MONum);
339 else if (!MO->isDef())
340 report("Explicit definition marked as use", MO, MONum);
341 else if (MO->isImplicit())
342 report("Explicit definition marked as implicit", MO, MONum);
345 switch (MO->getType()) {
346 case MachineOperand::MO_Register: {
347 const unsigned Reg = MO->getReg();
351 // Check Live Variables.
354 addRegWithSubRegs(regsKilled, Reg);
355 // Tied operands on two-address instuctions MUST NOT have a <kill> flag.
356 if (MI->isRegTiedToDefOperand(MONum))
357 report("Illegal kill flag on two-address instruction operand",
360 // TwoAddress instr modifying a reg is treated as kill+def.
362 if (MI->isRegTiedToDefOperand(MONum, &defIdx) &&
363 MI->getOperand(defIdx).getReg() == Reg)
364 addRegWithSubRegs(regsKilled, Reg);
366 // Explicit use of a dead register.
367 if (!MO->isImplicit() && !regsLive.count(Reg)) {
368 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
369 // Reserved registers may be used even when 'dead'.
370 if (!isReserved(Reg))
371 report("Using an undefined physical register", MO, MONum);
373 BBInfo &MInfo = MBBInfoMap[MI->getParent()];
374 // We don't know which virtual registers are live in, so only complain
375 // if vreg was killed in this MBB. Otherwise keep track of vregs that
376 // must be live in. PHI instructions are handled separately.
377 if (MInfo.regsKilled.count(Reg))
378 report("Using a killed virtual register", MO, MONum);
379 else if (MI->getOpcode() != TargetInstrInfo::PHI)
380 MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));
385 // TODO: verify that earlyclobber ops are not used.
386 if (MO->isImplicit())
387 addRegWithSubRegs(regsImpDefined, Reg);
389 addRegWithSubRegs(regsDefined, Reg);
392 addRegWithSubRegs(regsDead, Reg);
395 // Check register classes.
396 if (MONum < TI.getNumOperands() && !MO->isImplicit()) {
397 const TargetOperandInfo &TOI = TI.OpInfo[MONum];
398 unsigned SubIdx = MO->getSubReg();
400 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
403 unsigned s = TRI->getSubReg(Reg, SubIdx);
405 report("Invalid subregister index for physical register",
411 if (const TargetRegisterClass *DRC = TOI.getRegClass(TRI)) {
412 if (!DRC->contains(sr)) {
413 report("Illegal physical register for instruction", MO, MONum);
414 *OS << TRI->getName(sr) << " is not a "
415 << DRC->getName() << " register.\n";
420 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
422 if (RC->subregclasses_begin()+SubIdx >= RC->subregclasses_end()) {
423 report("Invalid subregister index for virtual register", MO, MONum);
426 RC = *(RC->subregclasses_begin()+SubIdx);
428 if (const TargetRegisterClass *DRC = TOI.getRegClass(TRI)) {
429 if (RC != DRC && !RC->hasSuperClass(DRC)) {
430 report("Illegal virtual register for instruction", MO, MONum);
431 *OS << "Expected a " << DRC->getName() << " register, but got a "
432 << RC->getName() << " register\n";
439 // Can PHI instrs refer to MBBs not in the CFG? X86 and ARM do.
440 // case MachineOperand::MO_MachineBasicBlock:
441 // if (MI->getOpcode() == TargetInstrInfo::PHI) {
442 // if (!MO->getMBB()->isSuccessor(MI->getParent()))
443 // report("PHI operand is not in the CFG", MO, MONum);
452 MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI)
454 BBInfo &MInfo = MBBInfoMap[MI->getParent()];
455 set_union(MInfo.regsKilled, regsKilled);
456 set_subtract(regsLive, regsKilled);
459 for (RegVector::const_iterator I = regsDefined.begin(),
460 E = regsDefined.end(); I != E; ++I) {
461 if (regsLive.count(*I)) {
462 if (TargetRegisterInfo::isPhysicalRegister(*I)) {
463 // We allow double defines to physical registers with live
465 if (!allowPhysDoubleDefs && !isReserved(*I) &&
466 !anySuperRegisters(regsLive, *I)) {
467 report("Redefining a live physical register", MI);
468 *OS << "Register " << TRI->getName(*I)
469 << " was defined but already live.\n";
472 if (!allowVirtDoubleDefs) {
473 report("Redefining a live virtual register", MI);
474 *OS << "Virtual register %reg" << *I
475 << " was defined but already live.\n";
478 } else if (TargetRegisterInfo::isVirtualRegister(*I) &&
479 !MInfo.regsKilled.count(*I)) {
480 // Virtual register defined without being killed first must be dead on
482 MInfo.vregsDeadIn.insert(std::make_pair(*I, MI));
486 set_union(regsLive, regsDefined); regsDefined.clear();
487 set_union(regsLive, regsImpDefined); regsImpDefined.clear();
488 set_subtract(regsLive, regsDead); regsDead.clear();
492 MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB)
494 MBBInfoMap[MBB].regsLiveOut = regsLive;
498 // Calculate the largest possible vregsPassed sets. These are the registers that
499 // can pass through an MBB live, but may not be live every time. It is assumed
500 // that all vregsPassed sets are empty before the call.
502 MachineVerifier::calcMaxRegsPassed()
504 // First push live-out regs to successors' vregsPassed. Remember the MBBs that
505 // have any vregsPassed.
506 DenseSet<const MachineBasicBlock*> todo;
507 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
509 const MachineBasicBlock &MBB(*MFI);
510 BBInfo &MInfo = MBBInfoMap[&MBB];
511 if (!MInfo.reachable)
513 for (MachineBasicBlock::const_succ_iterator SuI = MBB.succ_begin(),
514 SuE = MBB.succ_end(); SuI != SuE; ++SuI) {
515 BBInfo &SInfo = MBBInfoMap[*SuI];
516 if (SInfo.addPassed(MInfo.regsLiveOut))
521 // Iteratively push vregsPassed to successors. This will converge to the same
522 // final state regardless of DenseSet iteration order.
523 while (!todo.empty()) {
524 const MachineBasicBlock *MBB = *todo.begin();
526 BBInfo &MInfo = MBBInfoMap[MBB];
527 for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
528 SuE = MBB->succ_end(); SuI != SuE; ++SuI) {
531 BBInfo &SInfo = MBBInfoMap[*SuI];
532 if (SInfo.addPassed(MInfo.vregsPassed))
538 // Calculate the minimum vregsPassed set. These are the registers that always
539 // pass live through an MBB. The calculation assumes that calcMaxRegsPassed has
540 // been called earlier.
542 MachineVerifier::calcMinRegsPassed()
544 DenseSet<const MachineBasicBlock*> todo;
545 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
549 while (!todo.empty()) {
550 const MachineBasicBlock *MBB = *todo.begin();
552 BBInfo &MInfo = MBBInfoMap[MBB];
554 // Remove entries from vRegsPassed that are not live out from all
555 // reachable predecessors.
557 for (RegSet::iterator I = MInfo.vregsPassed.begin(),
558 E = MInfo.vregsPassed.end(); I != E; ++I) {
559 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
560 PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
561 BBInfo &PrInfo = MBBInfoMap[*PrI];
562 if (PrInfo.reachable && !PrInfo.isLiveOut(*I)) {
568 // If any regs removed, we need to recheck successors.
570 set_subtract(MInfo.vregsPassed, dead);
571 todo.insert(MBB->succ_begin(), MBB->succ_end());
576 // Check PHI instructions at the beginning of MBB. It is assumed that
577 // calcMinRegsPassed has been run so BBInfo::isLiveOut is valid.
579 MachineVerifier::checkPHIOps(const MachineBasicBlock *MBB)
581 for (MachineBasicBlock::const_iterator BBI = MBB->begin(), BBE = MBB->end();
582 BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI) {
583 DenseSet<const MachineBasicBlock*> seen;
585 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
586 unsigned Reg = BBI->getOperand(i).getReg();
587 const MachineBasicBlock *Pre = BBI->getOperand(i + 1).getMBB();
588 if (!Pre->isSuccessor(MBB))
591 BBInfo &PrInfo = MBBInfoMap[Pre];
592 if (PrInfo.reachable && !PrInfo.isLiveOut(Reg))
593 report("PHI operand is not live-out from predecessor",
594 &BBI->getOperand(i), i);
597 // Did we see all predecessors?
598 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
599 PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
600 if (!seen.count(*PrI)) {
601 report("Missing PHI operand", BBI);
602 *OS << "MBB #" << (*PrI)->getNumber()
603 << " is a predecessor according to the CFG.\n";
610 MachineVerifier::visitMachineFunctionAfter()
614 // With the maximal set of vregsPassed we can verify dead-in registers.
615 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
617 BBInfo &MInfo = MBBInfoMap[MFI];
619 // Skip unreachable MBBs.
620 if (!MInfo.reachable)
623 for (MachineBasicBlock::const_pred_iterator PrI = MFI->pred_begin(),
624 PrE = MFI->pred_end(); PrI != PrE; ++PrI) {
625 BBInfo &PrInfo = MBBInfoMap[*PrI];
626 if (!PrInfo.reachable)
629 // Verify physical live-ins. EH landing pads have magic live-ins so we
631 if (!MFI->isLandingPad()) {
632 for (MachineBasicBlock::const_livein_iterator I = MFI->livein_begin(),
633 E = MFI->livein_end(); I != E; ++I) {
634 if (TargetRegisterInfo::isPhysicalRegister(*I) &&
635 !isReserved (*I) && !PrInfo.isLiveOut(*I)) {
636 report("Live-in physical register is not live-out from predecessor",
638 *OS << "Register " << TRI->getName(*I)
639 << " is not live-out from MBB #" << (*PrI)->getNumber()
646 // Verify dead-in virtual registers.
647 if (!allowVirtDoubleDefs) {
648 for (RegMap::iterator I = MInfo.vregsDeadIn.begin(),
649 E = MInfo.vregsDeadIn.end(); I != E; ++I) {
650 // DeadIn register must be in neither regsLiveOut or vregsPassed of
652 if (PrInfo.isLiveOut(I->first)) {
653 report("Live-in virtual register redefined", I->second);
654 *OS << "Register %reg" << I->first
655 << " was live-out from predecessor MBB #"
656 << (*PrI)->getNumber() << ".\n";
665 // With the minimal set of vregsPassed we can verify live-in virtual
666 // registers, including PHI instructions.
667 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
669 BBInfo &MInfo = MBBInfoMap[MFI];
671 // Skip unreachable MBBs.
672 if (!MInfo.reachable)
677 for (MachineBasicBlock::const_pred_iterator PrI = MFI->pred_begin(),
678 PrE = MFI->pred_end(); PrI != PrE; ++PrI) {
679 BBInfo &PrInfo = MBBInfoMap[*PrI];
680 if (!PrInfo.reachable)
683 for (RegMap::iterator I = MInfo.vregsLiveIn.begin(),
684 E = MInfo.vregsLiveIn.end(); I != E; ++I) {
685 if (!PrInfo.isLiveOut(I->first)) {
686 report("Used virtual register is not live-in", I->second);
687 *OS << "Register %reg" << I->first
688 << " is not live-out from predecessor MBB #"
689 << (*PrI)->getNumber()