1 //===-- MachineVerifier.cpp - Machine Code Verifier -----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Pass to verify generated machine code. The following is checked:
12 // Operand counts: All explicit operands must be present.
14 // Register classes: All physical and virtual register operands must be
15 // compatible with the register class required by the instruction descriptor.
17 // Register live intervals: Registers must be defined only once, and must be
18 // defined before use.
20 // The machine code verifier is enabled from LLVMTargetMachine.cpp with the
21 // command-line option -verify-machineinstrs, or by defining the environment
22 // variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive
23 // the verifier errors.
24 //===----------------------------------------------------------------------===//
26 #include "llvm/CodeGen/Passes.h"
27 #include "llvm/ADT/DenseSet.h"
28 #include "llvm/ADT/DepthFirstIterator.h"
29 #include "llvm/ADT/SetOperations.h"
30 #include "llvm/ADT/SmallVector.h"
31 #include "llvm/Analysis/LibCallSemantics.h"
32 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
33 #include "llvm/CodeGen/LiveStackAnalysis.h"
34 #include "llvm/CodeGen/LiveVariables.h"
35 #include "llvm/CodeGen/MachineFrameInfo.h"
36 #include "llvm/CodeGen/MachineFunctionPass.h"
37 #include "llvm/CodeGen/MachineMemOperand.h"
38 #include "llvm/CodeGen/MachineRegisterInfo.h"
39 #include "llvm/IR/BasicBlock.h"
40 #include "llvm/IR/InlineAsm.h"
41 #include "llvm/IR/Instructions.h"
42 #include "llvm/MC/MCAsmInfo.h"
43 #include "llvm/Support/Debug.h"
44 #include "llvm/Support/ErrorHandling.h"
45 #include "llvm/Support/FileSystem.h"
46 #include "llvm/Support/raw_ostream.h"
47 #include "llvm/Target/TargetInstrInfo.h"
48 #include "llvm/Target/TargetMachine.h"
49 #include "llvm/Target/TargetRegisterInfo.h"
50 #include "llvm/Target/TargetSubtargetInfo.h"
54 struct MachineVerifier {
56 MachineVerifier(Pass *pass, const char *b) :
61 bool runOnMachineFunction(MachineFunction &MF);
65 const MachineFunction *MF;
66 const TargetMachine *TM;
67 const TargetInstrInfo *TII;
68 const TargetRegisterInfo *TRI;
69 const MachineRegisterInfo *MRI;
73 typedef SmallVector<unsigned, 16> RegVector;
74 typedef SmallVector<const uint32_t*, 4> RegMaskVector;
75 typedef DenseSet<unsigned> RegSet;
76 typedef DenseMap<unsigned, const MachineInstr*> RegMap;
77 typedef SmallPtrSet<const MachineBasicBlock*, 8> BlockSet;
79 const MachineInstr *FirstTerminator;
80 BlockSet FunctionBlocks;
82 BitVector regsReserved;
84 RegVector regsDefined, regsDead, regsKilled;
85 RegMaskVector regMasks;
86 RegSet regsLiveInButUnused;
90 // Add Reg and any sub-registers to RV
91 void addRegWithSubRegs(RegVector &RV, unsigned Reg) {
93 if (TargetRegisterInfo::isPhysicalRegister(Reg))
94 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
95 RV.push_back(*SubRegs);
99 // Is this MBB reachable from the MF entry point?
102 // Vregs that must be live in because they are used without being
103 // defined. Map value is the user.
106 // Regs killed in MBB. They may be defined again, and will then be in both
107 // regsKilled and regsLiveOut.
110 // Regs defined in MBB and live out. Note that vregs passing through may
111 // be live out without being mentioned here.
114 // Vregs that pass through MBB untouched. This set is disjoint from
115 // regsKilled and regsLiveOut.
118 // Vregs that must pass through MBB because they are needed by a successor
119 // block. This set is disjoint from regsLiveOut.
120 RegSet vregsRequired;
122 // Set versions of block's predecessor and successor lists.
123 BlockSet Preds, Succs;
125 BBInfo() : reachable(false) {}
127 // Add register to vregsPassed if it belongs there. Return true if
129 bool addPassed(unsigned Reg) {
130 if (!TargetRegisterInfo::isVirtualRegister(Reg))
132 if (regsKilled.count(Reg) || regsLiveOut.count(Reg))
134 return vregsPassed.insert(Reg).second;
137 // Same for a full set.
138 bool addPassed(const RegSet &RS) {
139 bool changed = false;
140 for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
146 // Add register to vregsRequired if it belongs there. Return true if
148 bool addRequired(unsigned Reg) {
149 if (!TargetRegisterInfo::isVirtualRegister(Reg))
151 if (regsLiveOut.count(Reg))
153 return vregsRequired.insert(Reg).second;
156 // Same for a full set.
157 bool addRequired(const RegSet &RS) {
158 bool changed = false;
159 for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
165 // Same for a full map.
166 bool addRequired(const RegMap &RM) {
167 bool changed = false;
168 for (RegMap::const_iterator I = RM.begin(), E = RM.end(); I != E; ++I)
169 if (addRequired(I->first))
174 // Live-out registers are either in regsLiveOut or vregsPassed.
175 bool isLiveOut(unsigned Reg) const {
176 return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
180 // Extra register info per MBB.
181 DenseMap<const MachineBasicBlock*, BBInfo> MBBInfoMap;
183 bool isReserved(unsigned Reg) {
184 return Reg < regsReserved.size() && regsReserved.test(Reg);
187 bool isAllocatable(unsigned Reg) {
188 return Reg < TRI->getNumRegs() && MRI->isAllocatable(Reg);
191 // Analysis information if available
192 LiveVariables *LiveVars;
193 LiveIntervals *LiveInts;
194 LiveStacks *LiveStks;
195 SlotIndexes *Indexes;
197 void visitMachineFunctionBefore();
198 void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);
199 void visitMachineBundleBefore(const MachineInstr *MI);
200 void visitMachineInstrBefore(const MachineInstr *MI);
201 void visitMachineOperand(const MachineOperand *MO, unsigned MONum);
202 void visitMachineInstrAfter(const MachineInstr *MI);
203 void visitMachineBundleAfter(const MachineInstr *MI);
204 void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB);
205 void visitMachineFunctionAfter();
207 template <typename T> void report(const char *msg, ilist_iterator<T> I) {
210 void report(const char *msg, const MachineFunction *MF);
211 void report(const char *msg, const MachineBasicBlock *MBB);
212 void report(const char *msg, const MachineInstr *MI);
213 void report(const char *msg, const MachineOperand *MO, unsigned MONum);
214 void report(const char *msg, const MachineFunction *MF,
215 const LiveInterval &LI);
216 void report(const char *msg, const MachineBasicBlock *MBB,
217 const LiveInterval &LI);
218 void report(const char *msg, const MachineFunction *MF,
219 const LiveRange &LR, unsigned Reg, LaneBitmask LaneMask);
220 void report(const char *msg, const MachineBasicBlock *MBB,
221 const LiveRange &LR, unsigned Reg, LaneBitmask LaneMask);
223 void verifyInlineAsm(const MachineInstr *MI);
225 void checkLiveness(const MachineOperand *MO, unsigned MONum);
226 void markReachable(const MachineBasicBlock *MBB);
227 void calcRegsPassed();
228 void checkPHIOps(const MachineBasicBlock *MBB);
230 void calcRegsRequired();
231 void verifyLiveVariables();
232 void verifyLiveIntervals();
233 void verifyLiveInterval(const LiveInterval&);
234 void verifyLiveRangeValue(const LiveRange&, const VNInfo*, unsigned,
236 void verifyLiveRangeSegment(const LiveRange&,
237 const LiveRange::const_iterator I, unsigned,
239 void verifyLiveRange(const LiveRange&, unsigned, LaneBitmask LaneMask = 0);
241 void verifyStackFrame();
243 void verifySlotIndexes() const;
246 struct MachineVerifierPass : public MachineFunctionPass {
247 static char ID; // Pass ID, replacement for typeid
248 const std::string Banner;
250 MachineVerifierPass(const std::string &banner = nullptr)
251 : MachineFunctionPass(ID), Banner(banner) {
252 initializeMachineVerifierPassPass(*PassRegistry::getPassRegistry());
255 void getAnalysisUsage(AnalysisUsage &AU) const override {
256 AU.setPreservesAll();
257 MachineFunctionPass::getAnalysisUsage(AU);
260 bool runOnMachineFunction(MachineFunction &MF) override {
261 MF.verify(this, Banner.c_str());
268 char MachineVerifierPass::ID = 0;
269 INITIALIZE_PASS(MachineVerifierPass, "machineverifier",
270 "Verify generated machine code", false, false)
272 FunctionPass *llvm::createMachineVerifierPass(const std::string &Banner) {
273 return new MachineVerifierPass(Banner);
276 void MachineFunction::verify(Pass *p, const char *Banner) const {
277 MachineVerifier(p, Banner)
278 .runOnMachineFunction(const_cast<MachineFunction&>(*this));
281 void MachineVerifier::verifySlotIndexes() const {
282 if (Indexes == nullptr)
285 // Ensure the IdxMBB list is sorted by slot indexes.
287 for (SlotIndexes::MBBIndexIterator I = Indexes->MBBIndexBegin(),
288 E = Indexes->MBBIndexEnd(); I != E; ++I) {
289 assert(!Last.isValid() || I->first > Last);
294 bool MachineVerifier::runOnMachineFunction(MachineFunction &MF) {
298 TM = &MF.getTarget();
299 TII = MF.getSubtarget().getInstrInfo();
300 TRI = MF.getSubtarget().getRegisterInfo();
301 MRI = &MF.getRegInfo();
308 LiveInts = PASS->getAnalysisIfAvailable<LiveIntervals>();
309 // We don't want to verify LiveVariables if LiveIntervals is available.
311 LiveVars = PASS->getAnalysisIfAvailable<LiveVariables>();
312 LiveStks = PASS->getAnalysisIfAvailable<LiveStacks>();
313 Indexes = PASS->getAnalysisIfAvailable<SlotIndexes>();
318 visitMachineFunctionBefore();
319 for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end();
321 visitMachineBasicBlockBefore(&*MFI);
322 // Keep track of the current bundle header.
323 const MachineInstr *CurBundle = nullptr;
324 // Do we expect the next instruction to be part of the same bundle?
325 bool InBundle = false;
327 for (MachineBasicBlock::const_instr_iterator MBBI = MFI->instr_begin(),
328 MBBE = MFI->instr_end(); MBBI != MBBE; ++MBBI) {
329 if (MBBI->getParent() != &*MFI) {
330 report("Bad instruction parent pointer", MFI);
331 errs() << "Instruction: " << *MBBI;
335 // Check for consistent bundle flags.
336 if (InBundle && !MBBI->isBundledWithPred())
337 report("Missing BundledPred flag, "
338 "BundledSucc was set on predecessor",
340 if (!InBundle && MBBI->isBundledWithPred())
341 report("BundledPred flag is set, "
342 "but BundledSucc not set on predecessor",
345 // Is this a bundle header?
346 if (!MBBI->isInsideBundle()) {
348 visitMachineBundleAfter(CurBundle);
350 visitMachineBundleBefore(CurBundle);
351 } else if (!CurBundle)
352 report("No bundle header", MBBI);
353 visitMachineInstrBefore(&*MBBI);
354 for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) {
355 const MachineInstr &MI = *MBBI;
356 const MachineOperand &Op = MI.getOperand(I);
357 if (Op.getParent() != &MI) {
358 // Make sure to use correct addOperand / RemoveOperand / ChangeTo
359 // functions when replacing operands of a MachineInstr.
360 report("Instruction has operand with wrong parent set", &MI);
363 visitMachineOperand(&Op, I);
366 visitMachineInstrAfter(&*MBBI);
368 // Was this the last bundled instruction?
369 InBundle = MBBI->isBundledWithSucc();
372 visitMachineBundleAfter(CurBundle);
374 report("BundledSucc flag set on last instruction in block", &MFI->back());
375 visitMachineBasicBlockAfter(&*MFI);
377 visitMachineFunctionAfter();
380 report_fatal_error("Found "+Twine(foundErrors)+" machine code errors.");
388 regsLiveInButUnused.clear();
391 return false; // no changes
394 void MachineVerifier::report(const char *msg, const MachineFunction *MF) {
397 if (!foundErrors++) {
399 errs() << "# " << Banner << '\n';
400 if (LiveInts != nullptr)
401 LiveInts->print(errs());
403 MF->print(errs(), Indexes);
405 errs() << "*** Bad machine code: " << msg << " ***\n"
406 << "- function: " << MF->getName() << "\n";
409 void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB) {
411 report(msg, MBB->getParent());
412 errs() << "- basic block: BB#" << MBB->getNumber()
413 << ' ' << MBB->getName()
414 << " (" << (const void*)MBB << ')';
416 errs() << " [" << Indexes->getMBBStartIdx(MBB)
417 << ';' << Indexes->getMBBEndIdx(MBB) << ')';
421 void MachineVerifier::report(const char *msg, const MachineInstr *MI) {
423 report(msg, MI->getParent());
424 errs() << "- instruction: ";
425 if (Indexes && Indexes->hasIndex(MI))
426 errs() << Indexes->getInstructionIndex(MI) << '\t';
427 MI->print(errs(), TM);
430 void MachineVerifier::report(const char *msg,
431 const MachineOperand *MO, unsigned MONum) {
433 report(msg, MO->getParent());
434 errs() << "- operand " << MONum << ": ";
435 MO->print(errs(), TRI);
439 void MachineVerifier::report(const char *msg, const MachineFunction *MF,
440 const LiveInterval &LI) {
442 errs() << "- interval: " << LI << '\n';
445 void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB,
446 const LiveInterval &LI) {
448 errs() << "- interval: " << LI << '\n';
451 void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB,
452 const LiveRange &LR, unsigned Reg,
453 LaneBitmask LaneMask) {
455 errs() << "- liverange: " << LR << '\n';
456 errs() << "- register: " << PrintReg(Reg, TRI) << '\n';
458 errs() << "- lanemask: " << PrintLaneMask(LaneMask) << '\n';
461 void MachineVerifier::report(const char *msg, const MachineFunction *MF,
462 const LiveRange &LR, unsigned Reg,
463 LaneBitmask LaneMask) {
465 errs() << "- liverange: " << LR << '\n';
466 errs() << "- register: " << PrintReg(Reg, TRI) << '\n';
468 errs() << "- lanemask: " << PrintLaneMask(LaneMask) << '\n';
471 void MachineVerifier::markReachable(const MachineBasicBlock *MBB) {
472 BBInfo &MInfo = MBBInfoMap[MBB];
473 if (!MInfo.reachable) {
474 MInfo.reachable = true;
475 for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
476 SuE = MBB->succ_end(); SuI != SuE; ++SuI)
481 void MachineVerifier::visitMachineFunctionBefore() {
482 lastIndex = SlotIndex();
483 regsReserved = MRI->getReservedRegs();
485 // A sub-register of a reserved register is also reserved
486 for (int Reg = regsReserved.find_first(); Reg>=0;
487 Reg = regsReserved.find_next(Reg)) {
488 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
489 // FIXME: This should probably be:
490 // assert(regsReserved.test(*SubRegs) && "Non-reserved sub-register");
491 regsReserved.set(*SubRegs);
495 markReachable(&MF->front());
497 // Build a set of the basic blocks in the function.
498 FunctionBlocks.clear();
499 for (const auto &MBB : *MF) {
500 FunctionBlocks.insert(&MBB);
501 BBInfo &MInfo = MBBInfoMap[&MBB];
503 MInfo.Preds.insert(MBB.pred_begin(), MBB.pred_end());
504 if (MInfo.Preds.size() != MBB.pred_size())
505 report("MBB has duplicate entries in its predecessor list.", &MBB);
507 MInfo.Succs.insert(MBB.succ_begin(), MBB.succ_end());
508 if (MInfo.Succs.size() != MBB.succ_size())
509 report("MBB has duplicate entries in its successor list.", &MBB);
512 // Check that the register use lists are sane.
513 MRI->verifyUseLists();
518 // Does iterator point to a and b as the first two elements?
519 static bool matchPair(MachineBasicBlock::const_succ_iterator i,
520 const MachineBasicBlock *a, const MachineBasicBlock *b) {
529 MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
530 FirstTerminator = nullptr;
533 // If this block has allocatable physical registers live-in, check that
534 // it is an entry block or landing pad.
535 for (const auto &LI : MBB->liveins()) {
536 if (isAllocatable(LI.PhysReg) && !MBB->isEHPad() &&
537 MBB != MBB->getParent()->begin()) {
538 report("MBB has allocable live-in, but isn't entry or landing-pad.", MBB);
543 // Count the number of landing pad successors.
544 SmallPtrSet<MachineBasicBlock*, 4> LandingPadSuccs;
545 for (MachineBasicBlock::const_succ_iterator I = MBB->succ_begin(),
546 E = MBB->succ_end(); I != E; ++I) {
548 LandingPadSuccs.insert(*I);
549 if (!FunctionBlocks.count(*I))
550 report("MBB has successor that isn't part of the function.", MBB);
551 if (!MBBInfoMap[*I].Preds.count(MBB)) {
552 report("Inconsistent CFG", MBB);
553 errs() << "MBB is not in the predecessor list of the successor BB#"
554 << (*I)->getNumber() << ".\n";
558 // Check the predecessor list.
559 for (MachineBasicBlock::const_pred_iterator I = MBB->pred_begin(),
560 E = MBB->pred_end(); I != E; ++I) {
561 if (!FunctionBlocks.count(*I))
562 report("MBB has predecessor that isn't part of the function.", MBB);
563 if (!MBBInfoMap[*I].Succs.count(MBB)) {
564 report("Inconsistent CFG", MBB);
565 errs() << "MBB is not in the successor list of the predecessor BB#"
566 << (*I)->getNumber() << ".\n";
570 const MCAsmInfo *AsmInfo = TM->getMCAsmInfo();
571 const BasicBlock *BB = MBB->getBasicBlock();
572 const Function *Fn = MF->getFunction();
573 if (LandingPadSuccs.size() > 1 &&
575 AsmInfo->getExceptionHandlingType() == ExceptionHandling::SjLj &&
576 BB && isa<SwitchInst>(BB->getTerminator())) &&
577 !isFuncletEHPersonality(classifyEHPersonality(Fn->getPersonalityFn())))
578 report("MBB has more than one landing pad successor", MBB);
580 // Call AnalyzeBranch. If it succeeds, there several more conditions to check.
581 MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
582 SmallVector<MachineOperand, 4> Cond;
583 if (!TII->AnalyzeBranch(*const_cast<MachineBasicBlock *>(MBB),
585 // Ok, AnalyzeBranch thinks it knows what's going on with this block. Let's
586 // check whether its answers match up with reality.
588 // Block falls through to its successor.
589 MachineFunction::const_iterator MBBI = MBB->getIterator();
591 if (MBBI == MF->end()) {
592 // It's possible that the block legitimately ends with a noreturn
593 // call or an unreachable, in which case it won't actually fall
594 // out the bottom of the function.
595 } else if (MBB->succ_size() == LandingPadSuccs.size()) {
596 // It's possible that the block legitimately ends with a noreturn
597 // call or an unreachable, in which case it won't actuall fall
599 } else if (MBB->succ_size() != 1+LandingPadSuccs.size()) {
600 report("MBB exits via unconditional fall-through but doesn't have "
601 "exactly one CFG successor!", MBB);
602 } else if (!MBB->isSuccessor(&*MBBI)) {
603 report("MBB exits via unconditional fall-through but its successor "
604 "differs from its CFG successor!", MBB);
606 if (!MBB->empty() && MBB->back().isBarrier() &&
607 !TII->isPredicated(&MBB->back())) {
608 report("MBB exits via unconditional fall-through but ends with a "
609 "barrier instruction!", MBB);
612 report("MBB exits via unconditional fall-through but has a condition!",
615 } else if (TBB && !FBB && Cond.empty()) {
616 // Block unconditionally branches somewhere.
617 // If the block has exactly one successor, that happens to be a
618 // landingpad, accept it as valid control flow.
619 if (MBB->succ_size() != 1+LandingPadSuccs.size() &&
620 (MBB->succ_size() != 1 || LandingPadSuccs.size() != 1 ||
621 *MBB->succ_begin() != *LandingPadSuccs.begin())) {
622 report("MBB exits via unconditional branch but doesn't have "
623 "exactly one CFG successor!", MBB);
624 } else if (!MBB->isSuccessor(TBB)) {
625 report("MBB exits via unconditional branch but the CFG "
626 "successor doesn't match the actual successor!", MBB);
629 report("MBB exits via unconditional branch but doesn't contain "
630 "any instructions!", MBB);
631 } else if (!MBB->back().isBarrier()) {
632 report("MBB exits via unconditional branch but doesn't end with a "
633 "barrier instruction!", MBB);
634 } else if (!MBB->back().isTerminator()) {
635 report("MBB exits via unconditional branch but the branch isn't a "
636 "terminator instruction!", MBB);
638 } else if (TBB && !FBB && !Cond.empty()) {
639 // Block conditionally branches somewhere, otherwise falls through.
640 MachineFunction::const_iterator MBBI = MBB->getIterator();
642 if (MBBI == MF->end()) {
643 report("MBB conditionally falls through out of function!", MBB);
644 } else if (MBB->succ_size() == 1) {
645 // A conditional branch with only one successor is weird, but allowed.
647 report("MBB exits via conditional branch/fall-through but only has "
648 "one CFG successor!", MBB);
649 else if (TBB != *MBB->succ_begin())
650 report("MBB exits via conditional branch/fall-through but the CFG "
651 "successor don't match the actual successor!", MBB);
652 } else if (MBB->succ_size() != 2) {
653 report("MBB exits via conditional branch/fall-through but doesn't have "
654 "exactly two CFG successors!", MBB);
655 } else if (!matchPair(MBB->succ_begin(), TBB, &*MBBI)) {
656 report("MBB exits via conditional branch/fall-through but the CFG "
657 "successors don't match the actual successors!", MBB);
660 report("MBB exits via conditional branch/fall-through but doesn't "
661 "contain any instructions!", MBB);
662 } else if (MBB->back().isBarrier()) {
663 report("MBB exits via conditional branch/fall-through but ends with a "
664 "barrier instruction!", MBB);
665 } else if (!MBB->back().isTerminator()) {
666 report("MBB exits via conditional branch/fall-through but the branch "
667 "isn't a terminator instruction!", MBB);
669 } else if (TBB && FBB) {
670 // Block conditionally branches somewhere, otherwise branches
672 if (MBB->succ_size() == 1) {
673 // A conditional branch with only one successor is weird, but allowed.
675 report("MBB exits via conditional branch/branch through but only has "
676 "one CFG successor!", MBB);
677 else if (TBB != *MBB->succ_begin())
678 report("MBB exits via conditional branch/branch through but the CFG "
679 "successor don't match the actual successor!", MBB);
680 } else if (MBB->succ_size() != 2) {
681 report("MBB exits via conditional branch/branch but doesn't have "
682 "exactly two CFG successors!", MBB);
683 } else if (!matchPair(MBB->succ_begin(), TBB, FBB)) {
684 report("MBB exits via conditional branch/branch but the CFG "
685 "successors don't match the actual successors!", MBB);
688 report("MBB exits via conditional branch/branch but doesn't "
689 "contain any instructions!", MBB);
690 } else if (!MBB->back().isBarrier()) {
691 report("MBB exits via conditional branch/branch but doesn't end with a "
692 "barrier instruction!", MBB);
693 } else if (!MBB->back().isTerminator()) {
694 report("MBB exits via conditional branch/branch but the branch "
695 "isn't a terminator instruction!", MBB);
698 report("MBB exits via conditinal branch/branch but there's no "
702 report("AnalyzeBranch returned invalid data!", MBB);
707 for (const auto &LI : MBB->liveins()) {
708 if (!TargetRegisterInfo::isPhysicalRegister(LI.PhysReg)) {
709 report("MBB live-in list contains non-physical register", MBB);
712 for (MCSubRegIterator SubRegs(LI.PhysReg, TRI, /*IncludeSelf=*/true);
713 SubRegs.isValid(); ++SubRegs)
714 regsLive.insert(*SubRegs);
716 regsLiveInButUnused = regsLive;
718 const MachineFrameInfo *MFI = MF->getFrameInfo();
719 assert(MFI && "Function has no frame info");
720 BitVector PR = MFI->getPristineRegs(*MF);
721 for (int I = PR.find_first(); I>0; I = PR.find_next(I)) {
722 for (MCSubRegIterator SubRegs(I, TRI, /*IncludeSelf=*/true);
723 SubRegs.isValid(); ++SubRegs)
724 regsLive.insert(*SubRegs);
731 lastIndex = Indexes->getMBBStartIdx(MBB);
734 // This function gets called for all bundle headers, including normal
735 // stand-alone unbundled instructions.
736 void MachineVerifier::visitMachineBundleBefore(const MachineInstr *MI) {
737 if (Indexes && Indexes->hasIndex(MI)) {
738 SlotIndex idx = Indexes->getInstructionIndex(MI);
739 if (!(idx > lastIndex)) {
740 report("Instruction index out of order", MI);
741 errs() << "Last instruction was at " << lastIndex << '\n';
746 // Ensure non-terminators don't follow terminators.
747 // Ignore predicated terminators formed by if conversion.
748 // FIXME: If conversion shouldn't need to violate this rule.
749 if (MI->isTerminator() && !TII->isPredicated(MI)) {
750 if (!FirstTerminator)
751 FirstTerminator = MI;
752 } else if (FirstTerminator) {
753 report("Non-terminator instruction after the first terminator", MI);
754 errs() << "First terminator was:\t" << *FirstTerminator;
758 // The operands on an INLINEASM instruction must follow a template.
759 // Verify that the flag operands make sense.
760 void MachineVerifier::verifyInlineAsm(const MachineInstr *MI) {
761 // The first two operands on INLINEASM are the asm string and global flags.
762 if (MI->getNumOperands() < 2) {
763 report("Too few operands on inline asm", MI);
766 if (!MI->getOperand(0).isSymbol())
767 report("Asm string must be an external symbol", MI);
768 if (!MI->getOperand(1).isImm())
769 report("Asm flags must be an immediate", MI);
770 // Allowed flags are Extra_HasSideEffects = 1, Extra_IsAlignStack = 2,
771 // Extra_AsmDialect = 4, Extra_MayLoad = 8, and Extra_MayStore = 16.
772 if (!isUInt<5>(MI->getOperand(1).getImm()))
773 report("Unknown asm flags", &MI->getOperand(1), 1);
775 static_assert(InlineAsm::MIOp_FirstOperand == 2, "Asm format changed");
777 unsigned OpNo = InlineAsm::MIOp_FirstOperand;
779 for (unsigned e = MI->getNumOperands(); OpNo < e; OpNo += NumOps) {
780 const MachineOperand &MO = MI->getOperand(OpNo);
781 // There may be implicit ops after the fixed operands.
784 NumOps = 1 + InlineAsm::getNumOperandRegisters(MO.getImm());
787 if (OpNo > MI->getNumOperands())
788 report("Missing operands in last group", MI);
790 // An optional MDNode follows the groups.
791 if (OpNo < MI->getNumOperands() && MI->getOperand(OpNo).isMetadata())
794 // All trailing operands must be implicit registers.
795 for (unsigned e = MI->getNumOperands(); OpNo < e; ++OpNo) {
796 const MachineOperand &MO = MI->getOperand(OpNo);
797 if (!MO.isReg() || !MO.isImplicit())
798 report("Expected implicit register after groups", &MO, OpNo);
802 void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
803 const MCInstrDesc &MCID = MI->getDesc();
804 if (MI->getNumOperands() < MCID.getNumOperands()) {
805 report("Too few operands", MI);
806 errs() << MCID.getNumOperands() << " operands expected, but "
807 << MI->getNumOperands() << " given.\n";
810 // Check the tied operands.
811 if (MI->isInlineAsm())
814 // Check the MachineMemOperands for basic consistency.
815 for (MachineInstr::mmo_iterator I = MI->memoperands_begin(),
816 E = MI->memoperands_end(); I != E; ++I) {
817 if ((*I)->isLoad() && !MI->mayLoad())
818 report("Missing mayLoad flag", MI);
819 if ((*I)->isStore() && !MI->mayStore())
820 report("Missing mayStore flag", MI);
823 // Debug values must not have a slot index.
824 // Other instructions must have one, unless they are inside a bundle.
826 bool mapped = !LiveInts->isNotInMIMap(MI);
827 if (MI->isDebugValue()) {
829 report("Debug instruction has a slot index", MI);
830 } else if (MI->isInsideBundle()) {
832 report("Instruction inside bundle has a slot index", MI);
835 report("Missing slot index", MI);
840 if (!TII->verifyInstruction(MI, ErrorInfo))
841 report(ErrorInfo.data(), MI);
845 MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
846 const MachineInstr *MI = MO->getParent();
847 const MCInstrDesc &MCID = MI->getDesc();
848 unsigned NumDefs = MCID.getNumDefs();
849 if (MCID.getOpcode() == TargetOpcode::PATCHPOINT)
850 NumDefs = (MONum == 0 && MO->isReg()) ? NumDefs : 0;
852 // The first MCID.NumDefs operands must be explicit register defines
853 if (MONum < NumDefs) {
854 const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
856 report("Explicit definition must be a register", MO, MONum);
857 else if (!MO->isDef() && !MCOI.isOptionalDef())
858 report("Explicit definition marked as use", MO, MONum);
859 else if (MO->isImplicit())
860 report("Explicit definition marked as implicit", MO, MONum);
861 } else if (MONum < MCID.getNumOperands()) {
862 const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
863 // Don't check if it's the last operand in a variadic instruction. See,
864 // e.g., LDM_RET in the arm back end.
866 !(MI->isVariadic() && MONum == MCID.getNumOperands()-1)) {
867 if (MO->isDef() && !MCOI.isOptionalDef())
868 report("Explicit operand marked as def", MO, MONum);
869 if (MO->isImplicit())
870 report("Explicit operand marked as implicit", MO, MONum);
873 int TiedTo = MCID.getOperandConstraint(MONum, MCOI::TIED_TO);
876 report("Tied use must be a register", MO, MONum);
877 else if (!MO->isTied())
878 report("Operand should be tied", MO, MONum);
879 else if (unsigned(TiedTo) != MI->findTiedOperandIdx(MONum))
880 report("Tied def doesn't match MCInstrDesc", MO, MONum);
881 } else if (MO->isReg() && MO->isTied())
882 report("Explicit operand should not be tied", MO, MONum);
884 // ARM adds %reg0 operands to indicate predicates. We'll allow that.
885 if (MO->isReg() && !MO->isImplicit() && !MI->isVariadic() && MO->getReg())
886 report("Extra explicit operand on non-variadic instruction", MO, MONum);
889 switch (MO->getType()) {
890 case MachineOperand::MO_Register: {
891 const unsigned Reg = MO->getReg();
894 if (MRI->tracksLiveness() && !MI->isDebugValue())
895 checkLiveness(MO, MONum);
897 // Verify the consistency of tied operands.
899 unsigned OtherIdx = MI->findTiedOperandIdx(MONum);
900 const MachineOperand &OtherMO = MI->getOperand(OtherIdx);
901 if (!OtherMO.isReg())
902 report("Must be tied to a register", MO, MONum);
903 if (!OtherMO.isTied())
904 report("Missing tie flags on tied operand", MO, MONum);
905 if (MI->findTiedOperandIdx(OtherIdx) != MONum)
906 report("Inconsistent tie links", MO, MONum);
907 if (MONum < MCID.getNumDefs()) {
908 if (OtherIdx < MCID.getNumOperands()) {
909 if (-1 == MCID.getOperandConstraint(OtherIdx, MCOI::TIED_TO))
910 report("Explicit def tied to explicit use without tie constraint",
913 if (!OtherMO.isImplicit())
914 report("Explicit def should be tied to implicit use", MO, MONum);
919 // Verify two-address constraints after leaving SSA form.
921 if (!MRI->isSSA() && MO->isUse() &&
922 MI->isRegTiedToDefOperand(MONum, &DefIdx) &&
923 Reg != MI->getOperand(DefIdx).getReg())
924 report("Two-address instruction operands must be identical", MO, MONum);
926 // Check register classes.
927 if (MONum < MCID.getNumOperands() && !MO->isImplicit()) {
928 unsigned SubIdx = MO->getSubReg();
930 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
932 report("Illegal subregister index for physical register", MO, MONum);
935 if (const TargetRegisterClass *DRC =
936 TII->getRegClass(MCID, MONum, TRI, *MF)) {
937 if (!DRC->contains(Reg)) {
938 report("Illegal physical register for instruction", MO, MONum);
939 errs() << TRI->getName(Reg) << " is not a "
940 << TRI->getRegClassName(DRC) << " register.\n";
945 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
947 const TargetRegisterClass *SRC =
948 TRI->getSubClassWithSubReg(RC, SubIdx);
950 report("Invalid subregister index for virtual register", MO, MONum);
951 errs() << "Register class " << TRI->getRegClassName(RC)
952 << " does not support subreg index " << SubIdx << "\n";
956 report("Invalid register class for subregister index", MO, MONum);
957 errs() << "Register class " << TRI->getRegClassName(RC)
958 << " does not fully support subreg index " << SubIdx << "\n";
962 if (const TargetRegisterClass *DRC =
963 TII->getRegClass(MCID, MONum, TRI, *MF)) {
965 const TargetRegisterClass *SuperRC =
966 TRI->getLargestLegalSuperClass(RC, *MF);
968 report("No largest legal super class exists.", MO, MONum);
971 DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx);
973 report("No matching super-reg register class.", MO, MONum);
977 if (!RC->hasSuperClassEq(DRC)) {
978 report("Illegal virtual register for instruction", MO, MONum);
979 errs() << "Expected a " << TRI->getRegClassName(DRC)
980 << " register, but got a " << TRI->getRegClassName(RC)
989 case MachineOperand::MO_RegisterMask:
990 regMasks.push_back(MO->getRegMask());
993 case MachineOperand::MO_MachineBasicBlock:
994 if (MI->isPHI() && !MO->getMBB()->isSuccessor(MI->getParent()))
995 report("PHI operand is not in the CFG", MO, MONum);
998 case MachineOperand::MO_FrameIndex:
999 if (LiveStks && LiveStks->hasInterval(MO->getIndex()) &&
1000 LiveInts && !LiveInts->isNotInMIMap(MI)) {
1001 int FI = MO->getIndex();
1002 LiveInterval &LI = LiveStks->getInterval(FI);
1003 SlotIndex Idx = LiveInts->getInstructionIndex(MI);
1005 bool stores = MI->mayStore();
1006 bool loads = MI->mayLoad();
1007 // For a memory-to-memory move, we need to check if the frame
1008 // index is used for storing or loading, by inspecting the
1010 if (stores && loads) {
1011 for (auto *MMO : MI->memoperands()) {
1012 const PseudoSourceValue *PSV = MMO->getPseudoValue();
1013 if (PSV == nullptr) continue;
1014 const FixedStackPseudoSourceValue *Value =
1015 dyn_cast<FixedStackPseudoSourceValue>(PSV);
1016 if (Value == nullptr) continue;
1017 if (Value->getFrameIndex() != FI) continue;
1025 if (loads == stores)
1026 report("Missing fixed stack memoperand.", MI);
1028 if (loads && !LI.liveAt(Idx.getRegSlot(true))) {
1029 report("Instruction loads from dead spill slot", MO, MONum);
1030 errs() << "Live stack: " << LI << '\n';
1032 if (stores && !LI.liveAt(Idx.getRegSlot())) {
1033 report("Instruction stores to dead spill slot", MO, MONum);
1034 errs() << "Live stack: " << LI << '\n';
1044 void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) {
1045 const MachineInstr *MI = MO->getParent();
1046 const unsigned Reg = MO->getReg();
1048 // Both use and def operands can read a register.
1049 if (MO->readsReg()) {
1050 regsLiveInButUnused.erase(Reg);
1053 addRegWithSubRegs(regsKilled, Reg);
1055 // Check that LiveVars knows this kill.
1056 if (LiveVars && TargetRegisterInfo::isVirtualRegister(Reg) &&
1058 LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
1059 if (std::find(VI.Kills.begin(), VI.Kills.end(), MI) == VI.Kills.end())
1060 report("Kill missing from LiveVariables", MO, MONum);
1063 // Check LiveInts liveness and kill.
1064 if (LiveInts && !LiveInts->isNotInMIMap(MI)) {
1065 SlotIndex UseIdx = LiveInts->getInstructionIndex(MI);
1066 // Check the cached regunit intervals.
1067 if (TargetRegisterInfo::isPhysicalRegister(Reg) && !isReserved(Reg)) {
1068 for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units) {
1069 if (const LiveRange *LR = LiveInts->getCachedRegUnit(*Units)) {
1070 LiveQueryResult LRQ = LR->Query(UseIdx);
1071 if (!LRQ.valueIn()) {
1072 report("No live segment at use", MO, MONum);
1073 errs() << UseIdx << " is not live in " << PrintRegUnit(*Units, TRI)
1074 << ' ' << *LR << '\n';
1076 if (MO->isKill() && !LRQ.isKill()) {
1077 report("Live range continues after kill flag", MO, MONum);
1078 errs() << PrintRegUnit(*Units, TRI) << ' ' << *LR << '\n';
1084 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
1085 if (LiveInts->hasInterval(Reg)) {
1086 // This is a virtual register interval.
1087 const LiveInterval &LI = LiveInts->getInterval(Reg);
1088 LiveQueryResult LRQ = LI.Query(UseIdx);
1089 if (!LRQ.valueIn()) {
1090 report("No live segment at use", MO, MONum);
1091 errs() << UseIdx << " is not live in " << LI << '\n';
1093 // Check for extra kill flags.
1094 // Note that we allow missing kill flags for now.
1095 if (MO->isKill() && !LRQ.isKill()) {
1096 report("Live range continues after kill flag", MO, MONum);
1097 errs() << "Live range: " << LI << '\n';
1100 report("Virtual register has no live interval", MO, MONum);
1105 // Use of a dead register.
1106 if (!regsLive.count(Reg)) {
1107 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
1108 // Reserved registers may be used even when 'dead'.
1109 bool Bad = !isReserved(Reg);
1110 // We are fine if just any subregister has a defined value.
1112 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid();
1114 if (regsLive.count(*SubRegs)) {
1120 // If there is an additional implicit-use of a super register we stop
1121 // here. By definition we are fine if the super register is not
1122 // (completely) dead, if the complete super register is dead we will
1123 // get a report for its operand.
1125 for (const MachineOperand &MOP : MI->uses()) {
1128 if (!MOP.isImplicit())
1130 for (MCSubRegIterator SubRegs(MOP.getReg(), TRI); SubRegs.isValid();
1132 if (*SubRegs == Reg) {
1140 report("Using an undefined physical register", MO, MONum);
1141 } else if (MRI->def_empty(Reg)) {
1142 report("Reading virtual register without a def", MO, MONum);
1144 BBInfo &MInfo = MBBInfoMap[MI->getParent()];
1145 // We don't know which virtual registers are live in, so only complain
1146 // if vreg was killed in this MBB. Otherwise keep track of vregs that
1147 // must be live in. PHI instructions are handled separately.
1148 if (MInfo.regsKilled.count(Reg))
1149 report("Using a killed virtual register", MO, MONum);
1150 else if (!MI->isPHI())
1151 MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));
1157 // Register defined.
1158 // TODO: verify that earlyclobber ops are not used.
1160 addRegWithSubRegs(regsDead, Reg);
1162 addRegWithSubRegs(regsDefined, Reg);
1165 if (MRI->isSSA() && TargetRegisterInfo::isVirtualRegister(Reg) &&
1166 std::next(MRI->def_begin(Reg)) != MRI->def_end())
1167 report("Multiple virtual register defs in SSA form", MO, MONum);
1169 // Check LiveInts for a live segment, but only for virtual registers.
1170 if (LiveInts && TargetRegisterInfo::isVirtualRegister(Reg) &&
1171 !LiveInts->isNotInMIMap(MI)) {
1172 SlotIndex DefIdx = LiveInts->getInstructionIndex(MI);
1173 DefIdx = DefIdx.getRegSlot(MO->isEarlyClobber());
1174 if (LiveInts->hasInterval(Reg)) {
1175 const LiveInterval &LI = LiveInts->getInterval(Reg);
1176 if (const VNInfo *VNI = LI.getVNInfoAt(DefIdx)) {
1177 assert(VNI && "NULL valno is not allowed");
1178 if (VNI->def != DefIdx) {
1179 report("Inconsistent valno->def", MO, MONum);
1180 errs() << "Valno " << VNI->id << " is not defined at "
1181 << DefIdx << " in " << LI << '\n';
1184 report("No live segment at def", MO, MONum);
1185 errs() << DefIdx << " is not live in " << LI << '\n';
1187 // Check that, if the dead def flag is present, LiveInts agree.
1189 LiveQueryResult LRQ = LI.Query(DefIdx);
1190 if (!LRQ.isDeadDef()) {
1191 report("Live range continues after dead def flag", MO, MONum);
1192 errs() << "Live range: " << LI << '\n';
1196 report("Virtual register has no Live interval", MO, MONum);
1202 void MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI) {
1205 // This function gets called after visiting all instructions in a bundle. The
1206 // argument points to the bundle header.
1207 // Normal stand-alone instructions are also considered 'bundles', and this
1208 // function is called for all of them.
1209 void MachineVerifier::visitMachineBundleAfter(const MachineInstr *MI) {
1210 BBInfo &MInfo = MBBInfoMap[MI->getParent()];
1211 set_union(MInfo.regsKilled, regsKilled);
1212 set_subtract(regsLive, regsKilled); regsKilled.clear();
1213 // Kill any masked registers.
1214 while (!regMasks.empty()) {
1215 const uint32_t *Mask = regMasks.pop_back_val();
1216 for (RegSet::iterator I = regsLive.begin(), E = regsLive.end(); I != E; ++I)
1217 if (TargetRegisterInfo::isPhysicalRegister(*I) &&
1218 MachineOperand::clobbersPhysReg(Mask, *I))
1219 regsDead.push_back(*I);
1221 set_subtract(regsLive, regsDead); regsDead.clear();
1222 set_union(regsLive, regsDefined); regsDefined.clear();
1226 MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB) {
1227 MBBInfoMap[MBB].regsLiveOut = regsLive;
1231 SlotIndex stop = Indexes->getMBBEndIdx(MBB);
1232 if (!(stop > lastIndex)) {
1233 report("Block ends before last instruction index", MBB);
1234 errs() << "Block ends at " << stop
1235 << " last instruction was at " << lastIndex << '\n';
1241 // Calculate the largest possible vregsPassed sets. These are the registers that
1242 // can pass through an MBB live, but may not be live every time. It is assumed
1243 // that all vregsPassed sets are empty before the call.
1244 void MachineVerifier::calcRegsPassed() {
1245 // First push live-out regs to successors' vregsPassed. Remember the MBBs that
1246 // have any vregsPassed.
1247 SmallPtrSet<const MachineBasicBlock*, 8> todo;
1248 for (const auto &MBB : *MF) {
1249 BBInfo &MInfo = MBBInfoMap[&MBB];
1250 if (!MInfo.reachable)
1252 for (MachineBasicBlock::const_succ_iterator SuI = MBB.succ_begin(),
1253 SuE = MBB.succ_end(); SuI != SuE; ++SuI) {
1254 BBInfo &SInfo = MBBInfoMap[*SuI];
1255 if (SInfo.addPassed(MInfo.regsLiveOut))
1260 // Iteratively push vregsPassed to successors. This will converge to the same
1261 // final state regardless of DenseSet iteration order.
1262 while (!todo.empty()) {
1263 const MachineBasicBlock *MBB = *todo.begin();
1265 BBInfo &MInfo = MBBInfoMap[MBB];
1266 for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
1267 SuE = MBB->succ_end(); SuI != SuE; ++SuI) {
1270 BBInfo &SInfo = MBBInfoMap[*SuI];
1271 if (SInfo.addPassed(MInfo.vregsPassed))
1277 // Calculate the set of virtual registers that must be passed through each basic
1278 // block in order to satisfy the requirements of successor blocks. This is very
1279 // similar to calcRegsPassed, only backwards.
1280 void MachineVerifier::calcRegsRequired() {
1281 // First push live-in regs to predecessors' vregsRequired.
1282 SmallPtrSet<const MachineBasicBlock*, 8> todo;
1283 for (const auto &MBB : *MF) {
1284 BBInfo &MInfo = MBBInfoMap[&MBB];
1285 for (MachineBasicBlock::const_pred_iterator PrI = MBB.pred_begin(),
1286 PrE = MBB.pred_end(); PrI != PrE; ++PrI) {
1287 BBInfo &PInfo = MBBInfoMap[*PrI];
1288 if (PInfo.addRequired(MInfo.vregsLiveIn))
1293 // Iteratively push vregsRequired to predecessors. This will converge to the
1294 // same final state regardless of DenseSet iteration order.
1295 while (!todo.empty()) {
1296 const MachineBasicBlock *MBB = *todo.begin();
1298 BBInfo &MInfo = MBBInfoMap[MBB];
1299 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
1300 PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
1303 BBInfo &SInfo = MBBInfoMap[*PrI];
1304 if (SInfo.addRequired(MInfo.vregsRequired))
1310 // Check PHI instructions at the beginning of MBB. It is assumed that
1311 // calcRegsPassed has been run so BBInfo::isLiveOut is valid.
1312 void MachineVerifier::checkPHIOps(const MachineBasicBlock *MBB) {
1313 SmallPtrSet<const MachineBasicBlock*, 8> seen;
1314 for (const auto &BBI : *MBB) {
1319 for (unsigned i = 1, e = BBI.getNumOperands(); i != e; i += 2) {
1320 unsigned Reg = BBI.getOperand(i).getReg();
1321 const MachineBasicBlock *Pre = BBI.getOperand(i + 1).getMBB();
1322 if (!Pre->isSuccessor(MBB))
1325 BBInfo &PrInfo = MBBInfoMap[Pre];
1326 if (PrInfo.reachable && !PrInfo.isLiveOut(Reg))
1327 report("PHI operand is not live-out from predecessor",
1328 &BBI.getOperand(i), i);
1331 // Did we see all predecessors?
1332 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
1333 PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
1334 if (!seen.count(*PrI)) {
1335 report("Missing PHI operand", &BBI);
1336 errs() << "BB#" << (*PrI)->getNumber()
1337 << " is a predecessor according to the CFG.\n";
1343 void MachineVerifier::visitMachineFunctionAfter() {
1346 for (const auto &MBB : *MF) {
1347 BBInfo &MInfo = MBBInfoMap[&MBB];
1349 // Skip unreachable MBBs.
1350 if (!MInfo.reachable)
1356 // Now check liveness info if available
1359 // Check for killed virtual registers that should be live out.
1360 for (const auto &MBB : *MF) {
1361 BBInfo &MInfo = MBBInfoMap[&MBB];
1362 for (RegSet::iterator
1363 I = MInfo.vregsRequired.begin(), E = MInfo.vregsRequired.end(); I != E;
1365 if (MInfo.regsKilled.count(*I)) {
1366 report("Virtual register killed in block, but needed live out.", &MBB);
1367 errs() << "Virtual register " << PrintReg(*I)
1368 << " is used after the block.\n";
1373 BBInfo &MInfo = MBBInfoMap[&MF->front()];
1374 for (RegSet::iterator
1375 I = MInfo.vregsRequired.begin(), E = MInfo.vregsRequired.end(); I != E;
1377 report("Virtual register def doesn't dominate all uses.",
1378 MRI->getVRegDef(*I));
1382 verifyLiveVariables();
1384 verifyLiveIntervals();
1387 void MachineVerifier::verifyLiveVariables() {
1388 assert(LiveVars && "Don't call verifyLiveVariables without LiveVars");
1389 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
1390 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
1391 LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
1392 for (const auto &MBB : *MF) {
1393 BBInfo &MInfo = MBBInfoMap[&MBB];
1395 // Our vregsRequired should be identical to LiveVariables' AliveBlocks
1396 if (MInfo.vregsRequired.count(Reg)) {
1397 if (!VI.AliveBlocks.test(MBB.getNumber())) {
1398 report("LiveVariables: Block missing from AliveBlocks", &MBB);
1399 errs() << "Virtual register " << PrintReg(Reg)
1400 << " must be live through the block.\n";
1403 if (VI.AliveBlocks.test(MBB.getNumber())) {
1404 report("LiveVariables: Block should not be in AliveBlocks", &MBB);
1405 errs() << "Virtual register " << PrintReg(Reg)
1406 << " is not needed live through the block.\n";
1413 void MachineVerifier::verifyLiveIntervals() {
1414 assert(LiveInts && "Don't call verifyLiveIntervals without LiveInts");
1415 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
1416 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
1418 // Spilling and splitting may leave unused registers around. Skip them.
1419 if (MRI->reg_nodbg_empty(Reg))
1422 if (!LiveInts->hasInterval(Reg)) {
1423 report("Missing live interval for virtual register", MF);
1424 errs() << PrintReg(Reg, TRI) << " still has defs or uses\n";
1428 const LiveInterval &LI = LiveInts->getInterval(Reg);
1429 assert(Reg == LI.reg && "Invalid reg to interval mapping");
1430 verifyLiveInterval(LI);
1433 // Verify all the cached regunit intervals.
1434 for (unsigned i = 0, e = TRI->getNumRegUnits(); i != e; ++i)
1435 if (const LiveRange *LR = LiveInts->getCachedRegUnit(i))
1436 verifyLiveRange(*LR, i);
1439 void MachineVerifier::verifyLiveRangeValue(const LiveRange &LR,
1440 const VNInfo *VNI, unsigned Reg,
1441 LaneBitmask LaneMask) {
1442 if (VNI->isUnused())
1445 const VNInfo *DefVNI = LR.getVNInfoAt(VNI->def);
1448 report("Valno not live at def and not marked unused", MF, LR, Reg,
1450 errs() << "Valno #" << VNI->id << '\n';
1454 if (DefVNI != VNI) {
1455 report("Live segment at def has different valno", MF, LR, Reg, LaneMask);
1456 errs() << "Valno #" << VNI->id << " is defined at " << VNI->def
1457 << " where valno #" << DefVNI->id << " is live\n";
1461 const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(VNI->def);
1463 report("Invalid definition index", MF, LR, Reg, LaneMask);
1464 errs() << "Valno #" << VNI->id << " is defined at " << VNI->def
1465 << " in " << LR << '\n';
1469 if (VNI->isPHIDef()) {
1470 if (VNI->def != LiveInts->getMBBStartIdx(MBB)) {
1471 report("PHIDef value is not defined at MBB start", MBB, LR, Reg,
1473 errs() << "Valno #" << VNI->id << " is defined at " << VNI->def
1474 << ", not at the beginning of BB#" << MBB->getNumber() << '\n';
1480 const MachineInstr *MI = LiveInts->getInstructionFromIndex(VNI->def);
1482 report("No instruction at def index", MBB, LR, Reg, LaneMask);
1483 errs() << "Valno #" << VNI->id << " is defined at " << VNI->def << '\n';
1488 bool hasDef = false;
1489 bool isEarlyClobber = false;
1490 for (ConstMIBundleOperands MOI(MI); MOI.isValid(); ++MOI) {
1491 if (!MOI->isReg() || !MOI->isDef())
1493 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
1494 if (MOI->getReg() != Reg)
1497 if (!TargetRegisterInfo::isPhysicalRegister(MOI->getReg()) ||
1498 !TRI->hasRegUnit(MOI->getReg(), Reg))
1501 if (LaneMask != 0 &&
1502 (TRI->getSubRegIndexLaneMask(MOI->getSubReg()) & LaneMask) == 0)
1505 if (MOI->isEarlyClobber())
1506 isEarlyClobber = true;
1510 report("Defining instruction does not modify register", MI);
1511 errs() << "Valno #" << VNI->id << " in " << LR << '\n';
1514 // Early clobber defs begin at USE slots, but other defs must begin at
1516 if (isEarlyClobber) {
1517 if (!VNI->def.isEarlyClobber()) {
1518 report("Early clobber def must be at an early-clobber slot", MBB, LR,
1520 errs() << "Valno #" << VNI->id << " is defined at " << VNI->def << '\n';
1522 } else if (!VNI->def.isRegister()) {
1523 report("Non-PHI, non-early clobber def must be at a register slot",
1524 MBB, LR, Reg, LaneMask);
1525 errs() << "Valno #" << VNI->id << " is defined at " << VNI->def << '\n';
1530 void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR,
1531 const LiveRange::const_iterator I,
1532 unsigned Reg, LaneBitmask LaneMask)
1534 const LiveRange::Segment &S = *I;
1535 const VNInfo *VNI = S.valno;
1536 assert(VNI && "Live segment has no valno");
1538 if (VNI->id >= LR.getNumValNums() || VNI != LR.getValNumInfo(VNI->id)) {
1539 report("Foreign valno in live segment", MF, LR, Reg, LaneMask);
1540 errs() << S << " has a bad valno\n";
1543 if (VNI->isUnused()) {
1544 report("Live segment valno is marked unused", MF, LR, Reg, LaneMask);
1545 errs() << S << '\n';
1548 const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(S.start);
1550 report("Bad start of live segment, no basic block", MF, LR, Reg, LaneMask);
1551 errs() << S << '\n';
1554 SlotIndex MBBStartIdx = LiveInts->getMBBStartIdx(MBB);
1555 if (S.start != MBBStartIdx && S.start != VNI->def) {
1556 report("Live segment must begin at MBB entry or valno def", MBB, LR, Reg,
1558 errs() << S << '\n';
1561 const MachineBasicBlock *EndMBB =
1562 LiveInts->getMBBFromIndex(S.end.getPrevSlot());
1564 report("Bad end of live segment, no basic block", MF, LR, Reg, LaneMask);
1565 errs() << S << '\n';
1569 // No more checks for live-out segments.
1570 if (S.end == LiveInts->getMBBEndIdx(EndMBB))
1573 // RegUnit intervals are allowed dead phis.
1574 if (!TargetRegisterInfo::isVirtualRegister(Reg) && VNI->isPHIDef() &&
1575 S.start == VNI->def && S.end == VNI->def.getDeadSlot())
1578 // The live segment is ending inside EndMBB
1579 const MachineInstr *MI =
1580 LiveInts->getInstructionFromIndex(S.end.getPrevSlot());
1582 report("Live segment doesn't end at a valid instruction", EndMBB, LR, Reg,
1584 errs() << S << '\n';
1588 // The block slot must refer to a basic block boundary.
1589 if (S.end.isBlock()) {
1590 report("Live segment ends at B slot of an instruction", EndMBB, LR, Reg,
1592 errs() << S << '\n';
1595 if (S.end.isDead()) {
1596 // Segment ends on the dead slot.
1597 // That means there must be a dead def.
1598 if (!SlotIndex::isSameInstr(S.start, S.end)) {
1599 report("Live segment ending at dead slot spans instructions", EndMBB, LR,
1601 errs() << S << '\n';
1605 // A live segment can only end at an early-clobber slot if it is being
1606 // redefined by an early-clobber def.
1607 if (S.end.isEarlyClobber()) {
1608 if (I+1 == LR.end() || (I+1)->start != S.end) {
1609 report("Live segment ending at early clobber slot must be "
1610 "redefined by an EC def in the same instruction", EndMBB, LR, Reg,
1612 errs() << S << '\n';
1616 // The following checks only apply to virtual registers. Physreg liveness
1617 // is too weird to check.
1618 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
1619 // A live segment can end with either a redefinition, a kill flag on a
1620 // use, or a dead flag on a def.
1621 bool hasRead = false;
1622 bool hasSubRegDef = false;
1623 for (ConstMIBundleOperands MOI(MI); MOI.isValid(); ++MOI) {
1624 if (!MOI->isReg() || MOI->getReg() != Reg)
1626 if (LaneMask != 0 &&
1627 (LaneMask & TRI->getSubRegIndexLaneMask(MOI->getSubReg())) == 0)
1629 if (MOI->isDef() && MOI->getSubReg() != 0)
1630 hasSubRegDef = true;
1631 if (MOI->readsReg())
1634 if (!S.end.isDead()) {
1636 // When tracking subregister liveness, the main range must start new
1637 // values on partial register writes, even if there is no read.
1638 if (!MRI->shouldTrackSubRegLiveness(Reg) || LaneMask != 0 ||
1640 report("Instruction ending live segment doesn't read the register",
1642 errs() << S << " in " << LR << '\n';
1648 // Now check all the basic blocks in this live segment.
1649 MachineFunction::const_iterator MFI = MBB->getIterator();
1650 // Is this live segment the beginning of a non-PHIDef VN?
1651 if (S.start == VNI->def && !VNI->isPHIDef()) {
1652 // Not live-in to any blocks.
1659 assert(LiveInts->isLiveInToMBB(LR, &*MFI));
1660 // We don't know how to track physregs into a landing pad.
1661 if (!TargetRegisterInfo::isVirtualRegister(Reg) &&
1663 if (&*MFI == EndMBB)
1669 // Is VNI a PHI-def in the current block?
1670 bool IsPHI = VNI->isPHIDef() &&
1671 VNI->def == LiveInts->getMBBStartIdx(&*MFI);
1673 // Check that VNI is live-out of all predecessors.
1674 for (MachineBasicBlock::const_pred_iterator PI = MFI->pred_begin(),
1675 PE = MFI->pred_end(); PI != PE; ++PI) {
1676 SlotIndex PEnd = LiveInts->getMBBEndIdx(*PI);
1677 const VNInfo *PVNI = LR.getVNInfoBefore(PEnd);
1679 // All predecessors must have a live-out value.
1681 report("Register not marked live out of predecessor", *PI, LR, Reg,
1683 errs() << "Valno #" << VNI->id << " live into BB#" << MFI->getNumber()
1684 << '@' << LiveInts->getMBBStartIdx(&*MFI) << ", not live before "
1689 // Only PHI-defs can take different predecessor values.
1690 if (!IsPHI && PVNI != VNI) {
1691 report("Different value live out of predecessor", *PI, LR, Reg,
1693 errs() << "Valno #" << PVNI->id << " live out of BB#"
1694 << (*PI)->getNumber() << '@' << PEnd << "\nValno #" << VNI->id
1695 << " live into BB#" << MFI->getNumber() << '@'
1696 << LiveInts->getMBBStartIdx(&*MFI) << '\n';
1699 if (&*MFI == EndMBB)
1705 void MachineVerifier::verifyLiveRange(const LiveRange &LR, unsigned Reg,
1706 LaneBitmask LaneMask) {
1707 for (const VNInfo *VNI : LR.valnos)
1708 verifyLiveRangeValue(LR, VNI, Reg, LaneMask);
1710 for (LiveRange::const_iterator I = LR.begin(), E = LR.end(); I != E; ++I)
1711 verifyLiveRangeSegment(LR, I, Reg, LaneMask);
1714 void MachineVerifier::verifyLiveInterval(const LiveInterval &LI) {
1715 unsigned Reg = LI.reg;
1716 assert(TargetRegisterInfo::isVirtualRegister(Reg));
1717 verifyLiveRange(LI, Reg);
1719 LaneBitmask Mask = 0;
1720 LaneBitmask MaxMask = MRI->getMaxLaneMaskForVReg(Reg);
1721 for (const LiveInterval::SubRange &SR : LI.subranges()) {
1722 if ((Mask & SR.LaneMask) != 0)
1723 report("Lane masks of sub ranges overlap in live interval", MF, LI);
1724 if ((SR.LaneMask & ~MaxMask) != 0)
1725 report("Subrange lanemask is invalid", MF, LI);
1727 report("Subrange must not be empty", MF, SR, LI.reg, SR.LaneMask);
1728 Mask |= SR.LaneMask;
1729 verifyLiveRange(SR, LI.reg, SR.LaneMask);
1731 report("A Subrange is not covered by the main range", MF, LI);
1734 // Check the LI only has one connected component.
1735 ConnectedVNInfoEqClasses ConEQ(*LiveInts);
1736 unsigned NumComp = ConEQ.Classify(&LI);
1738 report("Multiple connected components in live interval", MF, LI);
1739 for (unsigned comp = 0; comp != NumComp; ++comp) {
1740 errs() << comp << ": valnos";
1741 for (LiveInterval::const_vni_iterator I = LI.vni_begin(),
1742 E = LI.vni_end(); I!=E; ++I)
1743 if (comp == ConEQ.getEqClass(*I))
1744 errs() << ' ' << (*I)->id;
1751 // FrameSetup and FrameDestroy can have zero adjustment, so using a single
1752 // integer, we can't tell whether it is a FrameSetup or FrameDestroy if the
1754 // We use a bool plus an integer to capture the stack state.
1755 struct StackStateOfBB {
1756 StackStateOfBB() : EntryValue(0), ExitValue(0), EntryIsSetup(false),
1757 ExitIsSetup(false) { }
1758 StackStateOfBB(int EntryVal, int ExitVal, bool EntrySetup, bool ExitSetup) :
1759 EntryValue(EntryVal), ExitValue(ExitVal), EntryIsSetup(EntrySetup),
1760 ExitIsSetup(ExitSetup) { }
1761 // Can be negative, which means we are setting up a frame.
1769 /// Make sure on every path through the CFG, a FrameSetup <n> is always followed
1770 /// by a FrameDestroy <n>, stack adjustments are identical on all
1771 /// CFG edges to a merge point, and frame is destroyed at end of a return block.
1772 void MachineVerifier::verifyStackFrame() {
1773 unsigned FrameSetupOpcode = TII->getCallFrameSetupOpcode();
1774 unsigned FrameDestroyOpcode = TII->getCallFrameDestroyOpcode();
1776 SmallVector<StackStateOfBB, 8> SPState;
1777 SPState.resize(MF->getNumBlockIDs());
1778 SmallPtrSet<const MachineBasicBlock*, 8> Reachable;
1780 // Visit the MBBs in DFS order.
1781 for (df_ext_iterator<const MachineFunction*,
1782 SmallPtrSet<const MachineBasicBlock*, 8> >
1783 DFI = df_ext_begin(MF, Reachable), DFE = df_ext_end(MF, Reachable);
1784 DFI != DFE; ++DFI) {
1785 const MachineBasicBlock *MBB = *DFI;
1787 StackStateOfBB BBState;
1788 // Check the exit state of the DFS stack predecessor.
1789 if (DFI.getPathLength() >= 2) {
1790 const MachineBasicBlock *StackPred = DFI.getPath(DFI.getPathLength() - 2);
1791 assert(Reachable.count(StackPred) &&
1792 "DFS stack predecessor is already visited.\n");
1793 BBState.EntryValue = SPState[StackPred->getNumber()].ExitValue;
1794 BBState.EntryIsSetup = SPState[StackPred->getNumber()].ExitIsSetup;
1795 BBState.ExitValue = BBState.EntryValue;
1796 BBState.ExitIsSetup = BBState.EntryIsSetup;
1799 // Update stack state by checking contents of MBB.
1800 for (const auto &I : *MBB) {
1801 if (I.getOpcode() == FrameSetupOpcode) {
1802 // The first operand of a FrameOpcode should be i32.
1803 int Size = I.getOperand(0).getImm();
1805 "Value should be non-negative in FrameSetup and FrameDestroy.\n");
1807 if (BBState.ExitIsSetup)
1808 report("FrameSetup is after another FrameSetup", &I);
1809 BBState.ExitValue -= Size;
1810 BBState.ExitIsSetup = true;
1813 if (I.getOpcode() == FrameDestroyOpcode) {
1814 // The first operand of a FrameOpcode should be i32.
1815 int Size = I.getOperand(0).getImm();
1817 "Value should be non-negative in FrameSetup and FrameDestroy.\n");
1819 if (!BBState.ExitIsSetup)
1820 report("FrameDestroy is not after a FrameSetup", &I);
1821 int AbsSPAdj = BBState.ExitValue < 0 ? -BBState.ExitValue :
1823 if (BBState.ExitIsSetup && AbsSPAdj != Size) {
1824 report("FrameDestroy <n> is after FrameSetup <m>", &I);
1825 errs() << "FrameDestroy <" << Size << "> is after FrameSetup <"
1826 << AbsSPAdj << ">.\n";
1828 BBState.ExitValue += Size;
1829 BBState.ExitIsSetup = false;
1832 SPState[MBB->getNumber()] = BBState;
1834 // Make sure the exit state of any predecessor is consistent with the entry
1836 for (MachineBasicBlock::const_pred_iterator I = MBB->pred_begin(),
1837 E = MBB->pred_end(); I != E; ++I) {
1838 if (Reachable.count(*I) &&
1839 (SPState[(*I)->getNumber()].ExitValue != BBState.EntryValue ||
1840 SPState[(*I)->getNumber()].ExitIsSetup != BBState.EntryIsSetup)) {
1841 report("The exit stack state of a predecessor is inconsistent.", MBB);
1842 errs() << "Predecessor BB#" << (*I)->getNumber() << " has exit state ("
1843 << SPState[(*I)->getNumber()].ExitValue << ", "
1844 << SPState[(*I)->getNumber()].ExitIsSetup
1845 << "), while BB#" << MBB->getNumber() << " has entry state ("
1846 << BBState.EntryValue << ", " << BBState.EntryIsSetup << ").\n";
1850 // Make sure the entry state of any successor is consistent with the exit
1852 for (MachineBasicBlock::const_succ_iterator I = MBB->succ_begin(),
1853 E = MBB->succ_end(); I != E; ++I) {
1854 if (Reachable.count(*I) &&
1855 (SPState[(*I)->getNumber()].EntryValue != BBState.ExitValue ||
1856 SPState[(*I)->getNumber()].EntryIsSetup != BBState.ExitIsSetup)) {
1857 report("The entry stack state of a successor is inconsistent.", MBB);
1858 errs() << "Successor BB#" << (*I)->getNumber() << " has entry state ("
1859 << SPState[(*I)->getNumber()].EntryValue << ", "
1860 << SPState[(*I)->getNumber()].EntryIsSetup
1861 << "), while BB#" << MBB->getNumber() << " has exit state ("
1862 << BBState.ExitValue << ", " << BBState.ExitIsSetup << ").\n";
1866 // Make sure a basic block with return ends with zero stack adjustment.
1867 if (!MBB->empty() && MBB->back().isReturn()) {
1868 if (BBState.ExitIsSetup)
1869 report("A return block ends with a FrameSetup.", MBB);
1870 if (BBState.ExitValue)
1871 report("A return block ends with a nonzero stack adjustment.", MBB);