1 //===-- MachineVerifier.cpp - Machine Code Verifier -----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Pass to verify generated machine code. The following is checked:
12 // Operand counts: All explicit operands must be present.
14 // Register classes: All physical and virtual register operands must be
15 // compatible with the register class required by the instruction descriptor.
17 // Register live intervals: Registers must be defined only once, and must be
18 // defined before use.
20 // The machine code verifier is enabled from LLVMTargetMachine.cpp with the
21 // command-line option -verify-machineinstrs, or by defining the environment
22 // variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive
23 // the verifier errors.
24 //===----------------------------------------------------------------------===//
26 #include "llvm/CodeGen/Passes.h"
27 #include "llvm/ADT/DenseSet.h"
28 #include "llvm/ADT/DepthFirstIterator.h"
29 #include "llvm/ADT/SetOperations.h"
30 #include "llvm/ADT/SmallVector.h"
31 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
32 #include "llvm/CodeGen/LiveStackAnalysis.h"
33 #include "llvm/CodeGen/LiveVariables.h"
34 #include "llvm/CodeGen/MachineFrameInfo.h"
35 #include "llvm/CodeGen/MachineFunctionPass.h"
36 #include "llvm/CodeGen/MachineMemOperand.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/IR/BasicBlock.h"
39 #include "llvm/IR/InlineAsm.h"
40 #include "llvm/IR/Instructions.h"
41 #include "llvm/MC/MCAsmInfo.h"
42 #include "llvm/Support/Debug.h"
43 #include "llvm/Support/ErrorHandling.h"
44 #include "llvm/Support/FileSystem.h"
45 #include "llvm/Support/raw_ostream.h"
46 #include "llvm/Target/TargetInstrInfo.h"
47 #include "llvm/Target/TargetMachine.h"
48 #include "llvm/Target/TargetRegisterInfo.h"
49 #include "llvm/Target/TargetSubtargetInfo.h"
53 struct MachineVerifier {
55 MachineVerifier(Pass *pass, const char *b) :
60 bool runOnMachineFunction(MachineFunction &MF);
64 const MachineFunction *MF;
65 const TargetMachine *TM;
66 const TargetInstrInfo *TII;
67 const TargetRegisterInfo *TRI;
68 const MachineRegisterInfo *MRI;
72 typedef SmallVector<unsigned, 16> RegVector;
73 typedef SmallVector<const uint32_t*, 4> RegMaskVector;
74 typedef DenseSet<unsigned> RegSet;
75 typedef DenseMap<unsigned, const MachineInstr*> RegMap;
76 typedef SmallPtrSet<const MachineBasicBlock*, 8> BlockSet;
78 const MachineInstr *FirstTerminator;
79 BlockSet FunctionBlocks;
81 BitVector regsReserved;
83 RegVector regsDefined, regsDead, regsKilled;
84 RegMaskVector regMasks;
85 RegSet regsLiveInButUnused;
89 // Add Reg and any sub-registers to RV
90 void addRegWithSubRegs(RegVector &RV, unsigned Reg) {
92 if (TargetRegisterInfo::isPhysicalRegister(Reg))
93 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
94 RV.push_back(*SubRegs);
98 // Is this MBB reachable from the MF entry point?
101 // Vregs that must be live in because they are used without being
102 // defined. Map value is the user.
105 // Regs killed in MBB. They may be defined again, and will then be in both
106 // regsKilled and regsLiveOut.
109 // Regs defined in MBB and live out. Note that vregs passing through may
110 // be live out without being mentioned here.
113 // Vregs that pass through MBB untouched. This set is disjoint from
114 // regsKilled and regsLiveOut.
117 // Vregs that must pass through MBB because they are needed by a successor
118 // block. This set is disjoint from regsLiveOut.
119 RegSet vregsRequired;
121 // Set versions of block's predecessor and successor lists.
122 BlockSet Preds, Succs;
124 BBInfo() : reachable(false) {}
126 // Add register to vregsPassed if it belongs there. Return true if
128 bool addPassed(unsigned Reg) {
129 if (!TargetRegisterInfo::isVirtualRegister(Reg))
131 if (regsKilled.count(Reg) || regsLiveOut.count(Reg))
133 return vregsPassed.insert(Reg).second;
136 // Same for a full set.
137 bool addPassed(const RegSet &RS) {
138 bool changed = false;
139 for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
145 // Add register to vregsRequired if it belongs there. Return true if
147 bool addRequired(unsigned Reg) {
148 if (!TargetRegisterInfo::isVirtualRegister(Reg))
150 if (regsLiveOut.count(Reg))
152 return vregsRequired.insert(Reg).second;
155 // Same for a full set.
156 bool addRequired(const RegSet &RS) {
157 bool changed = false;
158 for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
164 // Same for a full map.
165 bool addRequired(const RegMap &RM) {
166 bool changed = false;
167 for (RegMap::const_iterator I = RM.begin(), E = RM.end(); I != E; ++I)
168 if (addRequired(I->first))
173 // Live-out registers are either in regsLiveOut or vregsPassed.
174 bool isLiveOut(unsigned Reg) const {
175 return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
179 // Extra register info per MBB.
180 DenseMap<const MachineBasicBlock*, BBInfo> MBBInfoMap;
182 bool isReserved(unsigned Reg) {
183 return Reg < regsReserved.size() && regsReserved.test(Reg);
186 bool isAllocatable(unsigned Reg) {
187 return Reg < TRI->getNumRegs() && MRI->isAllocatable(Reg);
190 // Analysis information if available
191 LiveVariables *LiveVars;
192 LiveIntervals *LiveInts;
193 LiveStacks *LiveStks;
194 SlotIndexes *Indexes;
196 void visitMachineFunctionBefore();
197 void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);
198 void visitMachineBundleBefore(const MachineInstr *MI);
199 void visitMachineInstrBefore(const MachineInstr *MI);
200 void visitMachineOperand(const MachineOperand *MO, unsigned MONum);
201 void visitMachineInstrAfter(const MachineInstr *MI);
202 void visitMachineBundleAfter(const MachineInstr *MI);
203 void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB);
204 void visitMachineFunctionAfter();
206 template <typename T> void report(const char *msg, ilist_iterator<T> I) {
209 void report(const char *msg, const MachineFunction *MF);
210 void report(const char *msg, const MachineBasicBlock *MBB);
211 void report(const char *msg, const MachineInstr *MI);
212 void report(const char *msg, const MachineOperand *MO, unsigned MONum);
213 void report(const char *msg, const MachineFunction *MF,
214 const LiveInterval &LI);
215 void report(const char *msg, const MachineBasicBlock *MBB,
216 const LiveInterval &LI);
217 void report(const char *msg, const MachineFunction *MF,
218 const LiveRange &LR, unsigned Reg, LaneBitmask LaneMask);
219 void report(const char *msg, const MachineBasicBlock *MBB,
220 const LiveRange &LR, unsigned Reg, LaneBitmask LaneMask);
222 void verifyInlineAsm(const MachineInstr *MI);
224 void checkLiveness(const MachineOperand *MO, unsigned MONum);
225 void markReachable(const MachineBasicBlock *MBB);
226 void calcRegsPassed();
227 void checkPHIOps(const MachineBasicBlock *MBB);
229 void calcRegsRequired();
230 void verifyLiveVariables();
231 void verifyLiveIntervals();
232 void verifyLiveInterval(const LiveInterval&);
233 void verifyLiveRangeValue(const LiveRange&, const VNInfo*, unsigned,
235 void verifyLiveRangeSegment(const LiveRange&,
236 const LiveRange::const_iterator I, unsigned,
238 void verifyLiveRange(const LiveRange&, unsigned, LaneBitmask LaneMask = 0);
240 void verifyStackFrame();
242 void verifySlotIndexes() const;
245 struct MachineVerifierPass : public MachineFunctionPass {
246 static char ID; // Pass ID, replacement for typeid
247 const std::string Banner;
249 MachineVerifierPass(const std::string &banner = nullptr)
250 : MachineFunctionPass(ID), Banner(banner) {
251 initializeMachineVerifierPassPass(*PassRegistry::getPassRegistry());
254 void getAnalysisUsage(AnalysisUsage &AU) const override {
255 AU.setPreservesAll();
256 MachineFunctionPass::getAnalysisUsage(AU);
259 bool runOnMachineFunction(MachineFunction &MF) override {
260 MF.verify(this, Banner.c_str());
267 char MachineVerifierPass::ID = 0;
268 INITIALIZE_PASS(MachineVerifierPass, "machineverifier",
269 "Verify generated machine code", false, false)
271 FunctionPass *llvm::createMachineVerifierPass(const std::string &Banner) {
272 return new MachineVerifierPass(Banner);
275 void MachineFunction::verify(Pass *p, const char *Banner) const {
276 MachineVerifier(p, Banner)
277 .runOnMachineFunction(const_cast<MachineFunction&>(*this));
280 void MachineVerifier::verifySlotIndexes() const {
281 if (Indexes == nullptr)
284 // Ensure the IdxMBB list is sorted by slot indexes.
286 for (SlotIndexes::MBBIndexIterator I = Indexes->MBBIndexBegin(),
287 E = Indexes->MBBIndexEnd(); I != E; ++I) {
288 assert(!Last.isValid() || I->first > Last);
293 bool MachineVerifier::runOnMachineFunction(MachineFunction &MF) {
297 TM = &MF.getTarget();
298 TII = MF.getSubtarget().getInstrInfo();
299 TRI = MF.getSubtarget().getRegisterInfo();
300 MRI = &MF.getRegInfo();
307 LiveInts = PASS->getAnalysisIfAvailable<LiveIntervals>();
308 // We don't want to verify LiveVariables if LiveIntervals is available.
310 LiveVars = PASS->getAnalysisIfAvailable<LiveVariables>();
311 LiveStks = PASS->getAnalysisIfAvailable<LiveStacks>();
312 Indexes = PASS->getAnalysisIfAvailable<SlotIndexes>();
317 visitMachineFunctionBefore();
318 for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end();
320 visitMachineBasicBlockBefore(&*MFI);
321 // Keep track of the current bundle header.
322 const MachineInstr *CurBundle = nullptr;
323 // Do we expect the next instruction to be part of the same bundle?
324 bool InBundle = false;
326 for (MachineBasicBlock::const_instr_iterator MBBI = MFI->instr_begin(),
327 MBBE = MFI->instr_end(); MBBI != MBBE; ++MBBI) {
328 if (MBBI->getParent() != &*MFI) {
329 report("Bad instruction parent pointer", MFI);
330 errs() << "Instruction: " << *MBBI;
334 // Check for consistent bundle flags.
335 if (InBundle && !MBBI->isBundledWithPred())
336 report("Missing BundledPred flag, "
337 "BundledSucc was set on predecessor",
339 if (!InBundle && MBBI->isBundledWithPred())
340 report("BundledPred flag is set, "
341 "but BundledSucc not set on predecessor",
344 // Is this a bundle header?
345 if (!MBBI->isInsideBundle()) {
347 visitMachineBundleAfter(CurBundle);
349 visitMachineBundleBefore(CurBundle);
350 } else if (!CurBundle)
351 report("No bundle header", MBBI);
352 visitMachineInstrBefore(&*MBBI);
353 for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) {
354 const MachineInstr &MI = *MBBI;
355 const MachineOperand &Op = MI.getOperand(I);
356 if (Op.getParent() != &MI) {
357 // Make sure to use correct addOperand / RemoveOperand / ChangeTo
358 // functions when replacing operands of a MachineInstr.
359 report("Instruction has operand with wrong parent set", &MI);
362 visitMachineOperand(&Op, I);
365 visitMachineInstrAfter(&*MBBI);
367 // Was this the last bundled instruction?
368 InBundle = MBBI->isBundledWithSucc();
371 visitMachineBundleAfter(CurBundle);
373 report("BundledSucc flag set on last instruction in block", &MFI->back());
374 visitMachineBasicBlockAfter(&*MFI);
376 visitMachineFunctionAfter();
379 report_fatal_error("Found "+Twine(foundErrors)+" machine code errors.");
387 regsLiveInButUnused.clear();
390 return false; // no changes
393 void MachineVerifier::report(const char *msg, const MachineFunction *MF) {
396 if (!foundErrors++) {
398 errs() << "# " << Banner << '\n';
399 MF->print(errs(), Indexes);
401 errs() << "*** Bad machine code: " << msg << " ***\n"
402 << "- function: " << MF->getName() << "\n";
405 void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB) {
407 report(msg, MBB->getParent());
408 errs() << "- basic block: BB#" << MBB->getNumber()
409 << ' ' << MBB->getName()
410 << " (" << (const void*)MBB << ')';
412 errs() << " [" << Indexes->getMBBStartIdx(MBB)
413 << ';' << Indexes->getMBBEndIdx(MBB) << ')';
417 void MachineVerifier::report(const char *msg, const MachineInstr *MI) {
419 report(msg, MI->getParent());
420 errs() << "- instruction: ";
421 if (Indexes && Indexes->hasIndex(MI))
422 errs() << Indexes->getInstructionIndex(MI) << '\t';
423 MI->print(errs(), TM);
426 void MachineVerifier::report(const char *msg,
427 const MachineOperand *MO, unsigned MONum) {
429 report(msg, MO->getParent());
430 errs() << "- operand " << MONum << ": ";
431 MO->print(errs(), TRI);
435 void MachineVerifier::report(const char *msg, const MachineFunction *MF,
436 const LiveInterval &LI) {
438 errs() << "- interval: " << LI << '\n';
441 void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB,
442 const LiveInterval &LI) {
444 errs() << "- interval: " << LI << '\n';
447 void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB,
448 const LiveRange &LR, unsigned Reg,
449 LaneBitmask LaneMask) {
451 errs() << "- liverange: " << LR << '\n';
452 errs() << "- register: " << PrintReg(Reg, TRI) << '\n';
454 errs() << "- lanemask: " << PrintLaneMask(LaneMask) << '\n';
457 void MachineVerifier::report(const char *msg, const MachineFunction *MF,
458 const LiveRange &LR, unsigned Reg,
459 LaneBitmask LaneMask) {
461 errs() << "- liverange: " << LR << '\n';
462 errs() << "- register: " << PrintReg(Reg, TRI) << '\n';
464 errs() << "- lanemask: " << PrintLaneMask(LaneMask) << '\n';
467 void MachineVerifier::markReachable(const MachineBasicBlock *MBB) {
468 BBInfo &MInfo = MBBInfoMap[MBB];
469 if (!MInfo.reachable) {
470 MInfo.reachable = true;
471 for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
472 SuE = MBB->succ_end(); SuI != SuE; ++SuI)
477 void MachineVerifier::visitMachineFunctionBefore() {
478 lastIndex = SlotIndex();
479 regsReserved = MRI->getReservedRegs();
481 // A sub-register of a reserved register is also reserved
482 for (int Reg = regsReserved.find_first(); Reg>=0;
483 Reg = regsReserved.find_next(Reg)) {
484 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
485 // FIXME: This should probably be:
486 // assert(regsReserved.test(*SubRegs) && "Non-reserved sub-register");
487 regsReserved.set(*SubRegs);
491 markReachable(&MF->front());
493 // Build a set of the basic blocks in the function.
494 FunctionBlocks.clear();
495 for (const auto &MBB : *MF) {
496 FunctionBlocks.insert(&MBB);
497 BBInfo &MInfo = MBBInfoMap[&MBB];
499 MInfo.Preds.insert(MBB.pred_begin(), MBB.pred_end());
500 if (MInfo.Preds.size() != MBB.pred_size())
501 report("MBB has duplicate entries in its predecessor list.", &MBB);
503 MInfo.Succs.insert(MBB.succ_begin(), MBB.succ_end());
504 if (MInfo.Succs.size() != MBB.succ_size())
505 report("MBB has duplicate entries in its successor list.", &MBB);
508 // Check that the register use lists are sane.
509 MRI->verifyUseLists();
514 // Does iterator point to a and b as the first two elements?
515 static bool matchPair(MachineBasicBlock::const_succ_iterator i,
516 const MachineBasicBlock *a, const MachineBasicBlock *b) {
525 MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
526 FirstTerminator = nullptr;
529 // If this block has allocatable physical registers live-in, check that
530 // it is an entry block or landing pad.
531 for (const auto &LI : MBB->liveins()) {
532 if (isAllocatable(LI.PhysReg) && !MBB->isEHPad() &&
533 MBB != MBB->getParent()->begin()) {
534 report("MBB has allocable live-in, but isn't entry or landing-pad.", MBB);
539 // Count the number of landing pad successors.
540 SmallPtrSet<MachineBasicBlock*, 4> LandingPadSuccs;
541 for (MachineBasicBlock::const_succ_iterator I = MBB->succ_begin(),
542 E = MBB->succ_end(); I != E; ++I) {
544 LandingPadSuccs.insert(*I);
545 if (!FunctionBlocks.count(*I))
546 report("MBB has successor that isn't part of the function.", MBB);
547 if (!MBBInfoMap[*I].Preds.count(MBB)) {
548 report("Inconsistent CFG", MBB);
549 errs() << "MBB is not in the predecessor list of the successor BB#"
550 << (*I)->getNumber() << ".\n";
554 // Check the predecessor list.
555 for (MachineBasicBlock::const_pred_iterator I = MBB->pred_begin(),
556 E = MBB->pred_end(); I != E; ++I) {
557 if (!FunctionBlocks.count(*I))
558 report("MBB has predecessor that isn't part of the function.", MBB);
559 if (!MBBInfoMap[*I].Succs.count(MBB)) {
560 report("Inconsistent CFG", MBB);
561 errs() << "MBB is not in the successor list of the predecessor BB#"
562 << (*I)->getNumber() << ".\n";
566 const MCAsmInfo *AsmInfo = TM->getMCAsmInfo();
567 const BasicBlock *BB = MBB->getBasicBlock();
568 if (LandingPadSuccs.size() > 1 &&
570 AsmInfo->getExceptionHandlingType() == ExceptionHandling::SjLj &&
571 BB && isa<SwitchInst>(BB->getTerminator())))
572 report("MBB has more than one landing pad successor", MBB);
574 // Call AnalyzeBranch. If it succeeds, there several more conditions to check.
575 MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
576 SmallVector<MachineOperand, 4> Cond;
577 if (!TII->AnalyzeBranch(*const_cast<MachineBasicBlock *>(MBB),
579 // Ok, AnalyzeBranch thinks it knows what's going on with this block. Let's
580 // check whether its answers match up with reality.
582 // Block falls through to its successor.
583 MachineFunction::const_iterator MBBI = MBB->getIterator();
585 if (MBBI == MF->end()) {
586 // It's possible that the block legitimately ends with a noreturn
587 // call or an unreachable, in which case it won't actually fall
588 // out the bottom of the function.
589 } else if (MBB->succ_size() == LandingPadSuccs.size()) {
590 // It's possible that the block legitimately ends with a noreturn
591 // call or an unreachable, in which case it won't actuall fall
593 } else if (MBB->succ_size() != 1+LandingPadSuccs.size()) {
594 report("MBB exits via unconditional fall-through but doesn't have "
595 "exactly one CFG successor!", MBB);
596 } else if (!MBB->isSuccessor(&*MBBI)) {
597 report("MBB exits via unconditional fall-through but its successor "
598 "differs from its CFG successor!", MBB);
600 if (!MBB->empty() && MBB->back().isBarrier() &&
601 !TII->isPredicated(&MBB->back())) {
602 report("MBB exits via unconditional fall-through but ends with a "
603 "barrier instruction!", MBB);
606 report("MBB exits via unconditional fall-through but has a condition!",
609 } else if (TBB && !FBB && Cond.empty()) {
610 // Block unconditionally branches somewhere.
611 // If the block has exactly one successor, that happens to be a
612 // landingpad, accept it as valid control flow.
613 if (MBB->succ_size() != 1+LandingPadSuccs.size() &&
614 (MBB->succ_size() != 1 || LandingPadSuccs.size() != 1 ||
615 *MBB->succ_begin() != *LandingPadSuccs.begin())) {
616 report("MBB exits via unconditional branch but doesn't have "
617 "exactly one CFG successor!", MBB);
618 } else if (!MBB->isSuccessor(TBB)) {
619 report("MBB exits via unconditional branch but the CFG "
620 "successor doesn't match the actual successor!", MBB);
623 report("MBB exits via unconditional branch but doesn't contain "
624 "any instructions!", MBB);
625 } else if (!MBB->back().isBarrier()) {
626 report("MBB exits via unconditional branch but doesn't end with a "
627 "barrier instruction!", MBB);
628 } else if (!MBB->back().isTerminator()) {
629 report("MBB exits via unconditional branch but the branch isn't a "
630 "terminator instruction!", MBB);
632 } else if (TBB && !FBB && !Cond.empty()) {
633 // Block conditionally branches somewhere, otherwise falls through.
634 MachineFunction::const_iterator MBBI = MBB->getIterator();
636 if (MBBI == MF->end()) {
637 report("MBB conditionally falls through out of function!", MBB);
638 } else if (MBB->succ_size() == 1) {
639 // A conditional branch with only one successor is weird, but allowed.
641 report("MBB exits via conditional branch/fall-through but only has "
642 "one CFG successor!", MBB);
643 else if (TBB != *MBB->succ_begin())
644 report("MBB exits via conditional branch/fall-through but the CFG "
645 "successor don't match the actual successor!", MBB);
646 } else if (MBB->succ_size() != 2) {
647 report("MBB exits via conditional branch/fall-through but doesn't have "
648 "exactly two CFG successors!", MBB);
649 } else if (!matchPair(MBB->succ_begin(), TBB, &*MBBI)) {
650 report("MBB exits via conditional branch/fall-through but the CFG "
651 "successors don't match the actual successors!", MBB);
654 report("MBB exits via conditional branch/fall-through but doesn't "
655 "contain any instructions!", MBB);
656 } else if (MBB->back().isBarrier()) {
657 report("MBB exits via conditional branch/fall-through but ends with a "
658 "barrier instruction!", MBB);
659 } else if (!MBB->back().isTerminator()) {
660 report("MBB exits via conditional branch/fall-through but the branch "
661 "isn't a terminator instruction!", MBB);
663 } else if (TBB && FBB) {
664 // Block conditionally branches somewhere, otherwise branches
666 if (MBB->succ_size() == 1) {
667 // A conditional branch with only one successor is weird, but allowed.
669 report("MBB exits via conditional branch/branch through but only has "
670 "one CFG successor!", MBB);
671 else if (TBB != *MBB->succ_begin())
672 report("MBB exits via conditional branch/branch through but the CFG "
673 "successor don't match the actual successor!", MBB);
674 } else if (MBB->succ_size() != 2) {
675 report("MBB exits via conditional branch/branch but doesn't have "
676 "exactly two CFG successors!", MBB);
677 } else if (!matchPair(MBB->succ_begin(), TBB, FBB)) {
678 report("MBB exits via conditional branch/branch but the CFG "
679 "successors don't match the actual successors!", MBB);
682 report("MBB exits via conditional branch/branch but doesn't "
683 "contain any instructions!", MBB);
684 } else if (!MBB->back().isBarrier()) {
685 report("MBB exits via conditional branch/branch but doesn't end with a "
686 "barrier instruction!", MBB);
687 } else if (!MBB->back().isTerminator()) {
688 report("MBB exits via conditional branch/branch but the branch "
689 "isn't a terminator instruction!", MBB);
692 report("MBB exits via conditinal branch/branch but there's no "
696 report("AnalyzeBranch returned invalid data!", MBB);
701 for (const auto &LI : MBB->liveins()) {
702 if (!TargetRegisterInfo::isPhysicalRegister(LI.PhysReg)) {
703 report("MBB live-in list contains non-physical register", MBB);
706 for (MCSubRegIterator SubRegs(LI.PhysReg, TRI, /*IncludeSelf=*/true);
707 SubRegs.isValid(); ++SubRegs)
708 regsLive.insert(*SubRegs);
710 regsLiveInButUnused = regsLive;
712 const MachineFrameInfo *MFI = MF->getFrameInfo();
713 assert(MFI && "Function has no frame info");
714 BitVector PR = MFI->getPristineRegs(*MF);
715 for (int I = PR.find_first(); I>0; I = PR.find_next(I)) {
716 for (MCSubRegIterator SubRegs(I, TRI, /*IncludeSelf=*/true);
717 SubRegs.isValid(); ++SubRegs)
718 regsLive.insert(*SubRegs);
725 lastIndex = Indexes->getMBBStartIdx(MBB);
728 // This function gets called for all bundle headers, including normal
729 // stand-alone unbundled instructions.
730 void MachineVerifier::visitMachineBundleBefore(const MachineInstr *MI) {
731 if (Indexes && Indexes->hasIndex(MI)) {
732 SlotIndex idx = Indexes->getInstructionIndex(MI);
733 if (!(idx > lastIndex)) {
734 report("Instruction index out of order", MI);
735 errs() << "Last instruction was at " << lastIndex << '\n';
740 // Ensure non-terminators don't follow terminators.
741 // Ignore predicated terminators formed by if conversion.
742 // FIXME: If conversion shouldn't need to violate this rule.
743 if (MI->isTerminator() && !TII->isPredicated(MI)) {
744 if (!FirstTerminator)
745 FirstTerminator = MI;
746 } else if (FirstTerminator) {
747 report("Non-terminator instruction after the first terminator", MI);
748 errs() << "First terminator was:\t" << *FirstTerminator;
752 // The operands on an INLINEASM instruction must follow a template.
753 // Verify that the flag operands make sense.
754 void MachineVerifier::verifyInlineAsm(const MachineInstr *MI) {
755 // The first two operands on INLINEASM are the asm string and global flags.
756 if (MI->getNumOperands() < 2) {
757 report("Too few operands on inline asm", MI);
760 if (!MI->getOperand(0).isSymbol())
761 report("Asm string must be an external symbol", MI);
762 if (!MI->getOperand(1).isImm())
763 report("Asm flags must be an immediate", MI);
764 // Allowed flags are Extra_HasSideEffects = 1, Extra_IsAlignStack = 2,
765 // Extra_AsmDialect = 4, Extra_MayLoad = 8, and Extra_MayStore = 16.
766 if (!isUInt<5>(MI->getOperand(1).getImm()))
767 report("Unknown asm flags", &MI->getOperand(1), 1);
769 static_assert(InlineAsm::MIOp_FirstOperand == 2, "Asm format changed");
771 unsigned OpNo = InlineAsm::MIOp_FirstOperand;
773 for (unsigned e = MI->getNumOperands(); OpNo < e; OpNo += NumOps) {
774 const MachineOperand &MO = MI->getOperand(OpNo);
775 // There may be implicit ops after the fixed operands.
778 NumOps = 1 + InlineAsm::getNumOperandRegisters(MO.getImm());
781 if (OpNo > MI->getNumOperands())
782 report("Missing operands in last group", MI);
784 // An optional MDNode follows the groups.
785 if (OpNo < MI->getNumOperands() && MI->getOperand(OpNo).isMetadata())
788 // All trailing operands must be implicit registers.
789 for (unsigned e = MI->getNumOperands(); OpNo < e; ++OpNo) {
790 const MachineOperand &MO = MI->getOperand(OpNo);
791 if (!MO.isReg() || !MO.isImplicit())
792 report("Expected implicit register after groups", &MO, OpNo);
796 void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
797 const MCInstrDesc &MCID = MI->getDesc();
798 if (MI->getNumOperands() < MCID.getNumOperands()) {
799 report("Too few operands", MI);
800 errs() << MCID.getNumOperands() << " operands expected, but "
801 << MI->getNumOperands() << " given.\n";
804 // Check the tied operands.
805 if (MI->isInlineAsm())
808 // Check the MachineMemOperands for basic consistency.
809 for (MachineInstr::mmo_iterator I = MI->memoperands_begin(),
810 E = MI->memoperands_end(); I != E; ++I) {
811 if ((*I)->isLoad() && !MI->mayLoad())
812 report("Missing mayLoad flag", MI);
813 if ((*I)->isStore() && !MI->mayStore())
814 report("Missing mayStore flag", MI);
817 // Debug values must not have a slot index.
818 // Other instructions must have one, unless they are inside a bundle.
820 bool mapped = !LiveInts->isNotInMIMap(MI);
821 if (MI->isDebugValue()) {
823 report("Debug instruction has a slot index", MI);
824 } else if (MI->isInsideBundle()) {
826 report("Instruction inside bundle has a slot index", MI);
829 report("Missing slot index", MI);
834 if (!TII->verifyInstruction(MI, ErrorInfo))
835 report(ErrorInfo.data(), MI);
839 MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
840 const MachineInstr *MI = MO->getParent();
841 const MCInstrDesc &MCID = MI->getDesc();
842 unsigned NumDefs = MCID.getNumDefs();
843 if (MCID.getOpcode() == TargetOpcode::PATCHPOINT)
844 NumDefs = (MONum == 0 && MO->isReg()) ? NumDefs : 0;
846 // The first MCID.NumDefs operands must be explicit register defines
847 if (MONum < NumDefs) {
848 const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
850 report("Explicit definition must be a register", MO, MONum);
851 else if (!MO->isDef() && !MCOI.isOptionalDef())
852 report("Explicit definition marked as use", MO, MONum);
853 else if (MO->isImplicit())
854 report("Explicit definition marked as implicit", MO, MONum);
855 } else if (MONum < MCID.getNumOperands()) {
856 const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
857 // Don't check if it's the last operand in a variadic instruction. See,
858 // e.g., LDM_RET in the arm back end.
860 !(MI->isVariadic() && MONum == MCID.getNumOperands()-1)) {
861 if (MO->isDef() && !MCOI.isOptionalDef())
862 report("Explicit operand marked as def", MO, MONum);
863 if (MO->isImplicit())
864 report("Explicit operand marked as implicit", MO, MONum);
867 int TiedTo = MCID.getOperandConstraint(MONum, MCOI::TIED_TO);
870 report("Tied use must be a register", MO, MONum);
871 else if (!MO->isTied())
872 report("Operand should be tied", MO, MONum);
873 else if (unsigned(TiedTo) != MI->findTiedOperandIdx(MONum))
874 report("Tied def doesn't match MCInstrDesc", MO, MONum);
875 } else if (MO->isReg() && MO->isTied())
876 report("Explicit operand should not be tied", MO, MONum);
878 // ARM adds %reg0 operands to indicate predicates. We'll allow that.
879 if (MO->isReg() && !MO->isImplicit() && !MI->isVariadic() && MO->getReg())
880 report("Extra explicit operand on non-variadic instruction", MO, MONum);
883 switch (MO->getType()) {
884 case MachineOperand::MO_Register: {
885 const unsigned Reg = MO->getReg();
888 if (MRI->tracksLiveness() && !MI->isDebugValue())
889 checkLiveness(MO, MONum);
891 // Verify the consistency of tied operands.
893 unsigned OtherIdx = MI->findTiedOperandIdx(MONum);
894 const MachineOperand &OtherMO = MI->getOperand(OtherIdx);
895 if (!OtherMO.isReg())
896 report("Must be tied to a register", MO, MONum);
897 if (!OtherMO.isTied())
898 report("Missing tie flags on tied operand", MO, MONum);
899 if (MI->findTiedOperandIdx(OtherIdx) != MONum)
900 report("Inconsistent tie links", MO, MONum);
901 if (MONum < MCID.getNumDefs()) {
902 if (OtherIdx < MCID.getNumOperands()) {
903 if (-1 == MCID.getOperandConstraint(OtherIdx, MCOI::TIED_TO))
904 report("Explicit def tied to explicit use without tie constraint",
907 if (!OtherMO.isImplicit())
908 report("Explicit def should be tied to implicit use", MO, MONum);
913 // Verify two-address constraints after leaving SSA form.
915 if (!MRI->isSSA() && MO->isUse() &&
916 MI->isRegTiedToDefOperand(MONum, &DefIdx) &&
917 Reg != MI->getOperand(DefIdx).getReg())
918 report("Two-address instruction operands must be identical", MO, MONum);
920 // Check register classes.
921 if (MONum < MCID.getNumOperands() && !MO->isImplicit()) {
922 unsigned SubIdx = MO->getSubReg();
924 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
926 report("Illegal subregister index for physical register", MO, MONum);
929 if (const TargetRegisterClass *DRC =
930 TII->getRegClass(MCID, MONum, TRI, *MF)) {
931 if (!DRC->contains(Reg)) {
932 report("Illegal physical register for instruction", MO, MONum);
933 errs() << TRI->getName(Reg) << " is not a "
934 << TRI->getRegClassName(DRC) << " register.\n";
939 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
941 const TargetRegisterClass *SRC =
942 TRI->getSubClassWithSubReg(RC, SubIdx);
944 report("Invalid subregister index for virtual register", MO, MONum);
945 errs() << "Register class " << TRI->getRegClassName(RC)
946 << " does not support subreg index " << SubIdx << "\n";
950 report("Invalid register class for subregister index", MO, MONum);
951 errs() << "Register class " << TRI->getRegClassName(RC)
952 << " does not fully support subreg index " << SubIdx << "\n";
956 if (const TargetRegisterClass *DRC =
957 TII->getRegClass(MCID, MONum, TRI, *MF)) {
959 const TargetRegisterClass *SuperRC =
960 TRI->getLargestLegalSuperClass(RC, *MF);
962 report("No largest legal super class exists.", MO, MONum);
965 DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx);
967 report("No matching super-reg register class.", MO, MONum);
971 if (!RC->hasSuperClassEq(DRC)) {
972 report("Illegal virtual register for instruction", MO, MONum);
973 errs() << "Expected a " << TRI->getRegClassName(DRC)
974 << " register, but got a " << TRI->getRegClassName(RC)
983 case MachineOperand::MO_RegisterMask:
984 regMasks.push_back(MO->getRegMask());
987 case MachineOperand::MO_MachineBasicBlock:
988 if (MI->isPHI() && !MO->getMBB()->isSuccessor(MI->getParent()))
989 report("PHI operand is not in the CFG", MO, MONum);
992 case MachineOperand::MO_FrameIndex:
993 if (LiveStks && LiveStks->hasInterval(MO->getIndex()) &&
994 LiveInts && !LiveInts->isNotInMIMap(MI)) {
995 LiveInterval &LI = LiveStks->getInterval(MO->getIndex());
996 SlotIndex Idx = LiveInts->getInstructionIndex(MI);
997 if (MI->mayLoad() && !LI.liveAt(Idx.getRegSlot(true))) {
998 report("Instruction loads from dead spill slot", MO, MONum);
999 errs() << "Live stack: " << LI << '\n';
1001 if (MI->mayStore() && !LI.liveAt(Idx.getRegSlot())) {
1002 report("Instruction stores to dead spill slot", MO, MONum);
1003 errs() << "Live stack: " << LI << '\n';
1013 void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) {
1014 const MachineInstr *MI = MO->getParent();
1015 const unsigned Reg = MO->getReg();
1017 // Both use and def operands can read a register.
1018 if (MO->readsReg()) {
1019 regsLiveInButUnused.erase(Reg);
1022 addRegWithSubRegs(regsKilled, Reg);
1024 // Check that LiveVars knows this kill.
1025 if (LiveVars && TargetRegisterInfo::isVirtualRegister(Reg) &&
1027 LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
1028 if (std::find(VI.Kills.begin(), VI.Kills.end(), MI) == VI.Kills.end())
1029 report("Kill missing from LiveVariables", MO, MONum);
1032 // Check LiveInts liveness and kill.
1033 if (LiveInts && !LiveInts->isNotInMIMap(MI)) {
1034 SlotIndex UseIdx = LiveInts->getInstructionIndex(MI);
1035 // Check the cached regunit intervals.
1036 if (TargetRegisterInfo::isPhysicalRegister(Reg) && !isReserved(Reg)) {
1037 for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units) {
1038 if (const LiveRange *LR = LiveInts->getCachedRegUnit(*Units)) {
1039 LiveQueryResult LRQ = LR->Query(UseIdx);
1040 if (!LRQ.valueIn()) {
1041 report("No live segment at use", MO, MONum);
1042 errs() << UseIdx << " is not live in " << PrintRegUnit(*Units, TRI)
1043 << ' ' << *LR << '\n';
1045 if (MO->isKill() && !LRQ.isKill()) {
1046 report("Live range continues after kill flag", MO, MONum);
1047 errs() << PrintRegUnit(*Units, TRI) << ' ' << *LR << '\n';
1053 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
1054 if (LiveInts->hasInterval(Reg)) {
1055 // This is a virtual register interval.
1056 const LiveInterval &LI = LiveInts->getInterval(Reg);
1057 LiveQueryResult LRQ = LI.Query(UseIdx);
1058 if (!LRQ.valueIn()) {
1059 report("No live segment at use", MO, MONum);
1060 errs() << UseIdx << " is not live in " << LI << '\n';
1062 // Check for extra kill flags.
1063 // Note that we allow missing kill flags for now.
1064 if (MO->isKill() && !LRQ.isKill()) {
1065 report("Live range continues after kill flag", MO, MONum);
1066 errs() << "Live range: " << LI << '\n';
1069 report("Virtual register has no live interval", MO, MONum);
1074 // Use of a dead register.
1075 if (!regsLive.count(Reg)) {
1076 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
1077 // Reserved registers may be used even when 'dead'.
1078 bool Bad = !isReserved(Reg);
1079 // We are fine if just any subregister has a defined value.
1081 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid();
1083 if (regsLive.count(*SubRegs)) {
1089 // If there is an additional implicit-use of a super register we stop
1090 // here. By definition we are fine if the super register is not
1091 // (completely) dead, if the complete super register is dead we will
1092 // get a report for its operand.
1094 for (const MachineOperand &MOP : MI->uses()) {
1097 if (!MOP.isImplicit())
1099 for (MCSubRegIterator SubRegs(MOP.getReg(), TRI); SubRegs.isValid();
1101 if (*SubRegs == Reg) {
1109 report("Using an undefined physical register", MO, MONum);
1110 } else if (MRI->def_empty(Reg)) {
1111 report("Reading virtual register without a def", MO, MONum);
1113 BBInfo &MInfo = MBBInfoMap[MI->getParent()];
1114 // We don't know which virtual registers are live in, so only complain
1115 // if vreg was killed in this MBB. Otherwise keep track of vregs that
1116 // must be live in. PHI instructions are handled separately.
1117 if (MInfo.regsKilled.count(Reg))
1118 report("Using a killed virtual register", MO, MONum);
1119 else if (!MI->isPHI())
1120 MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));
1126 // Register defined.
1127 // TODO: verify that earlyclobber ops are not used.
1129 addRegWithSubRegs(regsDead, Reg);
1131 addRegWithSubRegs(regsDefined, Reg);
1134 if (MRI->isSSA() && TargetRegisterInfo::isVirtualRegister(Reg) &&
1135 std::next(MRI->def_begin(Reg)) != MRI->def_end())
1136 report("Multiple virtual register defs in SSA form", MO, MONum);
1138 // Check LiveInts for a live segment, but only for virtual registers.
1139 if (LiveInts && TargetRegisterInfo::isVirtualRegister(Reg) &&
1140 !LiveInts->isNotInMIMap(MI)) {
1141 SlotIndex DefIdx = LiveInts->getInstructionIndex(MI);
1142 DefIdx = DefIdx.getRegSlot(MO->isEarlyClobber());
1143 if (LiveInts->hasInterval(Reg)) {
1144 const LiveInterval &LI = LiveInts->getInterval(Reg);
1145 if (const VNInfo *VNI = LI.getVNInfoAt(DefIdx)) {
1146 assert(VNI && "NULL valno is not allowed");
1147 if (VNI->def != DefIdx) {
1148 report("Inconsistent valno->def", MO, MONum);
1149 errs() << "Valno " << VNI->id << " is not defined at "
1150 << DefIdx << " in " << LI << '\n';
1153 report("No live segment at def", MO, MONum);
1154 errs() << DefIdx << " is not live in " << LI << '\n';
1156 // Check that, if the dead def flag is present, LiveInts agree.
1158 LiveQueryResult LRQ = LI.Query(DefIdx);
1159 if (!LRQ.isDeadDef()) {
1160 report("Live range continues after dead def flag", MO, MONum);
1161 errs() << "Live range: " << LI << '\n';
1165 report("Virtual register has no Live interval", MO, MONum);
1171 void MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI) {
1174 // This function gets called after visiting all instructions in a bundle. The
1175 // argument points to the bundle header.
1176 // Normal stand-alone instructions are also considered 'bundles', and this
1177 // function is called for all of them.
1178 void MachineVerifier::visitMachineBundleAfter(const MachineInstr *MI) {
1179 BBInfo &MInfo = MBBInfoMap[MI->getParent()];
1180 set_union(MInfo.regsKilled, regsKilled);
1181 set_subtract(regsLive, regsKilled); regsKilled.clear();
1182 // Kill any masked registers.
1183 while (!regMasks.empty()) {
1184 const uint32_t *Mask = regMasks.pop_back_val();
1185 for (RegSet::iterator I = regsLive.begin(), E = regsLive.end(); I != E; ++I)
1186 if (TargetRegisterInfo::isPhysicalRegister(*I) &&
1187 MachineOperand::clobbersPhysReg(Mask, *I))
1188 regsDead.push_back(*I);
1190 set_subtract(regsLive, regsDead); regsDead.clear();
1191 set_union(regsLive, regsDefined); regsDefined.clear();
1195 MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB) {
1196 MBBInfoMap[MBB].regsLiveOut = regsLive;
1200 SlotIndex stop = Indexes->getMBBEndIdx(MBB);
1201 if (!(stop > lastIndex)) {
1202 report("Block ends before last instruction index", MBB);
1203 errs() << "Block ends at " << stop
1204 << " last instruction was at " << lastIndex << '\n';
1210 // Calculate the largest possible vregsPassed sets. These are the registers that
1211 // can pass through an MBB live, but may not be live every time. It is assumed
1212 // that all vregsPassed sets are empty before the call.
1213 void MachineVerifier::calcRegsPassed() {
1214 // First push live-out regs to successors' vregsPassed. Remember the MBBs that
1215 // have any vregsPassed.
1216 SmallPtrSet<const MachineBasicBlock*, 8> todo;
1217 for (const auto &MBB : *MF) {
1218 BBInfo &MInfo = MBBInfoMap[&MBB];
1219 if (!MInfo.reachable)
1221 for (MachineBasicBlock::const_succ_iterator SuI = MBB.succ_begin(),
1222 SuE = MBB.succ_end(); SuI != SuE; ++SuI) {
1223 BBInfo &SInfo = MBBInfoMap[*SuI];
1224 if (SInfo.addPassed(MInfo.regsLiveOut))
1229 // Iteratively push vregsPassed to successors. This will converge to the same
1230 // final state regardless of DenseSet iteration order.
1231 while (!todo.empty()) {
1232 const MachineBasicBlock *MBB = *todo.begin();
1234 BBInfo &MInfo = MBBInfoMap[MBB];
1235 for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
1236 SuE = MBB->succ_end(); SuI != SuE; ++SuI) {
1239 BBInfo &SInfo = MBBInfoMap[*SuI];
1240 if (SInfo.addPassed(MInfo.vregsPassed))
1246 // Calculate the set of virtual registers that must be passed through each basic
1247 // block in order to satisfy the requirements of successor blocks. This is very
1248 // similar to calcRegsPassed, only backwards.
1249 void MachineVerifier::calcRegsRequired() {
1250 // First push live-in regs to predecessors' vregsRequired.
1251 SmallPtrSet<const MachineBasicBlock*, 8> todo;
1252 for (const auto &MBB : *MF) {
1253 BBInfo &MInfo = MBBInfoMap[&MBB];
1254 for (MachineBasicBlock::const_pred_iterator PrI = MBB.pred_begin(),
1255 PrE = MBB.pred_end(); PrI != PrE; ++PrI) {
1256 BBInfo &PInfo = MBBInfoMap[*PrI];
1257 if (PInfo.addRequired(MInfo.vregsLiveIn))
1262 // Iteratively push vregsRequired to predecessors. This will converge to the
1263 // same final state regardless of DenseSet iteration order.
1264 while (!todo.empty()) {
1265 const MachineBasicBlock *MBB = *todo.begin();
1267 BBInfo &MInfo = MBBInfoMap[MBB];
1268 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
1269 PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
1272 BBInfo &SInfo = MBBInfoMap[*PrI];
1273 if (SInfo.addRequired(MInfo.vregsRequired))
1279 // Check PHI instructions at the beginning of MBB. It is assumed that
1280 // calcRegsPassed has been run so BBInfo::isLiveOut is valid.
1281 void MachineVerifier::checkPHIOps(const MachineBasicBlock *MBB) {
1282 SmallPtrSet<const MachineBasicBlock*, 8> seen;
1283 for (const auto &BBI : *MBB) {
1288 for (unsigned i = 1, e = BBI.getNumOperands(); i != e; i += 2) {
1289 unsigned Reg = BBI.getOperand(i).getReg();
1290 const MachineBasicBlock *Pre = BBI.getOperand(i + 1).getMBB();
1291 if (!Pre->isSuccessor(MBB))
1294 BBInfo &PrInfo = MBBInfoMap[Pre];
1295 if (PrInfo.reachable && !PrInfo.isLiveOut(Reg))
1296 report("PHI operand is not live-out from predecessor",
1297 &BBI.getOperand(i), i);
1300 // Did we see all predecessors?
1301 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
1302 PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
1303 if (!seen.count(*PrI)) {
1304 report("Missing PHI operand", &BBI);
1305 errs() << "BB#" << (*PrI)->getNumber()
1306 << " is a predecessor according to the CFG.\n";
1312 void MachineVerifier::visitMachineFunctionAfter() {
1315 for (const auto &MBB : *MF) {
1316 BBInfo &MInfo = MBBInfoMap[&MBB];
1318 // Skip unreachable MBBs.
1319 if (!MInfo.reachable)
1325 // Now check liveness info if available
1328 // Check for killed virtual registers that should be live out.
1329 for (const auto &MBB : *MF) {
1330 BBInfo &MInfo = MBBInfoMap[&MBB];
1331 for (RegSet::iterator
1332 I = MInfo.vregsRequired.begin(), E = MInfo.vregsRequired.end(); I != E;
1334 if (MInfo.regsKilled.count(*I)) {
1335 report("Virtual register killed in block, but needed live out.", &MBB);
1336 errs() << "Virtual register " << PrintReg(*I)
1337 << " is used after the block.\n";
1342 BBInfo &MInfo = MBBInfoMap[&MF->front()];
1343 for (RegSet::iterator
1344 I = MInfo.vregsRequired.begin(), E = MInfo.vregsRequired.end(); I != E;
1346 report("Virtual register def doesn't dominate all uses.",
1347 MRI->getVRegDef(*I));
1351 verifyLiveVariables();
1353 verifyLiveIntervals();
1356 void MachineVerifier::verifyLiveVariables() {
1357 assert(LiveVars && "Don't call verifyLiveVariables without LiveVars");
1358 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
1359 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
1360 LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
1361 for (const auto &MBB : *MF) {
1362 BBInfo &MInfo = MBBInfoMap[&MBB];
1364 // Our vregsRequired should be identical to LiveVariables' AliveBlocks
1365 if (MInfo.vregsRequired.count(Reg)) {
1366 if (!VI.AliveBlocks.test(MBB.getNumber())) {
1367 report("LiveVariables: Block missing from AliveBlocks", &MBB);
1368 errs() << "Virtual register " << PrintReg(Reg)
1369 << " must be live through the block.\n";
1372 if (VI.AliveBlocks.test(MBB.getNumber())) {
1373 report("LiveVariables: Block should not be in AliveBlocks", &MBB);
1374 errs() << "Virtual register " << PrintReg(Reg)
1375 << " is not needed live through the block.\n";
1382 void MachineVerifier::verifyLiveIntervals() {
1383 assert(LiveInts && "Don't call verifyLiveIntervals without LiveInts");
1384 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
1385 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
1387 // Spilling and splitting may leave unused registers around. Skip them.
1388 if (MRI->reg_nodbg_empty(Reg))
1391 if (!LiveInts->hasInterval(Reg)) {
1392 report("Missing live interval for virtual register", MF);
1393 errs() << PrintReg(Reg, TRI) << " still has defs or uses\n";
1397 const LiveInterval &LI = LiveInts->getInterval(Reg);
1398 assert(Reg == LI.reg && "Invalid reg to interval mapping");
1399 verifyLiveInterval(LI);
1402 // Verify all the cached regunit intervals.
1403 for (unsigned i = 0, e = TRI->getNumRegUnits(); i != e; ++i)
1404 if (const LiveRange *LR = LiveInts->getCachedRegUnit(i))
1405 verifyLiveRange(*LR, i);
1408 void MachineVerifier::verifyLiveRangeValue(const LiveRange &LR,
1409 const VNInfo *VNI, unsigned Reg,
1410 LaneBitmask LaneMask) {
1411 if (VNI->isUnused())
1414 const VNInfo *DefVNI = LR.getVNInfoAt(VNI->def);
1417 report("Valno not live at def and not marked unused", MF, LR, Reg,
1419 errs() << "Valno #" << VNI->id << '\n';
1423 if (DefVNI != VNI) {
1424 report("Live segment at def has different valno", MF, LR, Reg, LaneMask);
1425 errs() << "Valno #" << VNI->id << " is defined at " << VNI->def
1426 << " where valno #" << DefVNI->id << " is live\n";
1430 const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(VNI->def);
1432 report("Invalid definition index", MF, LR, Reg, LaneMask);
1433 errs() << "Valno #" << VNI->id << " is defined at " << VNI->def
1434 << " in " << LR << '\n';
1438 if (VNI->isPHIDef()) {
1439 if (VNI->def != LiveInts->getMBBStartIdx(MBB)) {
1440 report("PHIDef value is not defined at MBB start", MBB, LR, Reg,
1442 errs() << "Valno #" << VNI->id << " is defined at " << VNI->def
1443 << ", not at the beginning of BB#" << MBB->getNumber() << '\n';
1449 const MachineInstr *MI = LiveInts->getInstructionFromIndex(VNI->def);
1451 report("No instruction at def index", MBB, LR, Reg, LaneMask);
1452 errs() << "Valno #" << VNI->id << " is defined at " << VNI->def << '\n';
1457 bool hasDef = false;
1458 bool isEarlyClobber = false;
1459 for (ConstMIBundleOperands MOI(MI); MOI.isValid(); ++MOI) {
1460 if (!MOI->isReg() || !MOI->isDef())
1462 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
1463 if (MOI->getReg() != Reg)
1466 if (!TargetRegisterInfo::isPhysicalRegister(MOI->getReg()) ||
1467 !TRI->hasRegUnit(MOI->getReg(), Reg))
1470 if (LaneMask != 0 &&
1471 (TRI->getSubRegIndexLaneMask(MOI->getSubReg()) & LaneMask) == 0)
1474 if (MOI->isEarlyClobber())
1475 isEarlyClobber = true;
1479 report("Defining instruction does not modify register", MI);
1480 errs() << "Valno #" << VNI->id << " in " << LR << '\n';
1483 // Early clobber defs begin at USE slots, but other defs must begin at
1485 if (isEarlyClobber) {
1486 if (!VNI->def.isEarlyClobber()) {
1487 report("Early clobber def must be at an early-clobber slot", MBB, LR,
1489 errs() << "Valno #" << VNI->id << " is defined at " << VNI->def << '\n';
1491 } else if (!VNI->def.isRegister()) {
1492 report("Non-PHI, non-early clobber def must be at a register slot",
1493 MBB, LR, Reg, LaneMask);
1494 errs() << "Valno #" << VNI->id << " is defined at " << VNI->def << '\n';
1499 void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR,
1500 const LiveRange::const_iterator I,
1501 unsigned Reg, LaneBitmask LaneMask)
1503 const LiveRange::Segment &S = *I;
1504 const VNInfo *VNI = S.valno;
1505 assert(VNI && "Live segment has no valno");
1507 if (VNI->id >= LR.getNumValNums() || VNI != LR.getValNumInfo(VNI->id)) {
1508 report("Foreign valno in live segment", MF, LR, Reg, LaneMask);
1509 errs() << S << " has a bad valno\n";
1512 if (VNI->isUnused()) {
1513 report("Live segment valno is marked unused", MF, LR, Reg, LaneMask);
1514 errs() << S << '\n';
1517 const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(S.start);
1519 report("Bad start of live segment, no basic block", MF, LR, Reg, LaneMask);
1520 errs() << S << '\n';
1523 SlotIndex MBBStartIdx = LiveInts->getMBBStartIdx(MBB);
1524 if (S.start != MBBStartIdx && S.start != VNI->def) {
1525 report("Live segment must begin at MBB entry or valno def", MBB, LR, Reg,
1527 errs() << S << '\n';
1530 const MachineBasicBlock *EndMBB =
1531 LiveInts->getMBBFromIndex(S.end.getPrevSlot());
1533 report("Bad end of live segment, no basic block", MF, LR, Reg, LaneMask);
1534 errs() << S << '\n';
1538 // No more checks for live-out segments.
1539 if (S.end == LiveInts->getMBBEndIdx(EndMBB))
1542 // RegUnit intervals are allowed dead phis.
1543 if (!TargetRegisterInfo::isVirtualRegister(Reg) && VNI->isPHIDef() &&
1544 S.start == VNI->def && S.end == VNI->def.getDeadSlot())
1547 // The live segment is ending inside EndMBB
1548 const MachineInstr *MI =
1549 LiveInts->getInstructionFromIndex(S.end.getPrevSlot());
1551 report("Live segment doesn't end at a valid instruction", EndMBB, LR, Reg,
1553 errs() << S << '\n';
1557 // The block slot must refer to a basic block boundary.
1558 if (S.end.isBlock()) {
1559 report("Live segment ends at B slot of an instruction", EndMBB, LR, Reg,
1561 errs() << S << '\n';
1564 if (S.end.isDead()) {
1565 // Segment ends on the dead slot.
1566 // That means there must be a dead def.
1567 if (!SlotIndex::isSameInstr(S.start, S.end)) {
1568 report("Live segment ending at dead slot spans instructions", EndMBB, LR,
1570 errs() << S << '\n';
1574 // A live segment can only end at an early-clobber slot if it is being
1575 // redefined by an early-clobber def.
1576 if (S.end.isEarlyClobber()) {
1577 if (I+1 == LR.end() || (I+1)->start != S.end) {
1578 report("Live segment ending at early clobber slot must be "
1579 "redefined by an EC def in the same instruction", EndMBB, LR, Reg,
1581 errs() << S << '\n';
1585 // The following checks only apply to virtual registers. Physreg liveness
1586 // is too weird to check.
1587 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
1588 // A live segment can end with either a redefinition, a kill flag on a
1589 // use, or a dead flag on a def.
1590 bool hasRead = false;
1591 bool hasSubRegDef = false;
1592 for (ConstMIBundleOperands MOI(MI); MOI.isValid(); ++MOI) {
1593 if (!MOI->isReg() || MOI->getReg() != Reg)
1595 if (LaneMask != 0 &&
1596 (LaneMask & TRI->getSubRegIndexLaneMask(MOI->getSubReg())) == 0)
1598 if (MOI->isDef() && MOI->getSubReg() != 0)
1599 hasSubRegDef = true;
1600 if (MOI->readsReg())
1603 if (!S.end.isDead()) {
1605 // When tracking subregister liveness, the main range must start new
1606 // values on partial register writes, even if there is no read.
1607 if (!MRI->shouldTrackSubRegLiveness(Reg) || LaneMask != 0 ||
1609 report("Instruction ending live segment doesn't read the register",
1611 errs() << S << " in " << LR << '\n';
1617 // Now check all the basic blocks in this live segment.
1618 MachineFunction::const_iterator MFI = MBB->getIterator();
1619 // Is this live segment the beginning of a non-PHIDef VN?
1620 if (S.start == VNI->def && !VNI->isPHIDef()) {
1621 // Not live-in to any blocks.
1628 assert(LiveInts->isLiveInToMBB(LR, &*MFI));
1629 // We don't know how to track physregs into a landing pad.
1630 if (!TargetRegisterInfo::isVirtualRegister(Reg) &&
1632 if (&*MFI == EndMBB)
1638 // Is VNI a PHI-def in the current block?
1639 bool IsPHI = VNI->isPHIDef() &&
1640 VNI->def == LiveInts->getMBBStartIdx(&*MFI);
1642 // Check that VNI is live-out of all predecessors.
1643 for (MachineBasicBlock::const_pred_iterator PI = MFI->pred_begin(),
1644 PE = MFI->pred_end(); PI != PE; ++PI) {
1645 SlotIndex PEnd = LiveInts->getMBBEndIdx(*PI);
1646 const VNInfo *PVNI = LR.getVNInfoBefore(PEnd);
1648 // All predecessors must have a live-out value.
1650 report("Register not marked live out of predecessor", *PI, LR, Reg,
1652 errs() << "Valno #" << VNI->id << " live into BB#" << MFI->getNumber()
1653 << '@' << LiveInts->getMBBStartIdx(&*MFI) << ", not live before "
1658 // Only PHI-defs can take different predecessor values.
1659 if (!IsPHI && PVNI != VNI) {
1660 report("Different value live out of predecessor", *PI, LR, Reg,
1662 errs() << "Valno #" << PVNI->id << " live out of BB#"
1663 << (*PI)->getNumber() << '@' << PEnd << "\nValno #" << VNI->id
1664 << " live into BB#" << MFI->getNumber() << '@'
1665 << LiveInts->getMBBStartIdx(&*MFI) << '\n';
1668 if (&*MFI == EndMBB)
1674 void MachineVerifier::verifyLiveRange(const LiveRange &LR, unsigned Reg,
1675 LaneBitmask LaneMask) {
1676 for (const VNInfo *VNI : LR.valnos)
1677 verifyLiveRangeValue(LR, VNI, Reg, LaneMask);
1679 for (LiveRange::const_iterator I = LR.begin(), E = LR.end(); I != E; ++I)
1680 verifyLiveRangeSegment(LR, I, Reg, LaneMask);
1683 void MachineVerifier::verifyLiveInterval(const LiveInterval &LI) {
1684 unsigned Reg = LI.reg;
1685 assert(TargetRegisterInfo::isVirtualRegister(Reg));
1686 verifyLiveRange(LI, Reg);
1688 LaneBitmask Mask = 0;
1689 LaneBitmask MaxMask = MRI->getMaxLaneMaskForVReg(Reg);
1690 for (const LiveInterval::SubRange &SR : LI.subranges()) {
1691 if ((Mask & SR.LaneMask) != 0)
1692 report("Lane masks of sub ranges overlap in live interval", MF, LI);
1693 if ((SR.LaneMask & ~MaxMask) != 0)
1694 report("Subrange lanemask is invalid", MF, LI);
1696 report("Subrange must not be empty", MF, SR, LI.reg, SR.LaneMask);
1697 Mask |= SR.LaneMask;
1698 verifyLiveRange(SR, LI.reg, SR.LaneMask);
1700 report("A Subrange is not covered by the main range", MF, LI);
1703 // Check the LI only has one connected component.
1704 ConnectedVNInfoEqClasses ConEQ(*LiveInts);
1705 unsigned NumComp = ConEQ.Classify(&LI);
1707 report("Multiple connected components in live interval", MF, LI);
1708 for (unsigned comp = 0; comp != NumComp; ++comp) {
1709 errs() << comp << ": valnos";
1710 for (LiveInterval::const_vni_iterator I = LI.vni_begin(),
1711 E = LI.vni_end(); I!=E; ++I)
1712 if (comp == ConEQ.getEqClass(*I))
1713 errs() << ' ' << (*I)->id;
1720 // FrameSetup and FrameDestroy can have zero adjustment, so using a single
1721 // integer, we can't tell whether it is a FrameSetup or FrameDestroy if the
1723 // We use a bool plus an integer to capture the stack state.
1724 struct StackStateOfBB {
1725 StackStateOfBB() : EntryValue(0), ExitValue(0), EntryIsSetup(false),
1726 ExitIsSetup(false) { }
1727 StackStateOfBB(int EntryVal, int ExitVal, bool EntrySetup, bool ExitSetup) :
1728 EntryValue(EntryVal), ExitValue(ExitVal), EntryIsSetup(EntrySetup),
1729 ExitIsSetup(ExitSetup) { }
1730 // Can be negative, which means we are setting up a frame.
1738 /// Make sure on every path through the CFG, a FrameSetup <n> is always followed
1739 /// by a FrameDestroy <n>, stack adjustments are identical on all
1740 /// CFG edges to a merge point, and frame is destroyed at end of a return block.
1741 void MachineVerifier::verifyStackFrame() {
1742 unsigned FrameSetupOpcode = TII->getCallFrameSetupOpcode();
1743 unsigned FrameDestroyOpcode = TII->getCallFrameDestroyOpcode();
1745 SmallVector<StackStateOfBB, 8> SPState;
1746 SPState.resize(MF->getNumBlockIDs());
1747 SmallPtrSet<const MachineBasicBlock*, 8> Reachable;
1749 // Visit the MBBs in DFS order.
1750 for (df_ext_iterator<const MachineFunction*,
1751 SmallPtrSet<const MachineBasicBlock*, 8> >
1752 DFI = df_ext_begin(MF, Reachable), DFE = df_ext_end(MF, Reachable);
1753 DFI != DFE; ++DFI) {
1754 const MachineBasicBlock *MBB = *DFI;
1756 StackStateOfBB BBState;
1757 // Check the exit state of the DFS stack predecessor.
1758 if (DFI.getPathLength() >= 2) {
1759 const MachineBasicBlock *StackPred = DFI.getPath(DFI.getPathLength() - 2);
1760 assert(Reachable.count(StackPred) &&
1761 "DFS stack predecessor is already visited.\n");
1762 BBState.EntryValue = SPState[StackPred->getNumber()].ExitValue;
1763 BBState.EntryIsSetup = SPState[StackPred->getNumber()].ExitIsSetup;
1764 BBState.ExitValue = BBState.EntryValue;
1765 BBState.ExitIsSetup = BBState.EntryIsSetup;
1768 // Update stack state by checking contents of MBB.
1769 for (const auto &I : *MBB) {
1770 if (I.getOpcode() == FrameSetupOpcode) {
1771 // The first operand of a FrameOpcode should be i32.
1772 int Size = I.getOperand(0).getImm();
1774 "Value should be non-negative in FrameSetup and FrameDestroy.\n");
1776 if (BBState.ExitIsSetup)
1777 report("FrameSetup is after another FrameSetup", &I);
1778 BBState.ExitValue -= Size;
1779 BBState.ExitIsSetup = true;
1782 if (I.getOpcode() == FrameDestroyOpcode) {
1783 // The first operand of a FrameOpcode should be i32.
1784 int Size = I.getOperand(0).getImm();
1786 "Value should be non-negative in FrameSetup and FrameDestroy.\n");
1788 if (!BBState.ExitIsSetup)
1789 report("FrameDestroy is not after a FrameSetup", &I);
1790 int AbsSPAdj = BBState.ExitValue < 0 ? -BBState.ExitValue :
1792 if (BBState.ExitIsSetup && AbsSPAdj != Size) {
1793 report("FrameDestroy <n> is after FrameSetup <m>", &I);
1794 errs() << "FrameDestroy <" << Size << "> is after FrameSetup <"
1795 << AbsSPAdj << ">.\n";
1797 BBState.ExitValue += Size;
1798 BBState.ExitIsSetup = false;
1801 SPState[MBB->getNumber()] = BBState;
1803 // Make sure the exit state of any predecessor is consistent with the entry
1805 for (MachineBasicBlock::const_pred_iterator I = MBB->pred_begin(),
1806 E = MBB->pred_end(); I != E; ++I) {
1807 if (Reachable.count(*I) &&
1808 (SPState[(*I)->getNumber()].ExitValue != BBState.EntryValue ||
1809 SPState[(*I)->getNumber()].ExitIsSetup != BBState.EntryIsSetup)) {
1810 report("The exit stack state of a predecessor is inconsistent.", MBB);
1811 errs() << "Predecessor BB#" << (*I)->getNumber() << " has exit state ("
1812 << SPState[(*I)->getNumber()].ExitValue << ", "
1813 << SPState[(*I)->getNumber()].ExitIsSetup
1814 << "), while BB#" << MBB->getNumber() << " has entry state ("
1815 << BBState.EntryValue << ", " << BBState.EntryIsSetup << ").\n";
1819 // Make sure the entry state of any successor is consistent with the exit
1821 for (MachineBasicBlock::const_succ_iterator I = MBB->succ_begin(),
1822 E = MBB->succ_end(); I != E; ++I) {
1823 if (Reachable.count(*I) &&
1824 (SPState[(*I)->getNumber()].EntryValue != BBState.ExitValue ||
1825 SPState[(*I)->getNumber()].EntryIsSetup != BBState.ExitIsSetup)) {
1826 report("The entry stack state of a successor is inconsistent.", MBB);
1827 errs() << "Successor BB#" << (*I)->getNumber() << " has entry state ("
1828 << SPState[(*I)->getNumber()].EntryValue << ", "
1829 << SPState[(*I)->getNumber()].EntryIsSetup
1830 << "), while BB#" << MBB->getNumber() << " has exit state ("
1831 << BBState.ExitValue << ", " << BBState.ExitIsSetup << ").\n";
1835 // Make sure a basic block with return ends with zero stack adjustment.
1836 if (!MBB->empty() && MBB->back().isReturn()) {
1837 if (BBState.ExitIsSetup)
1838 report("A return block ends with a FrameSetup.", MBB);
1839 if (BBState.ExitValue)
1840 report("A return block ends with a nonzero stack adjustment.", MBB);