1 //===-- MachineVerifier.cpp - Machine Code Verifier -----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Pass to verify generated machine code. The following is checked:
12 // Operand counts: All explicit operands must be present.
14 // Register classes: All physical and virtual register operands must be
15 // compatible with the register class required by the instruction descriptor.
17 // Register live intervals: Registers must be defined only once, and must be
18 // defined before use.
20 // The machine code verifier is enabled from LLVMTargetMachine.cpp with the
21 // command-line option -verify-machineinstrs, or by defining the environment
22 // variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive
23 // the verifier errors.
24 //===----------------------------------------------------------------------===//
26 #include "llvm/CodeGen/Passes.h"
27 #include "llvm/ADT/DenseSet.h"
28 #include "llvm/ADT/DepthFirstIterator.h"
29 #include "llvm/ADT/SetOperations.h"
30 #include "llvm/ADT/SmallVector.h"
31 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
32 #include "llvm/CodeGen/LiveStackAnalysis.h"
33 #include "llvm/CodeGen/LiveVariables.h"
34 #include "llvm/CodeGen/MachineFrameInfo.h"
35 #include "llvm/CodeGen/MachineFunctionPass.h"
36 #include "llvm/CodeGen/MachineMemOperand.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/IR/BasicBlock.h"
39 #include "llvm/IR/InlineAsm.h"
40 #include "llvm/IR/Instructions.h"
41 #include "llvm/MC/MCAsmInfo.h"
42 #include "llvm/Support/Debug.h"
43 #include "llvm/Support/ErrorHandling.h"
44 #include "llvm/Support/FileSystem.h"
45 #include "llvm/Support/Format.h"
46 #include "llvm/Support/raw_ostream.h"
47 #include "llvm/Target/TargetInstrInfo.h"
48 #include "llvm/Target/TargetMachine.h"
49 #include "llvm/Target/TargetRegisterInfo.h"
50 #include "llvm/Target/TargetSubtargetInfo.h"
54 struct MachineVerifier {
56 MachineVerifier(Pass *pass, const char *b) :
59 OutFileName(getenv("LLVM_VERIFY_MACHINEINSTRS"))
62 bool runOnMachineFunction(MachineFunction &MF);
66 const char *const OutFileName;
68 const MachineFunction *MF;
69 const TargetMachine *TM;
70 const TargetInstrInfo *TII;
71 const TargetRegisterInfo *TRI;
72 const MachineRegisterInfo *MRI;
76 typedef SmallVector<unsigned, 16> RegVector;
77 typedef SmallVector<const uint32_t*, 4> RegMaskVector;
78 typedef DenseSet<unsigned> RegSet;
79 typedef DenseMap<unsigned, const MachineInstr*> RegMap;
80 typedef SmallPtrSet<const MachineBasicBlock*, 8> BlockSet;
82 const MachineInstr *FirstTerminator;
83 BlockSet FunctionBlocks;
85 BitVector regsReserved;
87 RegVector regsDefined, regsDead, regsKilled;
88 RegMaskVector regMasks;
89 RegSet regsLiveInButUnused;
93 // Add Reg and any sub-registers to RV
94 void addRegWithSubRegs(RegVector &RV, unsigned Reg) {
96 if (TargetRegisterInfo::isPhysicalRegister(Reg))
97 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
98 RV.push_back(*SubRegs);
102 // Is this MBB reachable from the MF entry point?
105 // Vregs that must be live in because they are used without being
106 // defined. Map value is the user.
109 // Regs killed in MBB. They may be defined again, and will then be in both
110 // regsKilled and regsLiveOut.
113 // Regs defined in MBB and live out. Note that vregs passing through may
114 // be live out without being mentioned here.
117 // Vregs that pass through MBB untouched. This set is disjoint from
118 // regsKilled and regsLiveOut.
121 // Vregs that must pass through MBB because they are needed by a successor
122 // block. This set is disjoint from regsLiveOut.
123 RegSet vregsRequired;
125 // Set versions of block's predecessor and successor lists.
126 BlockSet Preds, Succs;
128 BBInfo() : reachable(false) {}
130 // Add register to vregsPassed if it belongs there. Return true if
132 bool addPassed(unsigned Reg) {
133 if (!TargetRegisterInfo::isVirtualRegister(Reg))
135 if (regsKilled.count(Reg) || regsLiveOut.count(Reg))
137 return vregsPassed.insert(Reg).second;
140 // Same for a full set.
141 bool addPassed(const RegSet &RS) {
142 bool changed = false;
143 for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
149 // Add register to vregsRequired if it belongs there. Return true if
151 bool addRequired(unsigned Reg) {
152 if (!TargetRegisterInfo::isVirtualRegister(Reg))
154 if (regsLiveOut.count(Reg))
156 return vregsRequired.insert(Reg).second;
159 // Same for a full set.
160 bool addRequired(const RegSet &RS) {
161 bool changed = false;
162 for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
168 // Same for a full map.
169 bool addRequired(const RegMap &RM) {
170 bool changed = false;
171 for (RegMap::const_iterator I = RM.begin(), E = RM.end(); I != E; ++I)
172 if (addRequired(I->first))
177 // Live-out registers are either in regsLiveOut or vregsPassed.
178 bool isLiveOut(unsigned Reg) const {
179 return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
183 // Extra register info per MBB.
184 DenseMap<const MachineBasicBlock*, BBInfo> MBBInfoMap;
186 bool isReserved(unsigned Reg) {
187 return Reg < regsReserved.size() && regsReserved.test(Reg);
190 bool isAllocatable(unsigned Reg) {
191 return Reg < TRI->getNumRegs() && MRI->isAllocatable(Reg);
194 // Analysis information if available
195 LiveVariables *LiveVars;
196 LiveIntervals *LiveInts;
197 LiveStacks *LiveStks;
198 SlotIndexes *Indexes;
200 void visitMachineFunctionBefore();
201 void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);
202 void visitMachineBundleBefore(const MachineInstr *MI);
203 void visitMachineInstrBefore(const MachineInstr *MI);
204 void visitMachineOperand(const MachineOperand *MO, unsigned MONum);
205 void visitMachineInstrAfter(const MachineInstr *MI);
206 void visitMachineBundleAfter(const MachineInstr *MI);
207 void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB);
208 void visitMachineFunctionAfter();
210 void report(const char *msg, const MachineFunction *MF);
211 void report(const char *msg, const MachineBasicBlock *MBB);
212 void report(const char *msg, const MachineInstr *MI);
213 void report(const char *msg, const MachineOperand *MO, unsigned MONum);
214 void report(const char *msg, const MachineFunction *MF,
215 const LiveInterval &LI);
216 void report(const char *msg, const MachineBasicBlock *MBB,
217 const LiveInterval &LI);
218 void report(const char *msg, const MachineFunction *MF,
219 const LiveRange &LR, unsigned Reg, unsigned LaneMask);
220 void report(const char *msg, const MachineBasicBlock *MBB,
221 const LiveRange &LR, unsigned Reg, unsigned LaneMask);
223 void verifyInlineAsm(const MachineInstr *MI);
225 void checkLiveness(const MachineOperand *MO, unsigned MONum);
226 void markReachable(const MachineBasicBlock *MBB);
227 void calcRegsPassed();
228 void checkPHIOps(const MachineBasicBlock *MBB);
230 void calcRegsRequired();
231 void verifyLiveVariables();
232 void verifyLiveIntervals();
233 void verifyLiveInterval(const LiveInterval&);
234 void verifyLiveRangeValue(const LiveRange&, const VNInfo*, unsigned,
236 void verifyLiveRangeSegment(const LiveRange&,
237 const LiveRange::const_iterator I, unsigned,
239 void verifyLiveRange(const LiveRange&, unsigned, unsigned LaneMask = 0);
241 void verifyStackFrame();
244 struct MachineVerifierPass : public MachineFunctionPass {
245 static char ID; // Pass ID, replacement for typeid
246 const std::string Banner;
248 MachineVerifierPass(const std::string &banner = nullptr)
249 : MachineFunctionPass(ID), Banner(banner) {
250 initializeMachineVerifierPassPass(*PassRegistry::getPassRegistry());
253 void getAnalysisUsage(AnalysisUsage &AU) const override {
254 AU.setPreservesAll();
255 MachineFunctionPass::getAnalysisUsage(AU);
258 bool runOnMachineFunction(MachineFunction &MF) override {
259 MF.verify(this, Banner.c_str());
266 char MachineVerifierPass::ID = 0;
267 INITIALIZE_PASS(MachineVerifierPass, "machineverifier",
268 "Verify generated machine code", false, false)
270 FunctionPass *llvm::createMachineVerifierPass(const std::string &Banner) {
271 return new MachineVerifierPass(Banner);
274 void MachineFunction::verify(Pass *p, const char *Banner) const {
275 MachineVerifier(p, Banner)
276 .runOnMachineFunction(const_cast<MachineFunction&>(*this));
279 bool MachineVerifier::runOnMachineFunction(MachineFunction &MF) {
280 raw_ostream *OutFile = nullptr;
283 OutFile = new raw_fd_ostream(OutFileName, EC,
284 sys::fs::F_Append | sys::fs::F_Text);
286 errs() << "Error opening '" << OutFileName << "': " << EC.message()
299 TM = &MF.getTarget();
300 TII = MF.getSubtarget().getInstrInfo();
301 TRI = MF.getSubtarget().getRegisterInfo();
302 MRI = &MF.getRegInfo();
309 LiveInts = PASS->getAnalysisIfAvailable<LiveIntervals>();
310 // We don't want to verify LiveVariables if LiveIntervals is available.
312 LiveVars = PASS->getAnalysisIfAvailable<LiveVariables>();
313 LiveStks = PASS->getAnalysisIfAvailable<LiveStacks>();
314 Indexes = PASS->getAnalysisIfAvailable<SlotIndexes>();
317 visitMachineFunctionBefore();
318 for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end();
320 visitMachineBasicBlockBefore(MFI);
321 // Keep track of the current bundle header.
322 const MachineInstr *CurBundle = nullptr;
323 // Do we expect the next instruction to be part of the same bundle?
324 bool InBundle = false;
326 for (MachineBasicBlock::const_instr_iterator MBBI = MFI->instr_begin(),
327 MBBE = MFI->instr_end(); MBBI != MBBE; ++MBBI) {
328 if (MBBI->getParent() != MFI) {
329 report("Bad instruction parent pointer", MFI);
330 *OS << "Instruction: " << *MBBI;
334 // Check for consistent bundle flags.
335 if (InBundle && !MBBI->isBundledWithPred())
336 report("Missing BundledPred flag, "
337 "BundledSucc was set on predecessor", MBBI);
338 if (!InBundle && MBBI->isBundledWithPred())
339 report("BundledPred flag is set, "
340 "but BundledSucc not set on predecessor", MBBI);
342 // Is this a bundle header?
343 if (!MBBI->isInsideBundle()) {
345 visitMachineBundleAfter(CurBundle);
347 visitMachineBundleBefore(CurBundle);
348 } else if (!CurBundle)
349 report("No bundle header", MBBI);
350 visitMachineInstrBefore(MBBI);
351 for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I)
352 visitMachineOperand(&MBBI->getOperand(I), I);
353 visitMachineInstrAfter(MBBI);
355 // Was this the last bundled instruction?
356 InBundle = MBBI->isBundledWithSucc();
359 visitMachineBundleAfter(CurBundle);
361 report("BundledSucc flag set on last instruction in block", &MFI->back());
362 visitMachineBasicBlockAfter(MFI);
364 visitMachineFunctionAfter();
368 else if (foundErrors)
369 report_fatal_error("Found "+Twine(foundErrors)+" machine code errors.");
377 regsLiveInButUnused.clear();
380 return false; // no changes
383 void MachineVerifier::report(const char *msg, const MachineFunction *MF) {
386 if (!foundErrors++) {
388 *OS << "# " << Banner << '\n';
389 MF->print(*OS, Indexes);
391 *OS << "*** Bad machine code: " << msg << " ***\n"
392 << "- function: " << MF->getName() << "\n";
395 void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB) {
397 report(msg, MBB->getParent());
398 *OS << "- basic block: BB#" << MBB->getNumber()
399 << ' ' << MBB->getName()
400 << " (" << (const void*)MBB << ')';
402 *OS << " [" << Indexes->getMBBStartIdx(MBB)
403 << ';' << Indexes->getMBBEndIdx(MBB) << ')';
407 void MachineVerifier::report(const char *msg, const MachineInstr *MI) {
409 report(msg, MI->getParent());
410 *OS << "- instruction: ";
411 if (Indexes && Indexes->hasIndex(MI))
412 *OS << Indexes->getInstructionIndex(MI) << '\t';
416 void MachineVerifier::report(const char *msg,
417 const MachineOperand *MO, unsigned MONum) {
419 report(msg, MO->getParent());
420 *OS << "- operand " << MONum << ": ";
425 void MachineVerifier::report(const char *msg, const MachineFunction *MF,
426 const LiveInterval &LI) {
428 *OS << "- interval: " << LI << '\n';
431 void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB,
432 const LiveInterval &LI) {
434 *OS << "- interval: " << LI << '\n';
437 void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB,
438 const LiveRange &LR, unsigned Reg,
441 *OS << "- liverange: " << LR << '\n';
442 *OS << "- register: " << PrintReg(Reg, TRI) << '\n';
444 *OS << "- lanemask: " << format("%04X\n", LaneMask);
447 void MachineVerifier::report(const char *msg, const MachineFunction *MF,
448 const LiveRange &LR, unsigned Reg,
451 *OS << "- liverange: " << LR << '\n';
452 *OS << "- register: " << PrintReg(Reg, TRI) << '\n';
454 *OS << "- lanemask: " << format("%04X\n", LaneMask);
457 void MachineVerifier::markReachable(const MachineBasicBlock *MBB) {
458 BBInfo &MInfo = MBBInfoMap[MBB];
459 if (!MInfo.reachable) {
460 MInfo.reachable = true;
461 for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
462 SuE = MBB->succ_end(); SuI != SuE; ++SuI)
467 void MachineVerifier::visitMachineFunctionBefore() {
468 lastIndex = SlotIndex();
469 regsReserved = MRI->getReservedRegs();
471 // A sub-register of a reserved register is also reserved
472 for (int Reg = regsReserved.find_first(); Reg>=0;
473 Reg = regsReserved.find_next(Reg)) {
474 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
475 // FIXME: This should probably be:
476 // assert(regsReserved.test(*SubRegs) && "Non-reserved sub-register");
477 regsReserved.set(*SubRegs);
481 markReachable(&MF->front());
483 // Build a set of the basic blocks in the function.
484 FunctionBlocks.clear();
485 for (const auto &MBB : *MF) {
486 FunctionBlocks.insert(&MBB);
487 BBInfo &MInfo = MBBInfoMap[&MBB];
489 MInfo.Preds.insert(MBB.pred_begin(), MBB.pred_end());
490 if (MInfo.Preds.size() != MBB.pred_size())
491 report("MBB has duplicate entries in its predecessor list.", &MBB);
493 MInfo.Succs.insert(MBB.succ_begin(), MBB.succ_end());
494 if (MInfo.Succs.size() != MBB.succ_size())
495 report("MBB has duplicate entries in its successor list.", &MBB);
498 // Check that the register use lists are sane.
499 MRI->verifyUseLists();
504 // Does iterator point to a and b as the first two elements?
505 static bool matchPair(MachineBasicBlock::const_succ_iterator i,
506 const MachineBasicBlock *a, const MachineBasicBlock *b) {
515 MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
516 FirstTerminator = nullptr;
519 // If this block has allocatable physical registers live-in, check that
520 // it is an entry block or landing pad.
521 for (MachineBasicBlock::livein_iterator LI = MBB->livein_begin(),
522 LE = MBB->livein_end();
525 if (isAllocatable(reg) && !MBB->isLandingPad() &&
526 MBB != MBB->getParent()->begin()) {
527 report("MBB has allocable live-in, but isn't entry or landing-pad.", MBB);
532 // Count the number of landing pad successors.
533 SmallPtrSet<MachineBasicBlock*, 4> LandingPadSuccs;
534 for (MachineBasicBlock::const_succ_iterator I = MBB->succ_begin(),
535 E = MBB->succ_end(); I != E; ++I) {
536 if ((*I)->isLandingPad())
537 LandingPadSuccs.insert(*I);
538 if (!FunctionBlocks.count(*I))
539 report("MBB has successor that isn't part of the function.", MBB);
540 if (!MBBInfoMap[*I].Preds.count(MBB)) {
541 report("Inconsistent CFG", MBB);
542 *OS << "MBB is not in the predecessor list of the successor BB#"
543 << (*I)->getNumber() << ".\n";
547 // Check the predecessor list.
548 for (MachineBasicBlock::const_pred_iterator I = MBB->pred_begin(),
549 E = MBB->pred_end(); I != E; ++I) {
550 if (!FunctionBlocks.count(*I))
551 report("MBB has predecessor that isn't part of the function.", MBB);
552 if (!MBBInfoMap[*I].Succs.count(MBB)) {
553 report("Inconsistent CFG", MBB);
554 *OS << "MBB is not in the successor list of the predecessor BB#"
555 << (*I)->getNumber() << ".\n";
559 const MCAsmInfo *AsmInfo = TM->getMCAsmInfo();
560 const BasicBlock *BB = MBB->getBasicBlock();
561 if (LandingPadSuccs.size() > 1 &&
563 AsmInfo->getExceptionHandlingType() == ExceptionHandling::SjLj &&
564 BB && isa<SwitchInst>(BB->getTerminator())))
565 report("MBB has more than one landing pad successor", MBB);
567 // Call AnalyzeBranch. If it succeeds, there several more conditions to check.
568 MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
569 SmallVector<MachineOperand, 4> Cond;
570 if (!TII->AnalyzeBranch(*const_cast<MachineBasicBlock *>(MBB),
572 // Ok, AnalyzeBranch thinks it knows what's going on with this block. Let's
573 // check whether its answers match up with reality.
575 // Block falls through to its successor.
576 MachineFunction::const_iterator MBBI = MBB;
578 if (MBBI == MF->end()) {
579 // It's possible that the block legitimately ends with a noreturn
580 // call or an unreachable, in which case it won't actually fall
581 // out the bottom of the function.
582 } else if (MBB->succ_size() == LandingPadSuccs.size()) {
583 // It's possible that the block legitimately ends with a noreturn
584 // call or an unreachable, in which case it won't actuall fall
586 } else if (MBB->succ_size() != 1+LandingPadSuccs.size()) {
587 report("MBB exits via unconditional fall-through but doesn't have "
588 "exactly one CFG successor!", MBB);
589 } else if (!MBB->isSuccessor(MBBI)) {
590 report("MBB exits via unconditional fall-through but its successor "
591 "differs from its CFG successor!", MBB);
593 if (!MBB->empty() && MBB->back().isBarrier() &&
594 !TII->isPredicated(&MBB->back())) {
595 report("MBB exits via unconditional fall-through but ends with a "
596 "barrier instruction!", MBB);
599 report("MBB exits via unconditional fall-through but has a condition!",
602 } else if (TBB && !FBB && Cond.empty()) {
603 // Block unconditionally branches somewhere.
604 // If the block has exactly one successor, that happens to be a
605 // landingpad, accept it as valid control flow.
606 if (MBB->succ_size() != 1+LandingPadSuccs.size() &&
607 (MBB->succ_size() != 1 || LandingPadSuccs.size() != 1 ||
608 *MBB->succ_begin() != *LandingPadSuccs.begin())) {
609 report("MBB exits via unconditional branch but doesn't have "
610 "exactly one CFG successor!", MBB);
611 } else if (!MBB->isSuccessor(TBB)) {
612 report("MBB exits via unconditional branch but the CFG "
613 "successor doesn't match the actual successor!", MBB);
616 report("MBB exits via unconditional branch but doesn't contain "
617 "any instructions!", MBB);
618 } else if (!MBB->back().isBarrier()) {
619 report("MBB exits via unconditional branch but doesn't end with a "
620 "barrier instruction!", MBB);
621 } else if (!MBB->back().isTerminator()) {
622 report("MBB exits via unconditional branch but the branch isn't a "
623 "terminator instruction!", MBB);
625 } else if (TBB && !FBB && !Cond.empty()) {
626 // Block conditionally branches somewhere, otherwise falls through.
627 MachineFunction::const_iterator MBBI = MBB;
629 if (MBBI == MF->end()) {
630 report("MBB conditionally falls through out of function!", MBB);
631 } else if (MBB->succ_size() == 1) {
632 // A conditional branch with only one successor is weird, but allowed.
634 report("MBB exits via conditional branch/fall-through but only has "
635 "one CFG successor!", MBB);
636 else if (TBB != *MBB->succ_begin())
637 report("MBB exits via conditional branch/fall-through but the CFG "
638 "successor don't match the actual successor!", MBB);
639 } else if (MBB->succ_size() != 2) {
640 report("MBB exits via conditional branch/fall-through but doesn't have "
641 "exactly two CFG successors!", MBB);
642 } else if (!matchPair(MBB->succ_begin(), TBB, MBBI)) {
643 report("MBB exits via conditional branch/fall-through but the CFG "
644 "successors don't match the actual successors!", MBB);
647 report("MBB exits via conditional branch/fall-through but doesn't "
648 "contain any instructions!", MBB);
649 } else if (MBB->back().isBarrier()) {
650 report("MBB exits via conditional branch/fall-through but ends with a "
651 "barrier instruction!", MBB);
652 } else if (!MBB->back().isTerminator()) {
653 report("MBB exits via conditional branch/fall-through but the branch "
654 "isn't a terminator instruction!", MBB);
656 } else if (TBB && FBB) {
657 // Block conditionally branches somewhere, otherwise branches
659 if (MBB->succ_size() == 1) {
660 // A conditional branch with only one successor is weird, but allowed.
662 report("MBB exits via conditional branch/branch through but only has "
663 "one CFG successor!", MBB);
664 else if (TBB != *MBB->succ_begin())
665 report("MBB exits via conditional branch/branch through but the CFG "
666 "successor don't match the actual successor!", MBB);
667 } else if (MBB->succ_size() != 2) {
668 report("MBB exits via conditional branch/branch but doesn't have "
669 "exactly two CFG successors!", MBB);
670 } else if (!matchPair(MBB->succ_begin(), TBB, FBB)) {
671 report("MBB exits via conditional branch/branch but the CFG "
672 "successors don't match the actual successors!", MBB);
675 report("MBB exits via conditional branch/branch but doesn't "
676 "contain any instructions!", MBB);
677 } else if (!MBB->back().isBarrier()) {
678 report("MBB exits via conditional branch/branch but doesn't end with a "
679 "barrier instruction!", MBB);
680 } else if (!MBB->back().isTerminator()) {
681 report("MBB exits via conditional branch/branch but the branch "
682 "isn't a terminator instruction!", MBB);
685 report("MBB exits via conditinal branch/branch but there's no "
689 report("AnalyzeBranch returned invalid data!", MBB);
694 for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(),
695 E = MBB->livein_end(); I != E; ++I) {
696 if (!TargetRegisterInfo::isPhysicalRegister(*I)) {
697 report("MBB live-in list contains non-physical register", MBB);
700 for (MCSubRegIterator SubRegs(*I, TRI, /*IncludeSelf=*/true);
701 SubRegs.isValid(); ++SubRegs)
702 regsLive.insert(*SubRegs);
704 regsLiveInButUnused = regsLive;
706 const MachineFrameInfo *MFI = MF->getFrameInfo();
707 assert(MFI && "Function has no frame info");
708 BitVector PR = MFI->getPristineRegs(MBB);
709 for (int I = PR.find_first(); I>0; I = PR.find_next(I)) {
710 for (MCSubRegIterator SubRegs(I, TRI, /*IncludeSelf=*/true);
711 SubRegs.isValid(); ++SubRegs)
712 regsLive.insert(*SubRegs);
719 lastIndex = Indexes->getMBBStartIdx(MBB);
722 // This function gets called for all bundle headers, including normal
723 // stand-alone unbundled instructions.
724 void MachineVerifier::visitMachineBundleBefore(const MachineInstr *MI) {
725 if (Indexes && Indexes->hasIndex(MI)) {
726 SlotIndex idx = Indexes->getInstructionIndex(MI);
727 if (!(idx > lastIndex)) {
728 report("Instruction index out of order", MI);
729 *OS << "Last instruction was at " << lastIndex << '\n';
734 // Ensure non-terminators don't follow terminators.
735 // Ignore predicated terminators formed by if conversion.
736 // FIXME: If conversion shouldn't need to violate this rule.
737 if (MI->isTerminator() && !TII->isPredicated(MI)) {
738 if (!FirstTerminator)
739 FirstTerminator = MI;
740 } else if (FirstTerminator) {
741 report("Non-terminator instruction after the first terminator", MI);
742 *OS << "First terminator was:\t" << *FirstTerminator;
746 // The operands on an INLINEASM instruction must follow a template.
747 // Verify that the flag operands make sense.
748 void MachineVerifier::verifyInlineAsm(const MachineInstr *MI) {
749 // The first two operands on INLINEASM are the asm string and global flags.
750 if (MI->getNumOperands() < 2) {
751 report("Too few operands on inline asm", MI);
754 if (!MI->getOperand(0).isSymbol())
755 report("Asm string must be an external symbol", MI);
756 if (!MI->getOperand(1).isImm())
757 report("Asm flags must be an immediate", MI);
758 // Allowed flags are Extra_HasSideEffects = 1, Extra_IsAlignStack = 2,
759 // Extra_AsmDialect = 4, Extra_MayLoad = 8, and Extra_MayStore = 16.
760 if (!isUInt<5>(MI->getOperand(1).getImm()))
761 report("Unknown asm flags", &MI->getOperand(1), 1);
763 assert(InlineAsm::MIOp_FirstOperand == 2 && "Asm format changed");
765 unsigned OpNo = InlineAsm::MIOp_FirstOperand;
767 for (unsigned e = MI->getNumOperands(); OpNo < e; OpNo += NumOps) {
768 const MachineOperand &MO = MI->getOperand(OpNo);
769 // There may be implicit ops after the fixed operands.
772 NumOps = 1 + InlineAsm::getNumOperandRegisters(MO.getImm());
775 if (OpNo > MI->getNumOperands())
776 report("Missing operands in last group", MI);
778 // An optional MDNode follows the groups.
779 if (OpNo < MI->getNumOperands() && MI->getOperand(OpNo).isMetadata())
782 // All trailing operands must be implicit registers.
783 for (unsigned e = MI->getNumOperands(); OpNo < e; ++OpNo) {
784 const MachineOperand &MO = MI->getOperand(OpNo);
785 if (!MO.isReg() || !MO.isImplicit())
786 report("Expected implicit register after groups", &MO, OpNo);
790 void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
791 const MCInstrDesc &MCID = MI->getDesc();
792 if (MI->getNumOperands() < MCID.getNumOperands()) {
793 report("Too few operands", MI);
794 *OS << MCID.getNumOperands() << " operands expected, but "
795 << MI->getNumOperands() << " given.\n";
798 // Check the tied operands.
799 if (MI->isInlineAsm())
802 // Check the MachineMemOperands for basic consistency.
803 for (MachineInstr::mmo_iterator I = MI->memoperands_begin(),
804 E = MI->memoperands_end(); I != E; ++I) {
805 if ((*I)->isLoad() && !MI->mayLoad())
806 report("Missing mayLoad flag", MI);
807 if ((*I)->isStore() && !MI->mayStore())
808 report("Missing mayStore flag", MI);
811 // Debug values must not have a slot index.
812 // Other instructions must have one, unless they are inside a bundle.
814 bool mapped = !LiveInts->isNotInMIMap(MI);
815 if (MI->isDebugValue()) {
817 report("Debug instruction has a slot index", MI);
818 } else if (MI->isInsideBundle()) {
820 report("Instruction inside bundle has a slot index", MI);
823 report("Missing slot index", MI);
828 if (!TII->verifyInstruction(MI, ErrorInfo))
829 report(ErrorInfo.data(), MI);
833 MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
834 const MachineInstr *MI = MO->getParent();
835 const MCInstrDesc &MCID = MI->getDesc();
837 // The first MCID.NumDefs operands must be explicit register defines
838 if (MONum < MCID.getNumDefs()) {
839 const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
841 report("Explicit definition must be a register", MO, MONum);
842 else if (!MO->isDef() && !MCOI.isOptionalDef())
843 report("Explicit definition marked as use", MO, MONum);
844 else if (MO->isImplicit())
845 report("Explicit definition marked as implicit", MO, MONum);
846 } else if (MONum < MCID.getNumOperands()) {
847 const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
848 // Don't check if it's the last operand in a variadic instruction. See,
849 // e.g., LDM_RET in the arm back end.
851 !(MI->isVariadic() && MONum == MCID.getNumOperands()-1)) {
852 if (MO->isDef() && !MCOI.isOptionalDef())
853 report("Explicit operand marked as def", MO, MONum);
854 if (MO->isImplicit())
855 report("Explicit operand marked as implicit", MO, MONum);
858 int TiedTo = MCID.getOperandConstraint(MONum, MCOI::TIED_TO);
861 report("Tied use must be a register", MO, MONum);
862 else if (!MO->isTied())
863 report("Operand should be tied", MO, MONum);
864 else if (unsigned(TiedTo) != MI->findTiedOperandIdx(MONum))
865 report("Tied def doesn't match MCInstrDesc", MO, MONum);
866 } else if (MO->isReg() && MO->isTied())
867 report("Explicit operand should not be tied", MO, MONum);
869 // ARM adds %reg0 operands to indicate predicates. We'll allow that.
870 if (MO->isReg() && !MO->isImplicit() && !MI->isVariadic() && MO->getReg())
871 report("Extra explicit operand on non-variadic instruction", MO, MONum);
874 switch (MO->getType()) {
875 case MachineOperand::MO_Register: {
876 const unsigned Reg = MO->getReg();
879 if (MRI->tracksLiveness() && !MI->isDebugValue())
880 checkLiveness(MO, MONum);
882 // Verify the consistency of tied operands.
884 unsigned OtherIdx = MI->findTiedOperandIdx(MONum);
885 const MachineOperand &OtherMO = MI->getOperand(OtherIdx);
886 if (!OtherMO.isReg())
887 report("Must be tied to a register", MO, MONum);
888 if (!OtherMO.isTied())
889 report("Missing tie flags on tied operand", MO, MONum);
890 if (MI->findTiedOperandIdx(OtherIdx) != MONum)
891 report("Inconsistent tie links", MO, MONum);
892 if (MONum < MCID.getNumDefs()) {
893 if (OtherIdx < MCID.getNumOperands()) {
894 if (-1 == MCID.getOperandConstraint(OtherIdx, MCOI::TIED_TO))
895 report("Explicit def tied to explicit use without tie constraint",
898 if (!OtherMO.isImplicit())
899 report("Explicit def should be tied to implicit use", MO, MONum);
904 // Verify two-address constraints after leaving SSA form.
906 if (!MRI->isSSA() && MO->isUse() &&
907 MI->isRegTiedToDefOperand(MONum, &DefIdx) &&
908 Reg != MI->getOperand(DefIdx).getReg())
909 report("Two-address instruction operands must be identical", MO, MONum);
911 // Check register classes.
912 if (MONum < MCID.getNumOperands() && !MO->isImplicit()) {
913 unsigned SubIdx = MO->getSubReg();
915 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
917 report("Illegal subregister index for physical register", MO, MONum);
920 if (const TargetRegisterClass *DRC =
921 TII->getRegClass(MCID, MONum, TRI, *MF)) {
922 if (!DRC->contains(Reg)) {
923 report("Illegal physical register for instruction", MO, MONum);
924 *OS << TRI->getName(Reg) << " is not a "
925 << TRI->getRegClassName(DRC) << " register.\n";
930 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
932 const TargetRegisterClass *SRC =
933 TRI->getSubClassWithSubReg(RC, SubIdx);
935 report("Invalid subregister index for virtual register", MO, MONum);
936 *OS << "Register class " << TRI->getRegClassName(RC)
937 << " does not support subreg index " << SubIdx << "\n";
941 report("Invalid register class for subregister index", MO, MONum);
942 *OS << "Register class " << TRI->getRegClassName(RC)
943 << " does not fully support subreg index " << SubIdx << "\n";
947 if (const TargetRegisterClass *DRC =
948 TII->getRegClass(MCID, MONum, TRI, *MF)) {
950 const TargetRegisterClass *SuperRC =
951 TRI->getLargestLegalSuperClass(RC);
953 report("No largest legal super class exists.", MO, MONum);
956 DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx);
958 report("No matching super-reg register class.", MO, MONum);
962 if (!RC->hasSuperClassEq(DRC)) {
963 report("Illegal virtual register for instruction", MO, MONum);
964 *OS << "Expected a " << TRI->getRegClassName(DRC)
965 << " register, but got a " << TRI->getRegClassName(RC)
974 case MachineOperand::MO_RegisterMask:
975 regMasks.push_back(MO->getRegMask());
978 case MachineOperand::MO_MachineBasicBlock:
979 if (MI->isPHI() && !MO->getMBB()->isSuccessor(MI->getParent()))
980 report("PHI operand is not in the CFG", MO, MONum);
983 case MachineOperand::MO_FrameIndex:
984 if (LiveStks && LiveStks->hasInterval(MO->getIndex()) &&
985 LiveInts && !LiveInts->isNotInMIMap(MI)) {
986 LiveInterval &LI = LiveStks->getInterval(MO->getIndex());
987 SlotIndex Idx = LiveInts->getInstructionIndex(MI);
988 if (MI->mayLoad() && !LI.liveAt(Idx.getRegSlot(true))) {
989 report("Instruction loads from dead spill slot", MO, MONum);
990 *OS << "Live stack: " << LI << '\n';
992 if (MI->mayStore() && !LI.liveAt(Idx.getRegSlot())) {
993 report("Instruction stores to dead spill slot", MO, MONum);
994 *OS << "Live stack: " << LI << '\n';
1004 void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) {
1005 const MachineInstr *MI = MO->getParent();
1006 const unsigned Reg = MO->getReg();
1008 // Both use and def operands can read a register.
1009 if (MO->readsReg()) {
1010 regsLiveInButUnused.erase(Reg);
1013 addRegWithSubRegs(regsKilled, Reg);
1015 // Check that LiveVars knows this kill.
1016 if (LiveVars && TargetRegisterInfo::isVirtualRegister(Reg) &&
1018 LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
1019 if (std::find(VI.Kills.begin(), VI.Kills.end(), MI) == VI.Kills.end())
1020 report("Kill missing from LiveVariables", MO, MONum);
1023 // Check LiveInts liveness and kill.
1024 if (LiveInts && !LiveInts->isNotInMIMap(MI)) {
1025 SlotIndex UseIdx = LiveInts->getInstructionIndex(MI);
1026 // Check the cached regunit intervals.
1027 if (TargetRegisterInfo::isPhysicalRegister(Reg) && !isReserved(Reg)) {
1028 for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units) {
1029 if (const LiveRange *LR = LiveInts->getCachedRegUnit(*Units)) {
1030 LiveQueryResult LRQ = LR->Query(UseIdx);
1031 if (!LRQ.valueIn()) {
1032 report("No live segment at use", MO, MONum);
1033 *OS << UseIdx << " is not live in " << PrintRegUnit(*Units, TRI)
1034 << ' ' << *LR << '\n';
1036 if (MO->isKill() && !LRQ.isKill()) {
1037 report("Live range continues after kill flag", MO, MONum);
1038 *OS << PrintRegUnit(*Units, TRI) << ' ' << *LR << '\n';
1044 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
1045 if (LiveInts->hasInterval(Reg)) {
1046 // This is a virtual register interval.
1047 const LiveInterval &LI = LiveInts->getInterval(Reg);
1048 LiveQueryResult LRQ = LI.Query(UseIdx);
1049 if (!LRQ.valueIn()) {
1050 report("No live segment at use", MO, MONum);
1051 *OS << UseIdx << " is not live in " << LI << '\n';
1053 // Check for extra kill flags.
1054 // Note that we allow missing kill flags for now.
1055 if (MO->isKill() && !LRQ.isKill()) {
1056 report("Live range continues after kill flag", MO, MONum);
1057 *OS << "Live range: " << LI << '\n';
1060 report("Virtual register has no live interval", MO, MONum);
1065 // Use of a dead register.
1066 if (!regsLive.count(Reg)) {
1067 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
1068 // Reserved registers may be used even when 'dead'.
1069 bool Bad = !isReserved(Reg);
1070 // We are fine if just any subregister has a defined value.
1072 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid();
1074 if (regsLive.count(*SubRegs)) {
1080 // If there is an additional implicit-use of a super register we stop
1081 // here. By definition we are fine if the super register is not
1082 // (completely) dead, if the complete super register is dead we will
1083 // get a report for its operand.
1085 for (const MachineOperand &MOP : MI->uses()) {
1088 if (!MOP.isImplicit())
1090 for (MCSubRegIterator SubRegs(MOP.getReg(), TRI); SubRegs.isValid();
1092 if (*SubRegs == Reg) {
1100 report("Using an undefined physical register", MO, MONum);
1101 } else if (MRI->def_empty(Reg)) {
1102 report("Reading virtual register without a def", MO, MONum);
1104 BBInfo &MInfo = MBBInfoMap[MI->getParent()];
1105 // We don't know which virtual registers are live in, so only complain
1106 // if vreg was killed in this MBB. Otherwise keep track of vregs that
1107 // must be live in. PHI instructions are handled separately.
1108 if (MInfo.regsKilled.count(Reg))
1109 report("Using a killed virtual register", MO, MONum);
1110 else if (!MI->isPHI())
1111 MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));
1117 // Register defined.
1118 // TODO: verify that earlyclobber ops are not used.
1120 addRegWithSubRegs(regsDead, Reg);
1122 addRegWithSubRegs(regsDefined, Reg);
1125 if (MRI->isSSA() && TargetRegisterInfo::isVirtualRegister(Reg) &&
1126 std::next(MRI->def_begin(Reg)) != MRI->def_end())
1127 report("Multiple virtual register defs in SSA form", MO, MONum);
1129 // Check LiveInts for a live segment, but only for virtual registers.
1130 if (LiveInts && TargetRegisterInfo::isVirtualRegister(Reg) &&
1131 !LiveInts->isNotInMIMap(MI)) {
1132 SlotIndex DefIdx = LiveInts->getInstructionIndex(MI);
1133 DefIdx = DefIdx.getRegSlot(MO->isEarlyClobber());
1134 if (LiveInts->hasInterval(Reg)) {
1135 const LiveInterval &LI = LiveInts->getInterval(Reg);
1136 if (const VNInfo *VNI = LI.getVNInfoAt(DefIdx)) {
1137 assert(VNI && "NULL valno is not allowed");
1138 if (VNI->def != DefIdx) {
1139 report("Inconsistent valno->def", MO, MONum);
1140 *OS << "Valno " << VNI->id << " is not defined at "
1141 << DefIdx << " in " << LI << '\n';
1144 report("No live segment at def", MO, MONum);
1145 *OS << DefIdx << " is not live in " << LI << '\n';
1147 // Check that, if the dead def flag is present, LiveInts agree.
1149 LiveQueryResult LRQ = LI.Query(DefIdx);
1150 if (!LRQ.isDeadDef()) {
1151 report("Live range continues after dead def flag", MO, MONum);
1152 *OS << "Live range: " << LI << '\n';
1156 report("Virtual register has no Live interval", MO, MONum);
1162 void MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI) {
1165 // This function gets called after visiting all instructions in a bundle. The
1166 // argument points to the bundle header.
1167 // Normal stand-alone instructions are also considered 'bundles', and this
1168 // function is called for all of them.
1169 void MachineVerifier::visitMachineBundleAfter(const MachineInstr *MI) {
1170 BBInfo &MInfo = MBBInfoMap[MI->getParent()];
1171 set_union(MInfo.regsKilled, regsKilled);
1172 set_subtract(regsLive, regsKilled); regsKilled.clear();
1173 // Kill any masked registers.
1174 while (!regMasks.empty()) {
1175 const uint32_t *Mask = regMasks.pop_back_val();
1176 for (RegSet::iterator I = regsLive.begin(), E = regsLive.end(); I != E; ++I)
1177 if (TargetRegisterInfo::isPhysicalRegister(*I) &&
1178 MachineOperand::clobbersPhysReg(Mask, *I))
1179 regsDead.push_back(*I);
1181 set_subtract(regsLive, regsDead); regsDead.clear();
1182 set_union(regsLive, regsDefined); regsDefined.clear();
1186 MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB) {
1187 MBBInfoMap[MBB].regsLiveOut = regsLive;
1191 SlotIndex stop = Indexes->getMBBEndIdx(MBB);
1192 if (!(stop > lastIndex)) {
1193 report("Block ends before last instruction index", MBB);
1194 *OS << "Block ends at " << stop
1195 << " last instruction was at " << lastIndex << '\n';
1201 // Calculate the largest possible vregsPassed sets. These are the registers that
1202 // can pass through an MBB live, but may not be live every time. It is assumed
1203 // that all vregsPassed sets are empty before the call.
1204 void MachineVerifier::calcRegsPassed() {
1205 // First push live-out regs to successors' vregsPassed. Remember the MBBs that
1206 // have any vregsPassed.
1207 SmallPtrSet<const MachineBasicBlock*, 8> todo;
1208 for (const auto &MBB : *MF) {
1209 BBInfo &MInfo = MBBInfoMap[&MBB];
1210 if (!MInfo.reachable)
1212 for (MachineBasicBlock::const_succ_iterator SuI = MBB.succ_begin(),
1213 SuE = MBB.succ_end(); SuI != SuE; ++SuI) {
1214 BBInfo &SInfo = MBBInfoMap[*SuI];
1215 if (SInfo.addPassed(MInfo.regsLiveOut))
1220 // Iteratively push vregsPassed to successors. This will converge to the same
1221 // final state regardless of DenseSet iteration order.
1222 while (!todo.empty()) {
1223 const MachineBasicBlock *MBB = *todo.begin();
1225 BBInfo &MInfo = MBBInfoMap[MBB];
1226 for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
1227 SuE = MBB->succ_end(); SuI != SuE; ++SuI) {
1230 BBInfo &SInfo = MBBInfoMap[*SuI];
1231 if (SInfo.addPassed(MInfo.vregsPassed))
1237 // Calculate the set of virtual registers that must be passed through each basic
1238 // block in order to satisfy the requirements of successor blocks. This is very
1239 // similar to calcRegsPassed, only backwards.
1240 void MachineVerifier::calcRegsRequired() {
1241 // First push live-in regs to predecessors' vregsRequired.
1242 SmallPtrSet<const MachineBasicBlock*, 8> todo;
1243 for (const auto &MBB : *MF) {
1244 BBInfo &MInfo = MBBInfoMap[&MBB];
1245 for (MachineBasicBlock::const_pred_iterator PrI = MBB.pred_begin(),
1246 PrE = MBB.pred_end(); PrI != PrE; ++PrI) {
1247 BBInfo &PInfo = MBBInfoMap[*PrI];
1248 if (PInfo.addRequired(MInfo.vregsLiveIn))
1253 // Iteratively push vregsRequired to predecessors. This will converge to the
1254 // same final state regardless of DenseSet iteration order.
1255 while (!todo.empty()) {
1256 const MachineBasicBlock *MBB = *todo.begin();
1258 BBInfo &MInfo = MBBInfoMap[MBB];
1259 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
1260 PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
1263 BBInfo &SInfo = MBBInfoMap[*PrI];
1264 if (SInfo.addRequired(MInfo.vregsRequired))
1270 // Check PHI instructions at the beginning of MBB. It is assumed that
1271 // calcRegsPassed has been run so BBInfo::isLiveOut is valid.
1272 void MachineVerifier::checkPHIOps(const MachineBasicBlock *MBB) {
1273 SmallPtrSet<const MachineBasicBlock*, 8> seen;
1274 for (const auto &BBI : *MBB) {
1279 for (unsigned i = 1, e = BBI.getNumOperands(); i != e; i += 2) {
1280 unsigned Reg = BBI.getOperand(i).getReg();
1281 const MachineBasicBlock *Pre = BBI.getOperand(i + 1).getMBB();
1282 if (!Pre->isSuccessor(MBB))
1285 BBInfo &PrInfo = MBBInfoMap[Pre];
1286 if (PrInfo.reachable && !PrInfo.isLiveOut(Reg))
1287 report("PHI operand is not live-out from predecessor",
1288 &BBI.getOperand(i), i);
1291 // Did we see all predecessors?
1292 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
1293 PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
1294 if (!seen.count(*PrI)) {
1295 report("Missing PHI operand", &BBI);
1296 *OS << "BB#" << (*PrI)->getNumber()
1297 << " is a predecessor according to the CFG.\n";
1303 void MachineVerifier::visitMachineFunctionAfter() {
1306 for (const auto &MBB : *MF) {
1307 BBInfo &MInfo = MBBInfoMap[&MBB];
1309 // Skip unreachable MBBs.
1310 if (!MInfo.reachable)
1316 // Now check liveness info if available
1319 // Check for killed virtual registers that should be live out.
1320 for (const auto &MBB : *MF) {
1321 BBInfo &MInfo = MBBInfoMap[&MBB];
1322 for (RegSet::iterator
1323 I = MInfo.vregsRequired.begin(), E = MInfo.vregsRequired.end(); I != E;
1325 if (MInfo.regsKilled.count(*I)) {
1326 report("Virtual register killed in block, but needed live out.", &MBB);
1327 *OS << "Virtual register " << PrintReg(*I)
1328 << " is used after the block.\n";
1333 BBInfo &MInfo = MBBInfoMap[&MF->front()];
1334 for (RegSet::iterator
1335 I = MInfo.vregsRequired.begin(), E = MInfo.vregsRequired.end(); I != E;
1337 report("Virtual register def doesn't dominate all uses.",
1338 MRI->getVRegDef(*I));
1342 verifyLiveVariables();
1344 verifyLiveIntervals();
1347 void MachineVerifier::verifyLiveVariables() {
1348 assert(LiveVars && "Don't call verifyLiveVariables without LiveVars");
1349 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
1350 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
1351 LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
1352 for (const auto &MBB : *MF) {
1353 BBInfo &MInfo = MBBInfoMap[&MBB];
1355 // Our vregsRequired should be identical to LiveVariables' AliveBlocks
1356 if (MInfo.vregsRequired.count(Reg)) {
1357 if (!VI.AliveBlocks.test(MBB.getNumber())) {
1358 report("LiveVariables: Block missing from AliveBlocks", &MBB);
1359 *OS << "Virtual register " << PrintReg(Reg)
1360 << " must be live through the block.\n";
1363 if (VI.AliveBlocks.test(MBB.getNumber())) {
1364 report("LiveVariables: Block should not be in AliveBlocks", &MBB);
1365 *OS << "Virtual register " << PrintReg(Reg)
1366 << " is not needed live through the block.\n";
1373 void MachineVerifier::verifyLiveIntervals() {
1374 assert(LiveInts && "Don't call verifyLiveIntervals without LiveInts");
1375 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
1376 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
1378 // Spilling and splitting may leave unused registers around. Skip them.
1379 if (MRI->reg_nodbg_empty(Reg))
1382 if (!LiveInts->hasInterval(Reg)) {
1383 report("Missing live interval for virtual register", MF);
1384 *OS << PrintReg(Reg, TRI) << " still has defs or uses\n";
1388 const LiveInterval &LI = LiveInts->getInterval(Reg);
1389 assert(Reg == LI.reg && "Invalid reg to interval mapping");
1390 verifyLiveInterval(LI);
1393 // Verify all the cached regunit intervals.
1394 for (unsigned i = 0, e = TRI->getNumRegUnits(); i != e; ++i)
1395 if (const LiveRange *LR = LiveInts->getCachedRegUnit(i))
1396 verifyLiveRange(*LR, i);
1399 void MachineVerifier::verifyLiveRangeValue(const LiveRange &LR,
1400 const VNInfo *VNI, unsigned Reg,
1401 unsigned LaneMask) {
1402 if (VNI->isUnused())
1405 const VNInfo *DefVNI = LR.getVNInfoAt(VNI->def);
1408 report("Valno not live at def and not marked unused", MF, LR, Reg,
1410 *OS << "Valno #" << VNI->id << '\n';
1414 if (DefVNI != VNI) {
1415 report("Live segment at def has different valno", MF, LR, Reg, LaneMask);
1416 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
1417 << " where valno #" << DefVNI->id << " is live\n";
1421 const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(VNI->def);
1423 report("Invalid definition index", MF, LR, Reg, LaneMask);
1424 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
1425 << " in " << LR << '\n';
1429 if (VNI->isPHIDef()) {
1430 if (VNI->def != LiveInts->getMBBStartIdx(MBB)) {
1431 report("PHIDef value is not defined at MBB start", MBB, LR, Reg,
1433 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
1434 << ", not at the beginning of BB#" << MBB->getNumber() << '\n';
1440 const MachineInstr *MI = LiveInts->getInstructionFromIndex(VNI->def);
1442 report("No instruction at def index", MBB, LR, Reg, LaneMask);
1443 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def << '\n';
1448 bool hasDef = false;
1449 bool isEarlyClobber = false;
1450 for (ConstMIBundleOperands MOI(MI); MOI.isValid(); ++MOI) {
1451 if (!MOI->isReg() || !MOI->isDef())
1453 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
1454 if (MOI->getReg() != Reg)
1457 if (!TargetRegisterInfo::isPhysicalRegister(MOI->getReg()) ||
1458 !TRI->hasRegUnit(MOI->getReg(), Reg))
1461 if (LaneMask != 0 &&
1462 (TRI->getSubRegIndexLaneMask(MOI->getSubReg()) & LaneMask) == 0)
1465 if (MOI->isEarlyClobber())
1466 isEarlyClobber = true;
1470 report("Defining instruction does not modify register", MI);
1471 *OS << "Valno #" << VNI->id << " in " << LR << '\n';
1474 // Early clobber defs begin at USE slots, but other defs must begin at
1476 if (isEarlyClobber) {
1477 if (!VNI->def.isEarlyClobber()) {
1478 report("Early clobber def must be at an early-clobber slot", MBB, LR,
1480 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def << '\n';
1482 } else if (!VNI->def.isRegister()) {
1483 report("Non-PHI, non-early clobber def must be at a register slot",
1484 MBB, LR, Reg, LaneMask);
1485 *OS << "Valno #" << VNI->id << " is defined at " << VNI->def << '\n';
1490 void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR,
1491 const LiveRange::const_iterator I,
1492 unsigned Reg, unsigned LaneMask) {
1493 const LiveRange::Segment &S = *I;
1494 const VNInfo *VNI = S.valno;
1495 assert(VNI && "Live segment has no valno");
1497 if (VNI->id >= LR.getNumValNums() || VNI != LR.getValNumInfo(VNI->id)) {
1498 report("Foreign valno in live segment", MF, LR, Reg, LaneMask);
1499 *OS << S << " has a bad valno\n";
1502 if (VNI->isUnused()) {
1503 report("Live segment valno is marked unused", MF, LR, Reg, LaneMask);
1507 const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(S.start);
1509 report("Bad start of live segment, no basic block", MF, LR, Reg, LaneMask);
1513 SlotIndex MBBStartIdx = LiveInts->getMBBStartIdx(MBB);
1514 if (S.start != MBBStartIdx && S.start != VNI->def) {
1515 report("Live segment must begin at MBB entry or valno def", MBB, LR, Reg,
1520 const MachineBasicBlock *EndMBB =
1521 LiveInts->getMBBFromIndex(S.end.getPrevSlot());
1523 report("Bad end of live segment, no basic block", MF, LR, Reg, LaneMask);
1528 // No more checks for live-out segments.
1529 if (S.end == LiveInts->getMBBEndIdx(EndMBB))
1532 // RegUnit intervals are allowed dead phis.
1533 if (!TargetRegisterInfo::isVirtualRegister(Reg) && VNI->isPHIDef() &&
1534 S.start == VNI->def && S.end == VNI->def.getDeadSlot())
1537 // The live segment is ending inside EndMBB
1538 const MachineInstr *MI =
1539 LiveInts->getInstructionFromIndex(S.end.getPrevSlot());
1541 report("Live segment doesn't end at a valid instruction", EndMBB, LR, Reg,
1547 // The block slot must refer to a basic block boundary.
1548 if (S.end.isBlock()) {
1549 report("Live segment ends at B slot of an instruction", EndMBB, LR, Reg,
1554 if (S.end.isDead()) {
1555 // Segment ends on the dead slot.
1556 // That means there must be a dead def.
1557 if (!SlotIndex::isSameInstr(S.start, S.end)) {
1558 report("Live segment ending at dead slot spans instructions", EndMBB, LR,
1564 // A live segment can only end at an early-clobber slot if it is being
1565 // redefined by an early-clobber def.
1566 if (S.end.isEarlyClobber()) {
1567 if (I+1 == LR.end() || (I+1)->start != S.end) {
1568 report("Live segment ending at early clobber slot must be "
1569 "redefined by an EC def in the same instruction", EndMBB, LR, Reg,
1575 // The following checks only apply to virtual registers. Physreg liveness
1576 // is too weird to check.
1577 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
1578 // A live segment can end with either a redefinition, a kill flag on a
1579 // use, or a dead flag on a def.
1580 bool hasRead = false;
1581 bool hasSubRegDef = false;
1582 for (ConstMIBundleOperands MOI(MI); MOI.isValid(); ++MOI) {
1583 if (!MOI->isReg() || MOI->getReg() != Reg)
1585 if (LaneMask != 0 &&
1586 (LaneMask & TRI->getSubRegIndexLaneMask(MOI->getSubReg())) == 0)
1588 if (MOI->isDef() && MOI->getSubReg() != 0)
1589 hasSubRegDef = true;
1590 if (MOI->readsReg())
1593 if (!S.end.isDead()) {
1595 // When tracking subregister liveness, the main range must start new
1596 // values on partial register writes, even if there is no read.
1597 if (!MRI->tracksSubRegLiveness() || LaneMask != 0 || !hasSubRegDef) {
1598 report("Instruction ending live segment doesn't read the register",
1600 *OS << S << " in " << LR << '\n';
1606 // Now check all the basic blocks in this live segment.
1607 MachineFunction::const_iterator MFI = MBB;
1608 // Is this live segment the beginning of a non-PHIDef VN?
1609 if (S.start == VNI->def && !VNI->isPHIDef()) {
1610 // Not live-in to any blocks.
1617 assert(LiveInts->isLiveInToMBB(LR, MFI));
1618 // We don't know how to track physregs into a landing pad.
1619 if (!TargetRegisterInfo::isVirtualRegister(Reg) &&
1620 MFI->isLandingPad()) {
1621 if (&*MFI == EndMBB)
1627 // Is VNI a PHI-def in the current block?
1628 bool IsPHI = VNI->isPHIDef() &&
1629 VNI->def == LiveInts->getMBBStartIdx(MFI);
1631 // Check that VNI is live-out of all predecessors.
1632 for (MachineBasicBlock::const_pred_iterator PI = MFI->pred_begin(),
1633 PE = MFI->pred_end(); PI != PE; ++PI) {
1634 SlotIndex PEnd = LiveInts->getMBBEndIdx(*PI);
1635 const VNInfo *PVNI = LR.getVNInfoBefore(PEnd);
1637 // All predecessors must have a live-out value.
1639 report("Register not marked live out of predecessor", *PI, LR, Reg,
1641 *OS << "Valno #" << VNI->id << " live into BB#" << MFI->getNumber()
1642 << '@' << LiveInts->getMBBStartIdx(MFI) << ", not live before "
1647 // Only PHI-defs can take different predecessor values.
1648 if (!IsPHI && PVNI != VNI) {
1649 report("Different value live out of predecessor", *PI, LR, Reg,
1651 *OS << "Valno #" << PVNI->id << " live out of BB#"
1652 << (*PI)->getNumber() << '@' << PEnd
1653 << "\nValno #" << VNI->id << " live into BB#" << MFI->getNumber()
1654 << '@' << LiveInts->getMBBStartIdx(MFI) << '\n';
1657 if (&*MFI == EndMBB)
1663 void MachineVerifier::verifyLiveRange(const LiveRange &LR, unsigned Reg,
1664 unsigned LaneMask) {
1665 for (const VNInfo *VNI : LR.valnos)
1666 verifyLiveRangeValue(LR, VNI, Reg, LaneMask);
1668 for (LiveRange::const_iterator I = LR.begin(), E = LR.end(); I != E; ++I)
1669 verifyLiveRangeSegment(LR, I, Reg, LaneMask);
1672 void MachineVerifier::verifyLiveInterval(const LiveInterval &LI) {
1673 verifyLiveRange(LI, LI.reg);
1675 unsigned Reg = LI.reg;
1676 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
1678 unsigned MaxMask = MRI->getMaxLaneMaskForVReg(Reg);
1679 for (const LiveInterval::SubRange &SR : LI.subranges()) {
1680 if ((Mask & SR.LaneMask) != 0)
1681 report("Lane masks of sub ranges overlap in live interval", MF, LI);
1682 if ((SR.LaneMask & ~MaxMask) != 0)
1683 report("Subrange lanemask is invalid", MF, LI);
1684 Mask |= SR.LaneMask;
1685 verifyLiveRange(SR, LI.reg, SR.LaneMask);
1687 report("A Subrange is not covered by the main range", MF, LI);
1689 } else if (LI.hasSubRanges()) {
1690 report("subregister liveness only allowed for virtual registers", MF, LI);
1693 // Check the LI only has one connected component.
1694 if (TargetRegisterInfo::isVirtualRegister(LI.reg)) {
1695 ConnectedVNInfoEqClasses ConEQ(*LiveInts);
1696 unsigned NumComp = ConEQ.Classify(&LI);
1698 report("Multiple connected components in live interval", MF, LI);
1699 for (unsigned comp = 0; comp != NumComp; ++comp) {
1700 *OS << comp << ": valnos";
1701 for (LiveInterval::const_vni_iterator I = LI.vni_begin(),
1702 E = LI.vni_end(); I!=E; ++I)
1703 if (comp == ConEQ.getEqClass(*I))
1704 *OS << ' ' << (*I)->id;
1712 // FrameSetup and FrameDestroy can have zero adjustment, so using a single
1713 // integer, we can't tell whether it is a FrameSetup or FrameDestroy if the
1715 // We use a bool plus an integer to capture the stack state.
1716 struct StackStateOfBB {
1717 StackStateOfBB() : EntryValue(0), ExitValue(0), EntryIsSetup(false),
1718 ExitIsSetup(false) { }
1719 StackStateOfBB(int EntryVal, int ExitVal, bool EntrySetup, bool ExitSetup) :
1720 EntryValue(EntryVal), ExitValue(ExitVal), EntryIsSetup(EntrySetup),
1721 ExitIsSetup(ExitSetup) { }
1722 // Can be negative, which means we are setting up a frame.
1730 /// Make sure on every path through the CFG, a FrameSetup <n> is always followed
1731 /// by a FrameDestroy <n>, stack adjustments are identical on all
1732 /// CFG edges to a merge point, and frame is destroyed at end of a return block.
1733 void MachineVerifier::verifyStackFrame() {
1734 int FrameSetupOpcode = TII->getCallFrameSetupOpcode();
1735 int FrameDestroyOpcode = TII->getCallFrameDestroyOpcode();
1737 SmallVector<StackStateOfBB, 8> SPState;
1738 SPState.resize(MF->getNumBlockIDs());
1739 SmallPtrSet<const MachineBasicBlock*, 8> Reachable;
1741 // Visit the MBBs in DFS order.
1742 for (df_ext_iterator<const MachineFunction*,
1743 SmallPtrSet<const MachineBasicBlock*, 8> >
1744 DFI = df_ext_begin(MF, Reachable), DFE = df_ext_end(MF, Reachable);
1745 DFI != DFE; ++DFI) {
1746 const MachineBasicBlock *MBB = *DFI;
1748 StackStateOfBB BBState;
1749 // Check the exit state of the DFS stack predecessor.
1750 if (DFI.getPathLength() >= 2) {
1751 const MachineBasicBlock *StackPred = DFI.getPath(DFI.getPathLength() - 2);
1752 assert(Reachable.count(StackPred) &&
1753 "DFS stack predecessor is already visited.\n");
1754 BBState.EntryValue = SPState[StackPred->getNumber()].ExitValue;
1755 BBState.EntryIsSetup = SPState[StackPred->getNumber()].ExitIsSetup;
1756 BBState.ExitValue = BBState.EntryValue;
1757 BBState.ExitIsSetup = BBState.EntryIsSetup;
1760 // Update stack state by checking contents of MBB.
1761 for (const auto &I : *MBB) {
1762 if (I.getOpcode() == FrameSetupOpcode) {
1763 // The first operand of a FrameOpcode should be i32.
1764 int Size = I.getOperand(0).getImm();
1766 "Value should be non-negative in FrameSetup and FrameDestroy.\n");
1768 if (BBState.ExitIsSetup)
1769 report("FrameSetup is after another FrameSetup", &I);
1770 BBState.ExitValue -= Size;
1771 BBState.ExitIsSetup = true;
1774 if (I.getOpcode() == FrameDestroyOpcode) {
1775 // The first operand of a FrameOpcode should be i32.
1776 int Size = I.getOperand(0).getImm();
1778 "Value should be non-negative in FrameSetup and FrameDestroy.\n");
1780 if (!BBState.ExitIsSetup)
1781 report("FrameDestroy is not after a FrameSetup", &I);
1782 int AbsSPAdj = BBState.ExitValue < 0 ? -BBState.ExitValue :
1784 if (BBState.ExitIsSetup && AbsSPAdj != Size) {
1785 report("FrameDestroy <n> is after FrameSetup <m>", &I);
1786 *OS << "FrameDestroy <" << Size << "> is after FrameSetup <"
1787 << AbsSPAdj << ">.\n";
1789 BBState.ExitValue += Size;
1790 BBState.ExitIsSetup = false;
1793 SPState[MBB->getNumber()] = BBState;
1795 // Make sure the exit state of any predecessor is consistent with the entry
1797 for (MachineBasicBlock::const_pred_iterator I = MBB->pred_begin(),
1798 E = MBB->pred_end(); I != E; ++I) {
1799 if (Reachable.count(*I) &&
1800 (SPState[(*I)->getNumber()].ExitValue != BBState.EntryValue ||
1801 SPState[(*I)->getNumber()].ExitIsSetup != BBState.EntryIsSetup)) {
1802 report("The exit stack state of a predecessor is inconsistent.", MBB);
1803 *OS << "Predecessor BB#" << (*I)->getNumber() << " has exit state ("
1804 << SPState[(*I)->getNumber()].ExitValue << ", "
1805 << SPState[(*I)->getNumber()].ExitIsSetup
1806 << "), while BB#" << MBB->getNumber() << " has entry state ("
1807 << BBState.EntryValue << ", " << BBState.EntryIsSetup << ").\n";
1811 // Make sure the entry state of any successor is consistent with the exit
1813 for (MachineBasicBlock::const_succ_iterator I = MBB->succ_begin(),
1814 E = MBB->succ_end(); I != E; ++I) {
1815 if (Reachable.count(*I) &&
1816 (SPState[(*I)->getNumber()].EntryValue != BBState.ExitValue ||
1817 SPState[(*I)->getNumber()].EntryIsSetup != BBState.ExitIsSetup)) {
1818 report("The entry stack state of a successor is inconsistent.", MBB);
1819 *OS << "Successor BB#" << (*I)->getNumber() << " has entry state ("
1820 << SPState[(*I)->getNumber()].EntryValue << ", "
1821 << SPState[(*I)->getNumber()].EntryIsSetup
1822 << "), while BB#" << MBB->getNumber() << " has exit state ("
1823 << BBState.ExitValue << ", " << BBState.ExitIsSetup << ").\n";
1827 // Make sure a basic block with return ends with zero stack adjustment.
1828 if (!MBB->empty() && MBB->back().isReturn()) {
1829 if (BBState.ExitIsSetup)
1830 report("A return block ends with a FrameSetup.", MBB);
1831 if (BBState.ExitValue)
1832 report("A return block ends with a nonzero stack adjustment.", MBB);