1 //===-- MachineVerifier.cpp - Machine Code Verifier -------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Pass to verify generated machine code. The following is checked:
12 // Operand counts: All explicit operands must be present.
14 // Register classes: All physical and virtual register operands must be
15 // compatible with the register class required by the instruction descriptor.
17 // Register live intervals: Registers must be defined only once, and must be
18 // defined before use.
20 // The machine code verifier is enabled from LLVMTargetMachine.cpp with the
21 // command-line option -verify-machineinstrs, or by defining the environment
22 // variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive
23 // the verifier errors.
24 //===----------------------------------------------------------------------===//
26 #include "llvm/ADT/DenseSet.h"
27 #include "llvm/ADT/SetOperations.h"
28 #include "llvm/ADT/SmallVector.h"
29 #include "llvm/Function.h"
30 #include "llvm/CodeGen/LiveVariables.h"
31 #include "llvm/CodeGen/MachineFunctionPass.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/Passes.h"
34 #include "llvm/Target/TargetMachine.h"
35 #include "llvm/Target/TargetRegisterInfo.h"
36 #include "llvm/Target/TargetInstrInfo.h"
37 #include "llvm/Support/Compiler.h"
38 #include "llvm/Support/Debug.h"
39 #include "llvm/Support/ErrorHandling.h"
40 #include "llvm/Support/raw_ostream.h"
46 struct VISIBILITY_HIDDEN MachineVerifier : public MachineFunctionPass {
47 static char ID; // Pass ID, replacement for typeid
49 MachineVerifier(bool allowDoubleDefs = false) :
50 MachineFunctionPass(&ID),
51 allowVirtDoubleDefs(allowDoubleDefs),
52 allowPhysDoubleDefs(allowDoubleDefs),
53 OutFileName(getenv("LLVM_VERIFY_MACHINEINSTRS"))
56 void getAnalysisUsage(AnalysisUsage &AU) const {
58 MachineFunctionPass::getAnalysisUsage(AU);
61 bool runOnMachineFunction(MachineFunction &MF);
63 const bool allowVirtDoubleDefs;
64 const bool allowPhysDoubleDefs;
66 const char *const OutFileName;
68 const MachineFunction *MF;
69 const TargetMachine *TM;
70 const TargetRegisterInfo *TRI;
71 const MachineRegisterInfo *MRI;
75 typedef SmallVector<unsigned, 16> RegVector;
76 typedef DenseSet<unsigned> RegSet;
77 typedef DenseMap<unsigned, const MachineInstr*> RegMap;
79 BitVector regsReserved;
81 RegVector regsDefined, regsImpDefined, regsDead, regsKilled;
83 // Add Reg and any sub-registers to RV
84 void addRegWithSubRegs(RegVector &RV, unsigned Reg) {
86 if (TargetRegisterInfo::isPhysicalRegister(Reg))
87 for (const unsigned *R = TRI->getSubRegisters(Reg); *R; R++)
91 // Does RS contain any super-registers of Reg?
92 bool anySuperRegisters(const RegSet &RS, unsigned Reg) {
93 for (const unsigned *R = TRI->getSuperRegisters(Reg); *R; R++)
100 // Is this MBB reachable from the MF entry point?
103 // Vregs that must be live in because they are used without being
104 // defined. Map value is the user.
107 // Vregs that must be dead in because they are defined without being
108 // killed first. Map value is the defining instruction.
111 // Regs killed in MBB. They may be defined again, and will then be in both
112 // regsKilled and regsLiveOut.
115 // Regs defined in MBB and live out. Note that vregs passing through may
116 // be live out without being mentioned here.
119 // Vregs that pass through MBB untouched. This set is disjoint from
120 // regsKilled and regsLiveOut.
123 BBInfo() : reachable(false) {}
125 // Add register to vregsPassed if it belongs there. Return true if
127 bool addPassed(unsigned Reg) {
128 if (!TargetRegisterInfo::isVirtualRegister(Reg))
130 if (regsKilled.count(Reg) || regsLiveOut.count(Reg))
132 return vregsPassed.insert(Reg).second;
135 // Same for a full set.
136 bool addPassed(const RegSet &RS) {
137 bool changed = false;
138 for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
144 // Live-out registers are either in regsLiveOut or vregsPassed.
145 bool isLiveOut(unsigned Reg) const {
146 return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
150 // Extra register info per MBB.
151 DenseMap<const MachineBasicBlock*, BBInfo> MBBInfoMap;
153 bool isReserved(unsigned Reg) {
154 return Reg < regsReserved.size() && regsReserved[Reg];
157 void visitMachineFunctionBefore();
158 void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);
159 void visitMachineInstrBefore(const MachineInstr *MI);
160 void visitMachineOperand(const MachineOperand *MO, unsigned MONum);
161 void visitMachineInstrAfter(const MachineInstr *MI);
162 void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB);
163 void visitMachineFunctionAfter();
165 void report(const char *msg, const MachineFunction *MF);
166 void report(const char *msg, const MachineBasicBlock *MBB);
167 void report(const char *msg, const MachineInstr *MI);
168 void report(const char *msg, const MachineOperand *MO, unsigned MONum);
170 void markReachable(const MachineBasicBlock *MBB);
171 void calcMaxRegsPassed();
172 void calcMinRegsPassed();
173 void checkPHIOps(const MachineBasicBlock *MBB);
177 char MachineVerifier::ID = 0;
178 static RegisterPass<MachineVerifier>
179 MachineVer("machineverifier", "Verify generated machine code");
180 static const PassInfo *const MachineVerifyID = &MachineVer;
183 llvm::createMachineVerifierPass(bool allowPhysDoubleDefs)
185 return new MachineVerifier(allowPhysDoubleDefs);
189 MachineVerifier::runOnMachineFunction(MachineFunction &MF)
191 std::ofstream OutFile;
193 OutFile.open(OutFileName, std::ios::out | std::ios::app);
202 TM = &MF.getTarget();
203 TRI = TM->getRegisterInfo();
204 MRI = &MF.getRegInfo();
206 visitMachineFunctionBefore();
207 for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end();
209 visitMachineBasicBlockBefore(MFI);
210 for (MachineBasicBlock::const_iterator MBBI = MFI->begin(),
211 MBBE = MFI->end(); MBBI != MBBE; ++MBBI) {
212 visitMachineInstrBefore(MBBI);
213 for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I)
214 visitMachineOperand(&MBBI->getOperand(I), I);
215 visitMachineInstrAfter(MBBI);
217 visitMachineBasicBlockAfter(MFI);
219 visitMachineFunctionAfter();
223 else if (foundErrors) {
225 raw_string_ostream Msg(msg);
226 Msg << "Found " << foundErrors << " machine code errors.";
227 llvm_report_error(Msg.str());
230 return false; // no changes
234 MachineVerifier::report(const char *msg, const MachineFunction *MF)
240 *OS << "*** Bad machine code: " << msg << " ***\n"
241 << "- function: " << MF->getFunction()->getNameStr() << "\n";
245 MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB)
248 report(msg, MBB->getParent());
249 *OS << "- basic block: " << MBB->getBasicBlock()->getNameStr()
251 << " (#" << MBB->getNumber() << ")\n";
255 MachineVerifier::report(const char *msg, const MachineInstr *MI)
258 report(msg, MI->getParent());
259 *OS << "- instruction: ";
264 MachineVerifier::report(const char *msg,
265 const MachineOperand *MO, unsigned MONum)
268 report(msg, MO->getParent());
269 *OS << "- operand " << MONum << ": ";
275 MachineVerifier::markReachable(const MachineBasicBlock *MBB)
277 BBInfo &MInfo = MBBInfoMap[MBB];
278 if (!MInfo.reachable) {
279 MInfo.reachable = true;
280 for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
281 SuE = MBB->succ_end(); SuI != SuE; ++SuI)
287 MachineVerifier::visitMachineFunctionBefore()
289 regsReserved = TRI->getReservedRegs(*MF);
290 markReachable(&MF->front());
294 MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB)
297 for (MachineBasicBlock::const_livein_iterator I = MBB->livein_begin(),
298 E = MBB->livein_end(); I != E; ++I) {
299 if (!TargetRegisterInfo::isPhysicalRegister(*I)) {
300 report("MBB live-in list contains non-physical register", MBB);
304 for (const unsigned *R = TRI->getSubRegisters(*I); *R; R++)
309 regsImpDefined.clear();
313 MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI)
315 const TargetInstrDesc &TI = MI->getDesc();
316 if (MI->getNumExplicitOperands() < TI.getNumOperands()) {
317 report("Too few operands", MI);
318 *OS << TI.getNumOperands() << " operands expected, but "
319 << MI->getNumExplicitOperands() << " given.\n";
321 if (!TI.isVariadic()) {
322 if (MI->getNumExplicitOperands() > TI.getNumOperands()) {
323 report("Too many operands", MI);
324 *OS << TI.getNumOperands() << " operands expected, but "
325 << MI->getNumExplicitOperands() << " given.\n";
331 MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum)
333 const MachineInstr *MI = MO->getParent();
334 const TargetInstrDesc &TI = MI->getDesc();
336 // The first TI.NumDefs operands must be explicit register defines
337 if (MONum < TI.getNumDefs()) {
339 report("Explicit definition must be a register", MO, MONum);
340 else if (!MO->isDef())
341 report("Explicit definition marked as use", MO, MONum);
342 else if (MO->isImplicit())
343 report("Explicit definition marked as implicit", MO, MONum);
346 switch (MO->getType()) {
347 case MachineOperand::MO_Register: {
348 const unsigned Reg = MO->getReg();
352 // Check Live Variables.
355 addRegWithSubRegs(regsKilled, Reg);
356 // Tied operands on two-address instuctions MUST NOT have a <kill> flag.
357 if (MI->isRegTiedToDefOperand(MONum))
358 report("Illegal kill flag on two-address instruction operand",
361 // TwoAddress instr modifying a reg is treated as kill+def.
363 if (MI->isRegTiedToDefOperand(MONum, &defIdx) &&
364 MI->getOperand(defIdx).getReg() == Reg)
365 addRegWithSubRegs(regsKilled, Reg);
367 // Explicit use of a dead register.
368 // A register use marked <undef> is OK.
369 if (!MO->isImplicit() && !MO->isUndef() && !regsLive.count(Reg)) {
370 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
371 // Reserved registers may be used even when 'dead'.
372 if (!isReserved(Reg))
373 report("Using an undefined physical register", MO, MONum);
375 BBInfo &MInfo = MBBInfoMap[MI->getParent()];
376 // We don't know which virtual registers are live in, so only complain
377 // if vreg was killed in this MBB. Otherwise keep track of vregs that
378 // must be live in. PHI instructions are handled separately.
379 if (MInfo.regsKilled.count(Reg))
380 report("Using a killed virtual register", MO, MONum);
381 else if (MI->getOpcode() != TargetInstrInfo::PHI)
382 MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));
387 // TODO: verify that earlyclobber ops are not used.
388 if (MO->isImplicit())
389 addRegWithSubRegs(regsImpDefined, Reg);
391 addRegWithSubRegs(regsDefined, Reg);
394 addRegWithSubRegs(regsDead, Reg);
397 // Check register classes.
398 if (MONum < TI.getNumOperands() && !MO->isImplicit()) {
399 const TargetOperandInfo &TOI = TI.OpInfo[MONum];
400 unsigned SubIdx = MO->getSubReg();
402 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
405 unsigned s = TRI->getSubReg(Reg, SubIdx);
407 report("Invalid subregister index for physical register",
413 if (const TargetRegisterClass *DRC = TOI.getRegClass(TRI)) {
414 if (!DRC->contains(sr)) {
415 report("Illegal physical register for instruction", MO, MONum);
416 *OS << TRI->getName(sr) << " is not a "
417 << DRC->getName() << " register.\n";
422 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
424 if (RC->subregclasses_begin()+SubIdx >= RC->subregclasses_end()) {
425 report("Invalid subregister index for virtual register", MO, MONum);
428 RC = *(RC->subregclasses_begin()+SubIdx);
430 if (const TargetRegisterClass *DRC = TOI.getRegClass(TRI)) {
431 if (RC != DRC && !RC->hasSuperClass(DRC)) {
432 report("Illegal virtual register for instruction", MO, MONum);
433 *OS << "Expected a " << DRC->getName() << " register, but got a "
434 << RC->getName() << " register\n";
441 // Can PHI instrs refer to MBBs not in the CFG? X86 and ARM do.
442 // case MachineOperand::MO_MachineBasicBlock:
443 // if (MI->getOpcode() == TargetInstrInfo::PHI) {
444 // if (!MO->getMBB()->isSuccessor(MI->getParent()))
445 // report("PHI operand is not in the CFG", MO, MONum);
454 MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI)
456 BBInfo &MInfo = MBBInfoMap[MI->getParent()];
457 set_union(MInfo.regsKilled, regsKilled);
458 set_subtract(regsLive, regsKilled);
461 for (RegVector::const_iterator I = regsDefined.begin(),
462 E = regsDefined.end(); I != E; ++I) {
463 if (regsLive.count(*I)) {
464 if (TargetRegisterInfo::isPhysicalRegister(*I)) {
465 // We allow double defines to physical registers with live
467 if (!allowPhysDoubleDefs && !isReserved(*I) &&
468 !anySuperRegisters(regsLive, *I)) {
469 report("Redefining a live physical register", MI);
470 *OS << "Register " << TRI->getName(*I)
471 << " was defined but already live.\n";
474 if (!allowVirtDoubleDefs) {
475 report("Redefining a live virtual register", MI);
476 *OS << "Virtual register %reg" << *I
477 << " was defined but already live.\n";
480 } else if (TargetRegisterInfo::isVirtualRegister(*I) &&
481 !MInfo.regsKilled.count(*I)) {
482 // Virtual register defined without being killed first must be dead on
484 MInfo.vregsDeadIn.insert(std::make_pair(*I, MI));
488 set_union(regsLive, regsDefined); regsDefined.clear();
489 set_union(regsLive, regsImpDefined); regsImpDefined.clear();
490 set_subtract(regsLive, regsDead); regsDead.clear();
494 MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB)
496 MBBInfoMap[MBB].regsLiveOut = regsLive;
500 // Calculate the largest possible vregsPassed sets. These are the registers that
501 // can pass through an MBB live, but may not be live every time. It is assumed
502 // that all vregsPassed sets are empty before the call.
504 MachineVerifier::calcMaxRegsPassed()
506 // First push live-out regs to successors' vregsPassed. Remember the MBBs that
507 // have any vregsPassed.
508 DenseSet<const MachineBasicBlock*> todo;
509 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
511 const MachineBasicBlock &MBB(*MFI);
512 BBInfo &MInfo = MBBInfoMap[&MBB];
513 if (!MInfo.reachable)
515 for (MachineBasicBlock::const_succ_iterator SuI = MBB.succ_begin(),
516 SuE = MBB.succ_end(); SuI != SuE; ++SuI) {
517 BBInfo &SInfo = MBBInfoMap[*SuI];
518 if (SInfo.addPassed(MInfo.regsLiveOut))
523 // Iteratively push vregsPassed to successors. This will converge to the same
524 // final state regardless of DenseSet iteration order.
525 while (!todo.empty()) {
526 const MachineBasicBlock *MBB = *todo.begin();
528 BBInfo &MInfo = MBBInfoMap[MBB];
529 for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
530 SuE = MBB->succ_end(); SuI != SuE; ++SuI) {
533 BBInfo &SInfo = MBBInfoMap[*SuI];
534 if (SInfo.addPassed(MInfo.vregsPassed))
540 // Calculate the minimum vregsPassed set. These are the registers that always
541 // pass live through an MBB. The calculation assumes that calcMaxRegsPassed has
542 // been called earlier.
544 MachineVerifier::calcMinRegsPassed()
546 DenseSet<const MachineBasicBlock*> todo;
547 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
551 while (!todo.empty()) {
552 const MachineBasicBlock *MBB = *todo.begin();
554 BBInfo &MInfo = MBBInfoMap[MBB];
556 // Remove entries from vRegsPassed that are not live out from all
557 // reachable predecessors.
559 for (RegSet::iterator I = MInfo.vregsPassed.begin(),
560 E = MInfo.vregsPassed.end(); I != E; ++I) {
561 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
562 PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
563 BBInfo &PrInfo = MBBInfoMap[*PrI];
564 if (PrInfo.reachable && !PrInfo.isLiveOut(*I)) {
570 // If any regs removed, we need to recheck successors.
572 set_subtract(MInfo.vregsPassed, dead);
573 todo.insert(MBB->succ_begin(), MBB->succ_end());
578 // Check PHI instructions at the beginning of MBB. It is assumed that
579 // calcMinRegsPassed has been run so BBInfo::isLiveOut is valid.
581 MachineVerifier::checkPHIOps(const MachineBasicBlock *MBB)
583 for (MachineBasicBlock::const_iterator BBI = MBB->begin(), BBE = MBB->end();
584 BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI) {
585 DenseSet<const MachineBasicBlock*> seen;
587 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
588 unsigned Reg = BBI->getOperand(i).getReg();
589 const MachineBasicBlock *Pre = BBI->getOperand(i + 1).getMBB();
590 if (!Pre->isSuccessor(MBB))
593 BBInfo &PrInfo = MBBInfoMap[Pre];
594 if (PrInfo.reachable && !PrInfo.isLiveOut(Reg))
595 report("PHI operand is not live-out from predecessor",
596 &BBI->getOperand(i), i);
599 // Did we see all predecessors?
600 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
601 PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
602 if (!seen.count(*PrI)) {
603 report("Missing PHI operand", BBI);
604 *OS << "MBB #" << (*PrI)->getNumber()
605 << " is a predecessor according to the CFG.\n";
612 MachineVerifier::visitMachineFunctionAfter()
616 // With the maximal set of vregsPassed we can verify dead-in registers.
617 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
619 BBInfo &MInfo = MBBInfoMap[MFI];
621 // Skip unreachable MBBs.
622 if (!MInfo.reachable)
625 for (MachineBasicBlock::const_pred_iterator PrI = MFI->pred_begin(),
626 PrE = MFI->pred_end(); PrI != PrE; ++PrI) {
627 BBInfo &PrInfo = MBBInfoMap[*PrI];
628 if (!PrInfo.reachable)
631 // Verify physical live-ins. EH landing pads have magic live-ins so we
633 if (!MFI->isLandingPad()) {
634 for (MachineBasicBlock::const_livein_iterator I = MFI->livein_begin(),
635 E = MFI->livein_end(); I != E; ++I) {
636 if (TargetRegisterInfo::isPhysicalRegister(*I) &&
637 !isReserved (*I) && !PrInfo.isLiveOut(*I)) {
638 report("Live-in physical register is not live-out from predecessor",
640 *OS << "Register " << TRI->getName(*I)
641 << " is not live-out from MBB #" << (*PrI)->getNumber()
648 // Verify dead-in virtual registers.
649 if (!allowVirtDoubleDefs) {
650 for (RegMap::iterator I = MInfo.vregsDeadIn.begin(),
651 E = MInfo.vregsDeadIn.end(); I != E; ++I) {
652 // DeadIn register must be in neither regsLiveOut or vregsPassed of
654 if (PrInfo.isLiveOut(I->first)) {
655 report("Live-in virtual register redefined", I->second);
656 *OS << "Register %reg" << I->first
657 << " was live-out from predecessor MBB #"
658 << (*PrI)->getNumber() << ".\n";
667 // With the minimal set of vregsPassed we can verify live-in virtual
668 // registers, including PHI instructions.
669 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
671 BBInfo &MInfo = MBBInfoMap[MFI];
673 // Skip unreachable MBBs.
674 if (!MInfo.reachable)
679 for (MachineBasicBlock::const_pred_iterator PrI = MFI->pred_begin(),
680 PrE = MFI->pred_end(); PrI != PrE; ++PrI) {
681 BBInfo &PrInfo = MBBInfoMap[*PrI];
682 if (!PrInfo.reachable)
685 for (RegMap::iterator I = MInfo.vregsLiveIn.begin(),
686 E = MInfo.vregsLiveIn.end(); I != E; ++I) {
687 if (!PrInfo.isLiveOut(I->first)) {
688 report("Used virtual register is not live-in", I->second);
689 *OS << "Register %reg" << I->first
690 << " is not live-out from predecessor MBB #"
691 << (*PrI)->getNumber()