1 //===- MachineScheduler.cpp - Machine Instruction Scheduler ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // MachineScheduler schedules machine instructions after phi elimination. It
11 // preserves LiveIntervals so it can be invoked before register allocation.
13 //===----------------------------------------------------------------------===//
15 #include "llvm/CodeGen/MachineScheduler.h"
16 #include "llvm/ADT/PriorityQueue.h"
17 #include "llvm/Analysis/AliasAnalysis.h"
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "llvm/CodeGen/MachineDominators.h"
20 #include "llvm/CodeGen/MachineLoopInfo.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/Passes.h"
23 #include "llvm/CodeGen/RegisterClassInfo.h"
24 #include "llvm/CodeGen/ScheduleDFS.h"
25 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/ErrorHandling.h"
29 #include "llvm/Support/GraphWriter.h"
30 #include "llvm/Support/raw_ostream.h"
31 #include "llvm/Target/TargetInstrInfo.h"
36 #define DEBUG_TYPE "misched"
39 cl::opt<bool> ForceTopDown("misched-topdown", cl::Hidden,
40 cl::desc("Force top-down list scheduling"));
41 cl::opt<bool> ForceBottomUp("misched-bottomup", cl::Hidden,
42 cl::desc("Force bottom-up list scheduling"));
46 static cl::opt<bool> ViewMISchedDAGs("view-misched-dags", cl::Hidden,
47 cl::desc("Pop up a window to show MISched dags after they are processed"));
49 static cl::opt<unsigned> MISchedCutoff("misched-cutoff", cl::Hidden,
50 cl::desc("Stop scheduling after N instructions"), cl::init(~0U));
52 static cl::opt<std::string> SchedOnlyFunc("misched-only-func", cl::Hidden,
53 cl::desc("Only schedule this function"));
54 static cl::opt<unsigned> SchedOnlyBlock("misched-only-block", cl::Hidden,
55 cl::desc("Only schedule this MBB#"));
57 static bool ViewMISchedDAGs = false;
60 static cl::opt<bool> EnableRegPressure("misched-regpressure", cl::Hidden,
61 cl::desc("Enable register pressure scheduling."), cl::init(true));
63 static cl::opt<bool> EnableCyclicPath("misched-cyclicpath", cl::Hidden,
64 cl::desc("Enable cyclic critical path analysis."), cl::init(true));
66 static cl::opt<bool> EnableLoadCluster("misched-cluster", cl::Hidden,
67 cl::desc("Enable load clustering."), cl::init(true));
69 // Experimental heuristics
70 static cl::opt<bool> EnableMacroFusion("misched-fusion", cl::Hidden,
71 cl::desc("Enable scheduling for macro fusion."), cl::init(true));
73 static cl::opt<bool> VerifyScheduling("verify-misched", cl::Hidden,
74 cl::desc("Verify machine instrs before and after machine scheduling"));
76 // DAG subtrees must have at least this many nodes.
77 static const unsigned MinSubtreeSize = 8;
79 // Pin the vtables to this file.
80 void MachineSchedStrategy::anchor() {}
81 void ScheduleDAGMutation::anchor() {}
83 //===----------------------------------------------------------------------===//
84 // Machine Instruction Scheduling Pass and Registry
85 //===----------------------------------------------------------------------===//
87 MachineSchedContext::MachineSchedContext():
88 MF(nullptr), MLI(nullptr), MDT(nullptr), PassConfig(nullptr), AA(nullptr), LIS(nullptr) {
89 RegClassInfo = new RegisterClassInfo();
92 MachineSchedContext::~MachineSchedContext() {
97 /// Base class for a machine scheduler class that can run at any point.
98 class MachineSchedulerBase : public MachineSchedContext,
99 public MachineFunctionPass {
101 MachineSchedulerBase(char &ID): MachineFunctionPass(ID) {}
103 void print(raw_ostream &O, const Module* = nullptr) const override;
106 void scheduleRegions(ScheduleDAGInstrs &Scheduler);
109 /// MachineScheduler runs after coalescing and before register allocation.
110 class MachineScheduler : public MachineSchedulerBase {
114 void getAnalysisUsage(AnalysisUsage &AU) const override;
116 bool runOnMachineFunction(MachineFunction&) override;
118 static char ID; // Class identification, replacement for typeinfo
121 ScheduleDAGInstrs *createMachineScheduler();
124 /// PostMachineScheduler runs after shortly before code emission.
125 class PostMachineScheduler : public MachineSchedulerBase {
127 PostMachineScheduler();
129 void getAnalysisUsage(AnalysisUsage &AU) const override;
131 bool runOnMachineFunction(MachineFunction&) override;
133 static char ID; // Class identification, replacement for typeinfo
136 ScheduleDAGInstrs *createPostMachineScheduler();
140 char MachineScheduler::ID = 0;
142 char &llvm::MachineSchedulerID = MachineScheduler::ID;
144 INITIALIZE_PASS_BEGIN(MachineScheduler, "misched",
145 "Machine Instruction Scheduler", false, false)
146 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
147 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
148 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
149 INITIALIZE_PASS_END(MachineScheduler, "misched",
150 "Machine Instruction Scheduler", false, false)
152 MachineScheduler::MachineScheduler()
153 : MachineSchedulerBase(ID) {
154 initializeMachineSchedulerPass(*PassRegistry::getPassRegistry());
157 void MachineScheduler::getAnalysisUsage(AnalysisUsage &AU) const {
158 AU.setPreservesCFG();
159 AU.addRequiredID(MachineDominatorsID);
160 AU.addRequired<MachineLoopInfo>();
161 AU.addRequired<AliasAnalysis>();
162 AU.addRequired<TargetPassConfig>();
163 AU.addRequired<SlotIndexes>();
164 AU.addPreserved<SlotIndexes>();
165 AU.addRequired<LiveIntervals>();
166 AU.addPreserved<LiveIntervals>();
167 MachineFunctionPass::getAnalysisUsage(AU);
170 char PostMachineScheduler::ID = 0;
172 char &llvm::PostMachineSchedulerID = PostMachineScheduler::ID;
174 INITIALIZE_PASS(PostMachineScheduler, "postmisched",
175 "PostRA Machine Instruction Scheduler", false, false)
177 PostMachineScheduler::PostMachineScheduler()
178 : MachineSchedulerBase(ID) {
179 initializePostMachineSchedulerPass(*PassRegistry::getPassRegistry());
182 void PostMachineScheduler::getAnalysisUsage(AnalysisUsage &AU) const {
183 AU.setPreservesCFG();
184 AU.addRequiredID(MachineDominatorsID);
185 AU.addRequired<MachineLoopInfo>();
186 AU.addRequired<TargetPassConfig>();
187 MachineFunctionPass::getAnalysisUsage(AU);
190 MachinePassRegistry MachineSchedRegistry::Registry;
192 /// A dummy default scheduler factory indicates whether the scheduler
193 /// is overridden on the command line.
194 static ScheduleDAGInstrs *useDefaultMachineSched(MachineSchedContext *C) {
198 /// MachineSchedOpt allows command line selection of the scheduler.
199 static cl::opt<MachineSchedRegistry::ScheduleDAGCtor, false,
200 RegisterPassParser<MachineSchedRegistry> >
201 MachineSchedOpt("misched",
202 cl::init(&useDefaultMachineSched), cl::Hidden,
203 cl::desc("Machine instruction scheduler to use"));
205 static MachineSchedRegistry
206 DefaultSchedRegistry("default", "Use the target's default scheduler choice.",
207 useDefaultMachineSched);
209 /// Forward declare the standard machine scheduler. This will be used as the
210 /// default scheduler if the target does not set a default.
211 static ScheduleDAGInstrs *createGenericSchedLive(MachineSchedContext *C);
212 static ScheduleDAGInstrs *createGenericSchedPostRA(MachineSchedContext *C);
214 /// Decrement this iterator until reaching the top or a non-debug instr.
215 static MachineBasicBlock::const_iterator
216 priorNonDebug(MachineBasicBlock::const_iterator I,
217 MachineBasicBlock::const_iterator Beg) {
218 assert(I != Beg && "reached the top of the region, cannot decrement");
220 if (!I->isDebugValue())
226 /// Non-const version.
227 static MachineBasicBlock::iterator
228 priorNonDebug(MachineBasicBlock::iterator I,
229 MachineBasicBlock::const_iterator Beg) {
230 return const_cast<MachineInstr*>(
231 &*priorNonDebug(MachineBasicBlock::const_iterator(I), Beg));
234 /// If this iterator is a debug value, increment until reaching the End or a
235 /// non-debug instruction.
236 static MachineBasicBlock::const_iterator
237 nextIfDebug(MachineBasicBlock::const_iterator I,
238 MachineBasicBlock::const_iterator End) {
239 for(; I != End; ++I) {
240 if (!I->isDebugValue())
246 /// Non-const version.
247 static MachineBasicBlock::iterator
248 nextIfDebug(MachineBasicBlock::iterator I,
249 MachineBasicBlock::const_iterator End) {
250 // Cast the return value to nonconst MachineInstr, then cast to an
251 // instr_iterator, which does not check for null, finally return a
253 return MachineBasicBlock::instr_iterator(
254 const_cast<MachineInstr*>(
255 &*nextIfDebug(MachineBasicBlock::const_iterator(I), End)));
258 /// Instantiate a ScheduleDAGInstrs that will be owned by the caller.
259 ScheduleDAGInstrs *MachineScheduler::createMachineScheduler() {
260 // Select the scheduler, or set the default.
261 MachineSchedRegistry::ScheduleDAGCtor Ctor = MachineSchedOpt;
262 if (Ctor != useDefaultMachineSched)
265 // Get the default scheduler set by the target for this function.
266 ScheduleDAGInstrs *Scheduler = PassConfig->createMachineScheduler(this);
270 // Default to GenericScheduler.
271 return createGenericSchedLive(this);
274 /// Instantiate a ScheduleDAGInstrs for PostRA scheduling that will be owned by
275 /// the caller. We don't have a command line option to override the postRA
276 /// scheduler. The Target must configure it.
277 ScheduleDAGInstrs *PostMachineScheduler::createPostMachineScheduler() {
278 // Get the postRA scheduler set by the target for this function.
279 ScheduleDAGInstrs *Scheduler = PassConfig->createPostMachineScheduler(this);
283 // Default to GenericScheduler.
284 return createGenericSchedPostRA(this);
287 /// Top-level MachineScheduler pass driver.
289 /// Visit blocks in function order. Divide each block into scheduling regions
290 /// and visit them bottom-up. Visiting regions bottom-up is not required, but is
291 /// consistent with the DAG builder, which traverses the interior of the
292 /// scheduling regions bottom-up.
294 /// This design avoids exposing scheduling boundaries to the DAG builder,
295 /// simplifying the DAG builder's support for "special" target instructions.
296 /// At the same time the design allows target schedulers to operate across
297 /// scheduling boundaries, for example to bundle the boudary instructions
298 /// without reordering them. This creates complexity, because the target
299 /// scheduler must update the RegionBegin and RegionEnd positions cached by
300 /// ScheduleDAGInstrs whenever adding or removing instructions. A much simpler
301 /// design would be to split blocks at scheduling boundaries, but LLVM has a
302 /// general bias against block splitting purely for implementation simplicity.
303 bool MachineScheduler::runOnMachineFunction(MachineFunction &mf) {
304 DEBUG(dbgs() << "Before MISsched:\n"; mf.print(dbgs()));
306 // Initialize the context of the pass.
308 MLI = &getAnalysis<MachineLoopInfo>();
309 MDT = &getAnalysis<MachineDominatorTree>();
310 PassConfig = &getAnalysis<TargetPassConfig>();
311 AA = &getAnalysis<AliasAnalysis>();
313 LIS = &getAnalysis<LiveIntervals>();
315 if (VerifyScheduling) {
317 MF->verify(this, "Before machine scheduling.");
319 RegClassInfo->runOnMachineFunction(*MF);
321 // Instantiate the selected scheduler for this target, function, and
322 // optimization level.
323 std::unique_ptr<ScheduleDAGInstrs> Scheduler(createMachineScheduler());
324 scheduleRegions(*Scheduler);
327 if (VerifyScheduling)
328 MF->verify(this, "After machine scheduling.");
332 bool PostMachineScheduler::runOnMachineFunction(MachineFunction &mf) {
333 if (skipOptnoneFunction(*mf.getFunction()))
336 const TargetSubtargetInfo &ST =
337 mf.getTarget().getSubtarget<TargetSubtargetInfo>();
338 if (!ST.enablePostMachineScheduler()) {
339 DEBUG(dbgs() << "Subtarget disables post-MI-sched.\n");
342 DEBUG(dbgs() << "Before post-MI-sched:\n"; mf.print(dbgs()));
344 // Initialize the context of the pass.
346 PassConfig = &getAnalysis<TargetPassConfig>();
348 if (VerifyScheduling)
349 MF->verify(this, "Before post machine scheduling.");
351 // Instantiate the selected scheduler for this target, function, and
352 // optimization level.
353 std::unique_ptr<ScheduleDAGInstrs> Scheduler(createPostMachineScheduler());
354 scheduleRegions(*Scheduler);
356 if (VerifyScheduling)
357 MF->verify(this, "After post machine scheduling.");
361 /// Return true of the given instruction should not be included in a scheduling
364 /// MachineScheduler does not currently support scheduling across calls. To
365 /// handle calls, the DAG builder needs to be modified to create register
366 /// anti/output dependencies on the registers clobbered by the call's regmask
367 /// operand. In PreRA scheduling, the stack pointer adjustment already prevents
368 /// scheduling across calls. In PostRA scheduling, we need the isCall to enforce
369 /// the boundary, but there would be no benefit to postRA scheduling across
370 /// calls this late anyway.
371 static bool isSchedBoundary(MachineBasicBlock::iterator MI,
372 MachineBasicBlock *MBB,
374 const TargetInstrInfo *TII,
376 return MI->isCall() || TII->isSchedulingBoundary(MI, MBB, *MF);
379 /// Main driver for both MachineScheduler and PostMachineScheduler.
380 void MachineSchedulerBase::scheduleRegions(ScheduleDAGInstrs &Scheduler) {
381 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
382 bool IsPostRA = Scheduler.isPostRA();
384 // Visit all machine basic blocks.
386 // TODO: Visit blocks in global postorder or postorder within the bottom-up
387 // loop tree. Then we can optionally compute global RegPressure.
388 for (MachineFunction::iterator MBB = MF->begin(), MBBEnd = MF->end();
389 MBB != MBBEnd; ++MBB) {
391 Scheduler.startBlock(MBB);
394 if (SchedOnlyFunc.getNumOccurrences() && SchedOnlyFunc != MF->getName())
396 if (SchedOnlyBlock.getNumOccurrences()
397 && (int)SchedOnlyBlock != MBB->getNumber())
401 // Break the block into scheduling regions [I, RegionEnd), and schedule each
402 // region as soon as it is discovered. RegionEnd points the scheduling
403 // boundary at the bottom of the region. The DAG does not include RegionEnd,
404 // but the region does (i.e. the next RegionEnd is above the previous
405 // RegionBegin). If the current block has no terminator then RegionEnd ==
406 // MBB->end() for the bottom region.
408 // The Scheduler may insert instructions during either schedule() or
409 // exitRegion(), even for empty regions. So the local iterators 'I' and
410 // 'RegionEnd' are invalid across these calls.
412 // MBB::size() uses instr_iterator to count. Here we need a bundle to count
413 // as a single instruction.
414 unsigned RemainingInstrs = std::distance(MBB->begin(), MBB->end());
415 for(MachineBasicBlock::iterator RegionEnd = MBB->end();
416 RegionEnd != MBB->begin(); RegionEnd = Scheduler.begin()) {
418 // Avoid decrementing RegionEnd for blocks with no terminator.
419 if (RegionEnd != MBB->end() ||
420 isSchedBoundary(std::prev(RegionEnd), MBB, MF, TII, IsPostRA)) {
422 // Count the boundary instruction.
426 // The next region starts above the previous region. Look backward in the
427 // instruction stream until we find the nearest boundary.
428 unsigned NumRegionInstrs = 0;
429 MachineBasicBlock::iterator I = RegionEnd;
430 for(;I != MBB->begin(); --I, --RemainingInstrs, ++NumRegionInstrs) {
431 if (isSchedBoundary(std::prev(I), MBB, MF, TII, IsPostRA))
434 // Notify the scheduler of the region, even if we may skip scheduling
435 // it. Perhaps it still needs to be bundled.
436 Scheduler.enterRegion(MBB, I, RegionEnd, NumRegionInstrs);
438 // Skip empty scheduling regions (0 or 1 schedulable instructions).
439 if (I == RegionEnd || I == std::prev(RegionEnd)) {
440 // Close the current region. Bundle the terminator if needed.
441 // This invalidates 'RegionEnd' and 'I'.
442 Scheduler.exitRegion();
445 DEBUG(dbgs() << "********** " << ((Scheduler.isPostRA()) ? "PostRA " : "")
446 << "MI Scheduling **********\n");
447 DEBUG(dbgs() << MF->getName()
448 << ":BB#" << MBB->getNumber() << " " << MBB->getName()
449 << "\n From: " << *I << " To: ";
450 if (RegionEnd != MBB->end()) dbgs() << *RegionEnd;
451 else dbgs() << "End";
452 dbgs() << " RegionInstrs: " << NumRegionInstrs
453 << " Remaining: " << RemainingInstrs << "\n");
455 // Schedule a region: possibly reorder instructions.
456 // This invalidates 'RegionEnd' and 'I'.
457 Scheduler.schedule();
459 // Close the current region.
460 Scheduler.exitRegion();
462 // Scheduling has invalidated the current iterator 'I'. Ask the
463 // scheduler for the top of it's scheduled region.
464 RegionEnd = Scheduler.begin();
466 assert(RemainingInstrs == 0 && "Instruction count mismatch!");
467 Scheduler.finishBlock();
468 if (Scheduler.isPostRA()) {
469 // FIXME: Ideally, no further passes should rely on kill flags. However,
470 // thumb2 size reduction is currently an exception.
471 Scheduler.fixupKills(MBB);
474 Scheduler.finalizeSchedule();
477 void MachineSchedulerBase::print(raw_ostream &O, const Module* m) const {
481 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
482 void ReadyQueue::dump() {
483 dbgs() << Name << ": ";
484 for (unsigned i = 0, e = Queue.size(); i < e; ++i)
485 dbgs() << Queue[i]->NodeNum << " ";
490 //===----------------------------------------------------------------------===//
491 // ScheduleDAGMI - Basic machine instruction scheduling. This is
492 // independent of PreRA/PostRA scheduling and involves no extra book-keeping for
493 // virtual registers.
494 // ===----------------------------------------------------------------------===/
496 // Provide a vtable anchor.
497 ScheduleDAGMI::~ScheduleDAGMI() {
500 bool ScheduleDAGMI::canAddEdge(SUnit *SuccSU, SUnit *PredSU) {
501 return SuccSU == &ExitSU || !Topo.IsReachable(PredSU, SuccSU);
504 bool ScheduleDAGMI::addEdge(SUnit *SuccSU, const SDep &PredDep) {
505 if (SuccSU != &ExitSU) {
506 // Do not use WillCreateCycle, it assumes SD scheduling.
507 // If Pred is reachable from Succ, then the edge creates a cycle.
508 if (Topo.IsReachable(PredDep.getSUnit(), SuccSU))
510 Topo.AddPred(SuccSU, PredDep.getSUnit());
512 SuccSU->addPred(PredDep, /*Required=*/!PredDep.isArtificial());
513 // Return true regardless of whether a new edge needed to be inserted.
517 /// ReleaseSucc - Decrement the NumPredsLeft count of a successor. When
518 /// NumPredsLeft reaches zero, release the successor node.
520 /// FIXME: Adjust SuccSU height based on MinLatency.
521 void ScheduleDAGMI::releaseSucc(SUnit *SU, SDep *SuccEdge) {
522 SUnit *SuccSU = SuccEdge->getSUnit();
524 if (SuccEdge->isWeak()) {
525 --SuccSU->WeakPredsLeft;
526 if (SuccEdge->isCluster())
527 NextClusterSucc = SuccSU;
531 if (SuccSU->NumPredsLeft == 0) {
532 dbgs() << "*** Scheduling failed! ***\n";
534 dbgs() << " has been released too many times!\n";
535 llvm_unreachable(nullptr);
538 // SU->TopReadyCycle was set to CurrCycle when it was scheduled. However,
539 // CurrCycle may have advanced since then.
540 if (SuccSU->TopReadyCycle < SU->TopReadyCycle + SuccEdge->getLatency())
541 SuccSU->TopReadyCycle = SU->TopReadyCycle + SuccEdge->getLatency();
543 --SuccSU->NumPredsLeft;
544 if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU)
545 SchedImpl->releaseTopNode(SuccSU);
548 /// releaseSuccessors - Call releaseSucc on each of SU's successors.
549 void ScheduleDAGMI::releaseSuccessors(SUnit *SU) {
550 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
552 releaseSucc(SU, &*I);
556 /// ReleasePred - Decrement the NumSuccsLeft count of a predecessor. When
557 /// NumSuccsLeft reaches zero, release the predecessor node.
559 /// FIXME: Adjust PredSU height based on MinLatency.
560 void ScheduleDAGMI::releasePred(SUnit *SU, SDep *PredEdge) {
561 SUnit *PredSU = PredEdge->getSUnit();
563 if (PredEdge->isWeak()) {
564 --PredSU->WeakSuccsLeft;
565 if (PredEdge->isCluster())
566 NextClusterPred = PredSU;
570 if (PredSU->NumSuccsLeft == 0) {
571 dbgs() << "*** Scheduling failed! ***\n";
573 dbgs() << " has been released too many times!\n";
574 llvm_unreachable(nullptr);
577 // SU->BotReadyCycle was set to CurrCycle when it was scheduled. However,
578 // CurrCycle may have advanced since then.
579 if (PredSU->BotReadyCycle < SU->BotReadyCycle + PredEdge->getLatency())
580 PredSU->BotReadyCycle = SU->BotReadyCycle + PredEdge->getLatency();
582 --PredSU->NumSuccsLeft;
583 if (PredSU->NumSuccsLeft == 0 && PredSU != &EntrySU)
584 SchedImpl->releaseBottomNode(PredSU);
587 /// releasePredecessors - Call releasePred on each of SU's predecessors.
588 void ScheduleDAGMI::releasePredecessors(SUnit *SU) {
589 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
591 releasePred(SU, &*I);
595 /// enterRegion - Called back from MachineScheduler::runOnMachineFunction after
596 /// crossing a scheduling boundary. [begin, end) includes all instructions in
597 /// the region, including the boundary itself and single-instruction regions
598 /// that don't get scheduled.
599 void ScheduleDAGMI::enterRegion(MachineBasicBlock *bb,
600 MachineBasicBlock::iterator begin,
601 MachineBasicBlock::iterator end,
602 unsigned regioninstrs)
604 ScheduleDAGInstrs::enterRegion(bb, begin, end, regioninstrs);
606 SchedImpl->initPolicy(begin, end, regioninstrs);
609 /// This is normally called from the main scheduler loop but may also be invoked
610 /// by the scheduling strategy to perform additional code motion.
611 void ScheduleDAGMI::moveInstruction(
612 MachineInstr *MI, MachineBasicBlock::iterator InsertPos) {
613 // Advance RegionBegin if the first instruction moves down.
614 if (&*RegionBegin == MI)
617 // Update the instruction stream.
618 BB->splice(InsertPos, BB, MI);
620 // Update LiveIntervals
622 LIS->handleMove(MI, /*UpdateFlags=*/true);
624 // Recede RegionBegin if an instruction moves above the first.
625 if (RegionBegin == InsertPos)
629 bool ScheduleDAGMI::checkSchedLimit() {
631 if (NumInstrsScheduled == MISchedCutoff && MISchedCutoff != ~0U) {
632 CurrentTop = CurrentBottom;
635 ++NumInstrsScheduled;
640 /// Per-region scheduling driver, called back from
641 /// MachineScheduler::runOnMachineFunction. This is a simplified driver that
642 /// does not consider liveness or register pressure. It is useful for PostRA
643 /// scheduling and potentially other custom schedulers.
644 void ScheduleDAGMI::schedule() {
648 Topo.InitDAGTopologicalSorting();
652 SmallVector<SUnit*, 8> TopRoots, BotRoots;
653 findRootsAndBiasEdges(TopRoots, BotRoots);
655 // Initialize the strategy before modifying the DAG.
656 // This may initialize a DFSResult to be used for queue priority.
657 SchedImpl->initialize(this);
659 DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
660 SUnits[su].dumpAll(this));
661 if (ViewMISchedDAGs) viewGraph();
663 // Initialize ready queues now that the DAG and priority data are finalized.
664 initQueues(TopRoots, BotRoots);
666 bool IsTopNode = false;
667 while (SUnit *SU = SchedImpl->pickNode(IsTopNode)) {
668 assert(!SU->isScheduled && "Node already scheduled");
669 if (!checkSchedLimit())
672 MachineInstr *MI = SU->getInstr();
674 assert(SU->isTopReady() && "node still has unscheduled dependencies");
675 if (&*CurrentTop == MI)
676 CurrentTop = nextIfDebug(++CurrentTop, CurrentBottom);
678 moveInstruction(MI, CurrentTop);
681 assert(SU->isBottomReady() && "node still has unscheduled dependencies");
682 MachineBasicBlock::iterator priorII =
683 priorNonDebug(CurrentBottom, CurrentTop);
685 CurrentBottom = priorII;
687 if (&*CurrentTop == MI)
688 CurrentTop = nextIfDebug(++CurrentTop, priorII);
689 moveInstruction(MI, CurrentBottom);
693 // Notify the scheduling strategy before updating the DAG.
694 // This sets the scheduled nodes ReadyCycle to CurrCycle. When updateQueues
695 // runs, it can then use the accurate ReadyCycle time to determine whether
696 // newly released nodes can move to the readyQ.
697 SchedImpl->schedNode(SU, IsTopNode);
699 updateQueues(SU, IsTopNode);
701 assert(CurrentTop == CurrentBottom && "Nonempty unscheduled zone.");
706 unsigned BBNum = begin()->getParent()->getNumber();
707 dbgs() << "*** Final schedule for BB#" << BBNum << " ***\n";
713 /// Apply each ScheduleDAGMutation step in order.
714 void ScheduleDAGMI::postprocessDAG() {
715 for (unsigned i = 0, e = Mutations.size(); i < e; ++i) {
716 Mutations[i]->apply(this);
721 findRootsAndBiasEdges(SmallVectorImpl<SUnit*> &TopRoots,
722 SmallVectorImpl<SUnit*> &BotRoots) {
723 for (std::vector<SUnit>::iterator
724 I = SUnits.begin(), E = SUnits.end(); I != E; ++I) {
726 assert(!SU->isBoundaryNode() && "Boundary node should not be in SUnits");
728 // Order predecessors so DFSResult follows the critical path.
729 SU->biasCriticalPath();
731 // A SUnit is ready to top schedule if it has no predecessors.
732 if (!I->NumPredsLeft)
733 TopRoots.push_back(SU);
734 // A SUnit is ready to bottom schedule if it has no successors.
735 if (!I->NumSuccsLeft)
736 BotRoots.push_back(SU);
738 ExitSU.biasCriticalPath();
741 /// Identify DAG roots and setup scheduler queues.
742 void ScheduleDAGMI::initQueues(ArrayRef<SUnit*> TopRoots,
743 ArrayRef<SUnit*> BotRoots) {
744 NextClusterSucc = nullptr;
745 NextClusterPred = nullptr;
747 // Release all DAG roots for scheduling, not including EntrySU/ExitSU.
749 // Nodes with unreleased weak edges can still be roots.
750 // Release top roots in forward order.
751 for (SmallVectorImpl<SUnit*>::const_iterator
752 I = TopRoots.begin(), E = TopRoots.end(); I != E; ++I) {
753 SchedImpl->releaseTopNode(*I);
755 // Release bottom roots in reverse order so the higher priority nodes appear
756 // first. This is more natural and slightly more efficient.
757 for (SmallVectorImpl<SUnit*>::const_reverse_iterator
758 I = BotRoots.rbegin(), E = BotRoots.rend(); I != E; ++I) {
759 SchedImpl->releaseBottomNode(*I);
762 releaseSuccessors(&EntrySU);
763 releasePredecessors(&ExitSU);
765 SchedImpl->registerRoots();
767 // Advance past initial DebugValues.
768 CurrentTop = nextIfDebug(RegionBegin, RegionEnd);
769 CurrentBottom = RegionEnd;
772 /// Update scheduler queues after scheduling an instruction.
773 void ScheduleDAGMI::updateQueues(SUnit *SU, bool IsTopNode) {
774 // Release dependent instructions for scheduling.
776 releaseSuccessors(SU);
778 releasePredecessors(SU);
780 SU->isScheduled = true;
783 /// Reinsert any remaining debug_values, just like the PostRA scheduler.
784 void ScheduleDAGMI::placeDebugValues() {
785 // If first instruction was a DBG_VALUE then put it back.
787 BB->splice(RegionBegin, BB, FirstDbgValue);
788 RegionBegin = FirstDbgValue;
791 for (std::vector<std::pair<MachineInstr *, MachineInstr *> >::iterator
792 DI = DbgValues.end(), DE = DbgValues.begin(); DI != DE; --DI) {
793 std::pair<MachineInstr *, MachineInstr *> P = *std::prev(DI);
794 MachineInstr *DbgValue = P.first;
795 MachineBasicBlock::iterator OrigPrevMI = P.second;
796 if (&*RegionBegin == DbgValue)
798 BB->splice(++OrigPrevMI, BB, DbgValue);
799 if (OrigPrevMI == std::prev(RegionEnd))
800 RegionEnd = DbgValue;
803 FirstDbgValue = nullptr;
806 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
807 void ScheduleDAGMI::dumpSchedule() const {
808 for (MachineBasicBlock::iterator MI = begin(), ME = end(); MI != ME; ++MI) {
809 if (SUnit *SU = getSUnit(&(*MI)))
812 dbgs() << "Missing SUnit\n";
817 //===----------------------------------------------------------------------===//
818 // ScheduleDAGMILive - Base class for MachineInstr scheduling with LiveIntervals
820 //===----------------------------------------------------------------------===//
822 ScheduleDAGMILive::~ScheduleDAGMILive() {
826 /// enterRegion - Called back from MachineScheduler::runOnMachineFunction after
827 /// crossing a scheduling boundary. [begin, end) includes all instructions in
828 /// the region, including the boundary itself and single-instruction regions
829 /// that don't get scheduled.
830 void ScheduleDAGMILive::enterRegion(MachineBasicBlock *bb,
831 MachineBasicBlock::iterator begin,
832 MachineBasicBlock::iterator end,
833 unsigned regioninstrs)
835 // ScheduleDAGMI initializes SchedImpl's per-region policy.
836 ScheduleDAGMI::enterRegion(bb, begin, end, regioninstrs);
838 // For convenience remember the end of the liveness region.
839 LiveRegionEnd = (RegionEnd == bb->end()) ? RegionEnd : std::next(RegionEnd);
841 SUPressureDiffs.clear();
843 ShouldTrackPressure = SchedImpl->shouldTrackPressure();
846 // Setup the register pressure trackers for the top scheduled top and bottom
847 // scheduled regions.
848 void ScheduleDAGMILive::initRegPressure() {
849 TopRPTracker.init(&MF, RegClassInfo, LIS, BB, RegionBegin);
850 BotRPTracker.init(&MF, RegClassInfo, LIS, BB, LiveRegionEnd);
852 // Close the RPTracker to finalize live ins.
853 RPTracker.closeRegion();
855 DEBUG(RPTracker.dump());
857 // Initialize the live ins and live outs.
858 TopRPTracker.addLiveRegs(RPTracker.getPressure().LiveInRegs);
859 BotRPTracker.addLiveRegs(RPTracker.getPressure().LiveOutRegs);
861 // Close one end of the tracker so we can call
862 // getMaxUpward/DownwardPressureDelta before advancing across any
863 // instructions. This converts currently live regs into live ins/outs.
864 TopRPTracker.closeTop();
865 BotRPTracker.closeBottom();
867 BotRPTracker.initLiveThru(RPTracker);
868 if (!BotRPTracker.getLiveThru().empty()) {
869 TopRPTracker.initLiveThru(BotRPTracker.getLiveThru());
870 DEBUG(dbgs() << "Live Thru: ";
871 dumpRegSetPressure(BotRPTracker.getLiveThru(), TRI));
874 // For each live out vreg reduce the pressure change associated with other
875 // uses of the same vreg below the live-out reaching def.
876 updatePressureDiffs(RPTracker.getPressure().LiveOutRegs);
878 // Account for liveness generated by the region boundary.
879 if (LiveRegionEnd != RegionEnd) {
880 SmallVector<unsigned, 8> LiveUses;
881 BotRPTracker.recede(&LiveUses);
882 updatePressureDiffs(LiveUses);
885 assert(BotRPTracker.getPos() == RegionEnd && "Can't find the region bottom");
887 // Cache the list of excess pressure sets in this region. This will also track
888 // the max pressure in the scheduled code for these sets.
889 RegionCriticalPSets.clear();
890 const std::vector<unsigned> &RegionPressure =
891 RPTracker.getPressure().MaxSetPressure;
892 for (unsigned i = 0, e = RegionPressure.size(); i < e; ++i) {
893 unsigned Limit = RegClassInfo->getRegPressureSetLimit(i);
894 if (RegionPressure[i] > Limit) {
895 DEBUG(dbgs() << TRI->getRegPressureSetName(i)
896 << " Limit " << Limit
897 << " Actual " << RegionPressure[i] << "\n");
898 RegionCriticalPSets.push_back(PressureChange(i));
901 DEBUG(dbgs() << "Excess PSets: ";
902 for (unsigned i = 0, e = RegionCriticalPSets.size(); i != e; ++i)
903 dbgs() << TRI->getRegPressureSetName(
904 RegionCriticalPSets[i].getPSet()) << " ";
908 void ScheduleDAGMILive::
909 updateScheduledPressure(const SUnit *SU,
910 const std::vector<unsigned> &NewMaxPressure) {
911 const PressureDiff &PDiff = getPressureDiff(SU);
912 unsigned CritIdx = 0, CritEnd = RegionCriticalPSets.size();
913 for (PressureDiff::const_iterator I = PDiff.begin(), E = PDiff.end();
917 unsigned ID = I->getPSet();
918 while (CritIdx != CritEnd && RegionCriticalPSets[CritIdx].getPSet() < ID)
920 if (CritIdx != CritEnd && RegionCriticalPSets[CritIdx].getPSet() == ID) {
921 if ((int)NewMaxPressure[ID] > RegionCriticalPSets[CritIdx].getUnitInc()
922 && NewMaxPressure[ID] <= INT16_MAX)
923 RegionCriticalPSets[CritIdx].setUnitInc(NewMaxPressure[ID]);
925 unsigned Limit = RegClassInfo->getRegPressureSetLimit(ID);
926 if (NewMaxPressure[ID] >= Limit - 2) {
927 DEBUG(dbgs() << " " << TRI->getRegPressureSetName(ID) << ": "
928 << NewMaxPressure[ID] << " > " << Limit << "(+ "
929 << BotRPTracker.getLiveThru()[ID] << " livethru)\n");
934 /// Update the PressureDiff array for liveness after scheduling this
936 void ScheduleDAGMILive::updatePressureDiffs(ArrayRef<unsigned> LiveUses) {
937 for (unsigned LUIdx = 0, LUEnd = LiveUses.size(); LUIdx != LUEnd; ++LUIdx) {
938 /// FIXME: Currently assuming single-use physregs.
939 unsigned Reg = LiveUses[LUIdx];
940 DEBUG(dbgs() << " LiveReg: " << PrintVRegOrUnit(Reg, TRI) << "\n");
941 if (!TRI->isVirtualRegister(Reg))
944 // This may be called before CurrentBottom has been initialized. However,
945 // BotRPTracker must have a valid position. We want the value live into the
946 // instruction or live out of the block, so ask for the previous
947 // instruction's live-out.
948 const LiveInterval &LI = LIS->getInterval(Reg);
950 MachineBasicBlock::const_iterator I =
951 nextIfDebug(BotRPTracker.getPos(), BB->end());
953 VNI = LI.getVNInfoBefore(LIS->getMBBEndIdx(BB));
955 LiveQueryResult LRQ = LI.Query(LIS->getInstructionIndex(I));
958 // RegisterPressureTracker guarantees that readsReg is true for LiveUses.
959 assert(VNI && "No live value at use.");
960 for (VReg2UseMap::iterator
961 UI = VRegUses.find(Reg); UI != VRegUses.end(); ++UI) {
963 DEBUG(dbgs() << " UpdateRegP: SU(" << SU->NodeNum << ") "
965 // If this use comes before the reaching def, it cannot be a last use, so
966 // descrease its pressure change.
967 if (!SU->isScheduled && SU != &ExitSU) {
969 = LI.Query(LIS->getInstructionIndex(SU->getInstr()));
970 if (LRQ.valueIn() == VNI)
971 getPressureDiff(SU).addPressureChange(Reg, true, &MRI);
977 /// schedule - Called back from MachineScheduler::runOnMachineFunction
978 /// after setting up the current scheduling region. [RegionBegin, RegionEnd)
979 /// only includes instructions that have DAG nodes, not scheduling boundaries.
981 /// This is a skeletal driver, with all the functionality pushed into helpers,
982 /// so that it can be easilly extended by experimental schedulers. Generally,
983 /// implementing MachineSchedStrategy should be sufficient to implement a new
984 /// scheduling algorithm. However, if a scheduler further subclasses
985 /// ScheduleDAGMILive then it will want to override this virtual method in order
986 /// to update any specialized state.
987 void ScheduleDAGMILive::schedule() {
988 buildDAGWithRegPressure();
990 Topo.InitDAGTopologicalSorting();
994 SmallVector<SUnit*, 8> TopRoots, BotRoots;
995 findRootsAndBiasEdges(TopRoots, BotRoots);
997 // Initialize the strategy before modifying the DAG.
998 // This may initialize a DFSResult to be used for queue priority.
999 SchedImpl->initialize(this);
1001 DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
1002 SUnits[su].dumpAll(this));
1003 if (ViewMISchedDAGs) viewGraph();
1005 // Initialize ready queues now that the DAG and priority data are finalized.
1006 initQueues(TopRoots, BotRoots);
1008 if (ShouldTrackPressure) {
1009 assert(TopRPTracker.getPos() == RegionBegin && "bad initial Top tracker");
1010 TopRPTracker.setPos(CurrentTop);
1013 bool IsTopNode = false;
1014 while (SUnit *SU = SchedImpl->pickNode(IsTopNode)) {
1015 assert(!SU->isScheduled && "Node already scheduled");
1016 if (!checkSchedLimit())
1019 scheduleMI(SU, IsTopNode);
1021 updateQueues(SU, IsTopNode);
1024 unsigned SubtreeID = DFSResult->getSubtreeID(SU);
1025 if (!ScheduledTrees.test(SubtreeID)) {
1026 ScheduledTrees.set(SubtreeID);
1027 DFSResult->scheduleTree(SubtreeID);
1028 SchedImpl->scheduleTree(SubtreeID);
1032 // Notify the scheduling strategy after updating the DAG.
1033 SchedImpl->schedNode(SU, IsTopNode);
1035 assert(CurrentTop == CurrentBottom && "Nonempty unscheduled zone.");
1040 unsigned BBNum = begin()->getParent()->getNumber();
1041 dbgs() << "*** Final schedule for BB#" << BBNum << " ***\n";
1047 /// Build the DAG and setup three register pressure trackers.
1048 void ScheduleDAGMILive::buildDAGWithRegPressure() {
1049 if (!ShouldTrackPressure) {
1051 RegionCriticalPSets.clear();
1052 buildSchedGraph(AA);
1056 // Initialize the register pressure tracker used by buildSchedGraph.
1057 RPTracker.init(&MF, RegClassInfo, LIS, BB, LiveRegionEnd,
1058 /*TrackUntiedDefs=*/true);
1060 // Account for liveness generate by the region boundary.
1061 if (LiveRegionEnd != RegionEnd)
1064 // Build the DAG, and compute current register pressure.
1065 buildSchedGraph(AA, &RPTracker, &SUPressureDiffs);
1067 // Initialize top/bottom trackers after computing region pressure.
1071 void ScheduleDAGMILive::computeDFSResult() {
1073 DFSResult = new SchedDFSResult(/*BottomU*/true, MinSubtreeSize);
1075 ScheduledTrees.clear();
1076 DFSResult->resize(SUnits.size());
1077 DFSResult->compute(SUnits);
1078 ScheduledTrees.resize(DFSResult->getNumSubtrees());
1081 /// Compute the max cyclic critical path through the DAG. The scheduling DAG
1082 /// only provides the critical path for single block loops. To handle loops that
1083 /// span blocks, we could use the vreg path latencies provided by
1084 /// MachineTraceMetrics instead. However, MachineTraceMetrics is not currently
1085 /// available for use in the scheduler.
1087 /// The cyclic path estimation identifies a def-use pair that crosses the back
1088 /// edge and considers the depth and height of the nodes. For example, consider
1089 /// the following instruction sequence where each instruction has unit latency
1090 /// and defines an epomymous virtual register:
1092 /// a->b(a,c)->c(b)->d(c)->exit
1094 /// The cyclic critical path is a two cycles: b->c->b
1095 /// The acyclic critical path is four cycles: a->b->c->d->exit
1096 /// LiveOutHeight = height(c) = len(c->d->exit) = 2
1097 /// LiveOutDepth = depth(c) + 1 = len(a->b->c) + 1 = 3
1098 /// LiveInHeight = height(b) + 1 = len(b->c->d->exit) + 1 = 4
1099 /// LiveInDepth = depth(b) = len(a->b) = 1
1101 /// LiveOutDepth - LiveInDepth = 3 - 1 = 2
1102 /// LiveInHeight - LiveOutHeight = 4 - 2 = 2
1103 /// CyclicCriticalPath = min(2, 2) = 2
1105 /// This could be relevant to PostRA scheduling, but is currently implemented
1106 /// assuming LiveIntervals.
1107 unsigned ScheduleDAGMILive::computeCyclicCriticalPath() {
1108 // This only applies to single block loop.
1109 if (!BB->isSuccessor(BB))
1112 unsigned MaxCyclicLatency = 0;
1113 // Visit each live out vreg def to find def/use pairs that cross iterations.
1114 ArrayRef<unsigned> LiveOuts = RPTracker.getPressure().LiveOutRegs;
1115 for (ArrayRef<unsigned>::iterator RI = LiveOuts.begin(), RE = LiveOuts.end();
1118 if (!TRI->isVirtualRegister(Reg))
1120 const LiveInterval &LI = LIS->getInterval(Reg);
1121 const VNInfo *DefVNI = LI.getVNInfoBefore(LIS->getMBBEndIdx(BB));
1125 MachineInstr *DefMI = LIS->getInstructionFromIndex(DefVNI->def);
1126 const SUnit *DefSU = getSUnit(DefMI);
1130 unsigned LiveOutHeight = DefSU->getHeight();
1131 unsigned LiveOutDepth = DefSU->getDepth() + DefSU->Latency;
1132 // Visit all local users of the vreg def.
1133 for (VReg2UseMap::iterator
1134 UI = VRegUses.find(Reg); UI != VRegUses.end(); ++UI) {
1135 if (UI->SU == &ExitSU)
1138 // Only consider uses of the phi.
1139 LiveQueryResult LRQ =
1140 LI.Query(LIS->getInstructionIndex(UI->SU->getInstr()));
1141 if (!LRQ.valueIn()->isPHIDef())
1144 // Assume that a path spanning two iterations is a cycle, which could
1145 // overestimate in strange cases. This allows cyclic latency to be
1146 // estimated as the minimum slack of the vreg's depth or height.
1147 unsigned CyclicLatency = 0;
1148 if (LiveOutDepth > UI->SU->getDepth())
1149 CyclicLatency = LiveOutDepth - UI->SU->getDepth();
1151 unsigned LiveInHeight = UI->SU->getHeight() + DefSU->Latency;
1152 if (LiveInHeight > LiveOutHeight) {
1153 if (LiveInHeight - LiveOutHeight < CyclicLatency)
1154 CyclicLatency = LiveInHeight - LiveOutHeight;
1159 DEBUG(dbgs() << "Cyclic Path: SU(" << DefSU->NodeNum << ") -> SU("
1160 << UI->SU->NodeNum << ") = " << CyclicLatency << "c\n");
1161 if (CyclicLatency > MaxCyclicLatency)
1162 MaxCyclicLatency = CyclicLatency;
1165 DEBUG(dbgs() << "Cyclic Critical Path: " << MaxCyclicLatency << "c\n");
1166 return MaxCyclicLatency;
1169 /// Move an instruction and update register pressure.
1170 void ScheduleDAGMILive::scheduleMI(SUnit *SU, bool IsTopNode) {
1171 // Move the instruction to its new location in the instruction stream.
1172 MachineInstr *MI = SU->getInstr();
1175 assert(SU->isTopReady() && "node still has unscheduled dependencies");
1176 if (&*CurrentTop == MI)
1177 CurrentTop = nextIfDebug(++CurrentTop, CurrentBottom);
1179 moveInstruction(MI, CurrentTop);
1180 TopRPTracker.setPos(MI);
1183 if (ShouldTrackPressure) {
1184 // Update top scheduled pressure.
1185 TopRPTracker.advance();
1186 assert(TopRPTracker.getPos() == CurrentTop && "out of sync");
1187 updateScheduledPressure(SU, TopRPTracker.getPressure().MaxSetPressure);
1191 assert(SU->isBottomReady() && "node still has unscheduled dependencies");
1192 MachineBasicBlock::iterator priorII =
1193 priorNonDebug(CurrentBottom, CurrentTop);
1194 if (&*priorII == MI)
1195 CurrentBottom = priorII;
1197 if (&*CurrentTop == MI) {
1198 CurrentTop = nextIfDebug(++CurrentTop, priorII);
1199 TopRPTracker.setPos(CurrentTop);
1201 moveInstruction(MI, CurrentBottom);
1204 if (ShouldTrackPressure) {
1205 // Update bottom scheduled pressure.
1206 SmallVector<unsigned, 8> LiveUses;
1207 BotRPTracker.recede(&LiveUses);
1208 assert(BotRPTracker.getPos() == CurrentBottom && "out of sync");
1209 updateScheduledPressure(SU, BotRPTracker.getPressure().MaxSetPressure);
1210 updatePressureDiffs(LiveUses);
1215 //===----------------------------------------------------------------------===//
1216 // LoadClusterMutation - DAG post-processing to cluster loads.
1217 //===----------------------------------------------------------------------===//
1220 /// \brief Post-process the DAG to create cluster edges between neighboring
1222 class LoadClusterMutation : public ScheduleDAGMutation {
1227 LoadInfo(SUnit *su, unsigned reg, unsigned ofs)
1228 : SU(su), BaseReg(reg), Offset(ofs) {}
1230 bool operator<(const LoadInfo &RHS) const {
1231 return std::tie(BaseReg, Offset) < std::tie(RHS.BaseReg, RHS.Offset);
1235 const TargetInstrInfo *TII;
1236 const TargetRegisterInfo *TRI;
1238 LoadClusterMutation(const TargetInstrInfo *tii,
1239 const TargetRegisterInfo *tri)
1240 : TII(tii), TRI(tri) {}
1242 void apply(ScheduleDAGMI *DAG) override;
1244 void clusterNeighboringLoads(ArrayRef<SUnit*> Loads, ScheduleDAGMI *DAG);
1248 void LoadClusterMutation::clusterNeighboringLoads(ArrayRef<SUnit*> Loads,
1249 ScheduleDAGMI *DAG) {
1250 SmallVector<LoadClusterMutation::LoadInfo,32> LoadRecords;
1251 for (unsigned Idx = 0, End = Loads.size(); Idx != End; ++Idx) {
1252 SUnit *SU = Loads[Idx];
1255 if (TII->getLdStBaseRegImmOfs(SU->getInstr(), BaseReg, Offset, TRI))
1256 LoadRecords.push_back(LoadInfo(SU, BaseReg, Offset));
1258 if (LoadRecords.size() < 2)
1260 std::sort(LoadRecords.begin(), LoadRecords.end());
1261 unsigned ClusterLength = 1;
1262 for (unsigned Idx = 0, End = LoadRecords.size(); Idx < (End - 1); ++Idx) {
1263 if (LoadRecords[Idx].BaseReg != LoadRecords[Idx+1].BaseReg) {
1268 SUnit *SUa = LoadRecords[Idx].SU;
1269 SUnit *SUb = LoadRecords[Idx+1].SU;
1270 if (TII->shouldClusterLoads(SUa->getInstr(), SUb->getInstr(), ClusterLength)
1271 && DAG->addEdge(SUb, SDep(SUa, SDep::Cluster))) {
1273 DEBUG(dbgs() << "Cluster loads SU(" << SUa->NodeNum << ") - SU("
1274 << SUb->NodeNum << ")\n");
1275 // Copy successor edges from SUa to SUb. Interleaving computation
1276 // dependent on SUa can prevent load combining due to register reuse.
1277 // Predecessor edges do not need to be copied from SUb to SUa since nearby
1278 // loads should have effectively the same inputs.
1279 for (SUnit::const_succ_iterator
1280 SI = SUa->Succs.begin(), SE = SUa->Succs.end(); SI != SE; ++SI) {
1281 if (SI->getSUnit() == SUb)
1283 DEBUG(dbgs() << " Copy Succ SU(" << SI->getSUnit()->NodeNum << ")\n");
1284 DAG->addEdge(SI->getSUnit(), SDep(SUb, SDep::Artificial));
1293 /// \brief Callback from DAG postProcessing to create cluster edges for loads.
1294 void LoadClusterMutation::apply(ScheduleDAGMI *DAG) {
1295 // Map DAG NodeNum to store chain ID.
1296 DenseMap<unsigned, unsigned> StoreChainIDs;
1297 // Map each store chain to a set of dependent loads.
1298 SmallVector<SmallVector<SUnit*,4>, 32> StoreChainDependents;
1299 for (unsigned Idx = 0, End = DAG->SUnits.size(); Idx != End; ++Idx) {
1300 SUnit *SU = &DAG->SUnits[Idx];
1301 if (!SU->getInstr()->mayLoad())
1303 unsigned ChainPredID = DAG->SUnits.size();
1304 for (SUnit::const_pred_iterator
1305 PI = SU->Preds.begin(), PE = SU->Preds.end(); PI != PE; ++PI) {
1307 ChainPredID = PI->getSUnit()->NodeNum;
1311 // Check if this chain-like pred has been seen
1312 // before. ChainPredID==MaxNodeID for loads at the top of the schedule.
1313 unsigned NumChains = StoreChainDependents.size();
1314 std::pair<DenseMap<unsigned, unsigned>::iterator, bool> Result =
1315 StoreChainIDs.insert(std::make_pair(ChainPredID, NumChains));
1317 StoreChainDependents.resize(NumChains + 1);
1318 StoreChainDependents[Result.first->second].push_back(SU);
1320 // Iterate over the store chains.
1321 for (unsigned Idx = 0, End = StoreChainDependents.size(); Idx != End; ++Idx)
1322 clusterNeighboringLoads(StoreChainDependents[Idx], DAG);
1325 //===----------------------------------------------------------------------===//
1326 // MacroFusion - DAG post-processing to encourage fusion of macro ops.
1327 //===----------------------------------------------------------------------===//
1330 /// \brief Post-process the DAG to create cluster edges between instructions
1331 /// that may be fused by the processor into a single operation.
1332 class MacroFusion : public ScheduleDAGMutation {
1333 const TargetInstrInfo *TII;
1335 MacroFusion(const TargetInstrInfo *tii): TII(tii) {}
1337 void apply(ScheduleDAGMI *DAG) override;
1341 /// \brief Callback from DAG postProcessing to create cluster edges to encourage
1342 /// fused operations.
1343 void MacroFusion::apply(ScheduleDAGMI *DAG) {
1344 // For now, assume targets can only fuse with the branch.
1345 MachineInstr *Branch = DAG->ExitSU.getInstr();
1349 for (unsigned Idx = DAG->SUnits.size(); Idx > 0;) {
1350 SUnit *SU = &DAG->SUnits[--Idx];
1351 if (!TII->shouldScheduleAdjacent(SU->getInstr(), Branch))
1354 // Create a single weak edge from SU to ExitSU. The only effect is to cause
1355 // bottom-up scheduling to heavily prioritize the clustered SU. There is no
1356 // need to copy predecessor edges from ExitSU to SU, since top-down
1357 // scheduling cannot prioritize ExitSU anyway. To defer top-down scheduling
1358 // of SU, we could create an artificial edge from the deepest root, but it
1359 // hasn't been needed yet.
1360 bool Success = DAG->addEdge(&DAG->ExitSU, SDep(SU, SDep::Cluster));
1362 assert(Success && "No DAG nodes should be reachable from ExitSU");
1364 DEBUG(dbgs() << "Macro Fuse SU(" << SU->NodeNum << ")\n");
1369 //===----------------------------------------------------------------------===//
1370 // CopyConstrain - DAG post-processing to encourage copy elimination.
1371 //===----------------------------------------------------------------------===//
1374 /// \brief Post-process the DAG to create weak edges from all uses of a copy to
1375 /// the one use that defines the copy's source vreg, most likely an induction
1376 /// variable increment.
1377 class CopyConstrain : public ScheduleDAGMutation {
1379 SlotIndex RegionBeginIdx;
1380 // RegionEndIdx is the slot index of the last non-debug instruction in the
1381 // scheduling region. So we may have RegionBeginIdx == RegionEndIdx.
1382 SlotIndex RegionEndIdx;
1384 CopyConstrain(const TargetInstrInfo *, const TargetRegisterInfo *) {}
1386 void apply(ScheduleDAGMI *DAG) override;
1389 void constrainLocalCopy(SUnit *CopySU, ScheduleDAGMILive *DAG);
1393 /// constrainLocalCopy handles two possibilities:
1398 /// I3: dst = src (copy)
1399 /// (create pred->succ edges I0->I1, I2->I1)
1402 /// I0: dst = src (copy)
1406 /// (create pred->succ edges I1->I2, I3->I2)
1408 /// Although the MachineScheduler is currently constrained to single blocks,
1409 /// this algorithm should handle extended blocks. An EBB is a set of
1410 /// contiguously numbered blocks such that the previous block in the EBB is
1411 /// always the single predecessor.
1412 void CopyConstrain::constrainLocalCopy(SUnit *CopySU, ScheduleDAGMILive *DAG) {
1413 LiveIntervals *LIS = DAG->getLIS();
1414 MachineInstr *Copy = CopySU->getInstr();
1416 // Check for pure vreg copies.
1417 unsigned SrcReg = Copy->getOperand(1).getReg();
1418 if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
1421 unsigned DstReg = Copy->getOperand(0).getReg();
1422 if (!TargetRegisterInfo::isVirtualRegister(DstReg))
1425 // Check if either the dest or source is local. If it's live across a back
1426 // edge, it's not local. Note that if both vregs are live across the back
1427 // edge, we cannot successfully contrain the copy without cyclic scheduling.
1428 unsigned LocalReg = DstReg;
1429 unsigned GlobalReg = SrcReg;
1430 LiveInterval *LocalLI = &LIS->getInterval(LocalReg);
1431 if (!LocalLI->isLocal(RegionBeginIdx, RegionEndIdx)) {
1434 LocalLI = &LIS->getInterval(LocalReg);
1435 if (!LocalLI->isLocal(RegionBeginIdx, RegionEndIdx))
1438 LiveInterval *GlobalLI = &LIS->getInterval(GlobalReg);
1440 // Find the global segment after the start of the local LI.
1441 LiveInterval::iterator GlobalSegment = GlobalLI->find(LocalLI->beginIndex());
1442 // If GlobalLI does not overlap LocalLI->start, then a copy directly feeds a
1443 // local live range. We could create edges from other global uses to the local
1444 // start, but the coalescer should have already eliminated these cases, so
1445 // don't bother dealing with it.
1446 if (GlobalSegment == GlobalLI->end())
1449 // If GlobalSegment is killed at the LocalLI->start, the call to find()
1450 // returned the next global segment. But if GlobalSegment overlaps with
1451 // LocalLI->start, then advance to the next segement. If a hole in GlobalLI
1452 // exists in LocalLI's vicinity, GlobalSegment will be the end of the hole.
1453 if (GlobalSegment->contains(LocalLI->beginIndex()))
1456 if (GlobalSegment == GlobalLI->end())
1459 // Check if GlobalLI contains a hole in the vicinity of LocalLI.
1460 if (GlobalSegment != GlobalLI->begin()) {
1461 // Two address defs have no hole.
1462 if (SlotIndex::isSameInstr(std::prev(GlobalSegment)->end,
1463 GlobalSegment->start)) {
1466 // If the prior global segment may be defined by the same two-address
1467 // instruction that also defines LocalLI, then can't make a hole here.
1468 if (SlotIndex::isSameInstr(std::prev(GlobalSegment)->start,
1469 LocalLI->beginIndex())) {
1472 // If GlobalLI has a prior segment, it must be live into the EBB. Otherwise
1473 // it would be a disconnected component in the live range.
1474 assert(std::prev(GlobalSegment)->start < LocalLI->beginIndex() &&
1475 "Disconnected LRG within the scheduling region.");
1477 MachineInstr *GlobalDef = LIS->getInstructionFromIndex(GlobalSegment->start);
1481 SUnit *GlobalSU = DAG->getSUnit(GlobalDef);
1485 // GlobalDef is the bottom of the GlobalLI hole. Open the hole by
1486 // constraining the uses of the last local def to precede GlobalDef.
1487 SmallVector<SUnit*,8> LocalUses;
1488 const VNInfo *LastLocalVN = LocalLI->getVNInfoBefore(LocalLI->endIndex());
1489 MachineInstr *LastLocalDef = LIS->getInstructionFromIndex(LastLocalVN->def);
1490 SUnit *LastLocalSU = DAG->getSUnit(LastLocalDef);
1491 for (SUnit::const_succ_iterator
1492 I = LastLocalSU->Succs.begin(), E = LastLocalSU->Succs.end();
1494 if (I->getKind() != SDep::Data || I->getReg() != LocalReg)
1496 if (I->getSUnit() == GlobalSU)
1498 if (!DAG->canAddEdge(GlobalSU, I->getSUnit()))
1500 LocalUses.push_back(I->getSUnit());
1502 // Open the top of the GlobalLI hole by constraining any earlier global uses
1503 // to precede the start of LocalLI.
1504 SmallVector<SUnit*,8> GlobalUses;
1505 MachineInstr *FirstLocalDef =
1506 LIS->getInstructionFromIndex(LocalLI->beginIndex());
1507 SUnit *FirstLocalSU = DAG->getSUnit(FirstLocalDef);
1508 for (SUnit::const_pred_iterator
1509 I = GlobalSU->Preds.begin(), E = GlobalSU->Preds.end(); I != E; ++I) {
1510 if (I->getKind() != SDep::Anti || I->getReg() != GlobalReg)
1512 if (I->getSUnit() == FirstLocalSU)
1514 if (!DAG->canAddEdge(FirstLocalSU, I->getSUnit()))
1516 GlobalUses.push_back(I->getSUnit());
1518 DEBUG(dbgs() << "Constraining copy SU(" << CopySU->NodeNum << ")\n");
1519 // Add the weak edges.
1520 for (SmallVectorImpl<SUnit*>::const_iterator
1521 I = LocalUses.begin(), E = LocalUses.end(); I != E; ++I) {
1522 DEBUG(dbgs() << " Local use SU(" << (*I)->NodeNum << ") -> SU("
1523 << GlobalSU->NodeNum << ")\n");
1524 DAG->addEdge(GlobalSU, SDep(*I, SDep::Weak));
1526 for (SmallVectorImpl<SUnit*>::const_iterator
1527 I = GlobalUses.begin(), E = GlobalUses.end(); I != E; ++I) {
1528 DEBUG(dbgs() << " Global use SU(" << (*I)->NodeNum << ") -> SU("
1529 << FirstLocalSU->NodeNum << ")\n");
1530 DAG->addEdge(FirstLocalSU, SDep(*I, SDep::Weak));
1534 /// \brief Callback from DAG postProcessing to create weak edges to encourage
1535 /// copy elimination.
1536 void CopyConstrain::apply(ScheduleDAGMI *DAG) {
1537 assert(DAG->hasVRegLiveness() && "Expect VRegs with LiveIntervals");
1539 MachineBasicBlock::iterator FirstPos = nextIfDebug(DAG->begin(), DAG->end());
1540 if (FirstPos == DAG->end())
1542 RegionBeginIdx = DAG->getLIS()->getInstructionIndex(&*FirstPos);
1543 RegionEndIdx = DAG->getLIS()->getInstructionIndex(
1544 &*priorNonDebug(DAG->end(), DAG->begin()));
1546 for (unsigned Idx = 0, End = DAG->SUnits.size(); Idx != End; ++Idx) {
1547 SUnit *SU = &DAG->SUnits[Idx];
1548 if (!SU->getInstr()->isCopy())
1551 constrainLocalCopy(SU, static_cast<ScheduleDAGMILive*>(DAG));
1555 //===----------------------------------------------------------------------===//
1556 // MachineSchedStrategy helpers used by GenericScheduler, GenericPostScheduler
1557 // and possibly other custom schedulers.
1558 //===----------------------------------------------------------------------===//
1560 static const unsigned InvalidCycle = ~0U;
1562 SchedBoundary::~SchedBoundary() { delete HazardRec; }
1564 void SchedBoundary::reset() {
1565 // A new HazardRec is created for each DAG and owned by SchedBoundary.
1566 // Destroying and reconstructing it is very expensive though. So keep
1567 // invalid, placeholder HazardRecs.
1568 if (HazardRec && HazardRec->isEnabled()) {
1570 HazardRec = nullptr;
1574 CheckPending = false;
1578 MinReadyCycle = UINT_MAX;
1579 ExpectedLatency = 0;
1580 DependentLatency = 0;
1582 MaxExecutedResCount = 0;
1584 IsResourceLimited = false;
1585 ReservedCycles.clear();
1587 // Track the maximum number of stall cycles that could arise either from the
1588 // latency of a DAG edge or the number of cycles that a processor resource is
1589 // reserved (SchedBoundary::ReservedCycles).
1590 MaxObservedStall = 0;
1592 // Reserve a zero-count for invalid CritResIdx.
1593 ExecutedResCounts.resize(1);
1594 assert(!ExecutedResCounts[0] && "nonzero count for bad resource");
1597 void SchedRemainder::
1598 init(ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel) {
1600 if (!SchedModel->hasInstrSchedModel())
1602 RemainingCounts.resize(SchedModel->getNumProcResourceKinds());
1603 for (std::vector<SUnit>::iterator
1604 I = DAG->SUnits.begin(), E = DAG->SUnits.end(); I != E; ++I) {
1605 const MCSchedClassDesc *SC = DAG->getSchedClass(&*I);
1606 RemIssueCount += SchedModel->getNumMicroOps(I->getInstr(), SC)
1607 * SchedModel->getMicroOpFactor();
1608 for (TargetSchedModel::ProcResIter
1609 PI = SchedModel->getWriteProcResBegin(SC),
1610 PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) {
1611 unsigned PIdx = PI->ProcResourceIdx;
1612 unsigned Factor = SchedModel->getResourceFactor(PIdx);
1613 RemainingCounts[PIdx] += (Factor * PI->Cycles);
1618 void SchedBoundary::
1619 init(ScheduleDAGMI *dag, const TargetSchedModel *smodel, SchedRemainder *rem) {
1622 SchedModel = smodel;
1624 if (SchedModel->hasInstrSchedModel()) {
1625 ExecutedResCounts.resize(SchedModel->getNumProcResourceKinds());
1626 ReservedCycles.resize(SchedModel->getNumProcResourceKinds(), InvalidCycle);
1630 /// Compute the stall cycles based on this SUnit's ready time. Heuristics treat
1631 /// these "soft stalls" differently than the hard stall cycles based on CPU
1632 /// resources and computed by checkHazard(). A fully in-order model
1633 /// (MicroOpBufferSize==0) will not make use of this since instructions are not
1634 /// available for scheduling until they are ready. However, a weaker in-order
1635 /// model may use this for heuristics. For example, if a processor has in-order
1636 /// behavior when reading certain resources, this may come into play.
1637 unsigned SchedBoundary::getLatencyStallCycles(SUnit *SU) {
1638 if (!SU->isUnbuffered)
1641 unsigned ReadyCycle = (isTop() ? SU->TopReadyCycle : SU->BotReadyCycle);
1642 if (ReadyCycle > CurrCycle)
1643 return ReadyCycle - CurrCycle;
1647 /// Compute the next cycle at which the given processor resource can be
1649 unsigned SchedBoundary::
1650 getNextResourceCycle(unsigned PIdx, unsigned Cycles) {
1651 unsigned NextUnreserved = ReservedCycles[PIdx];
1652 // If this resource has never been used, always return cycle zero.
1653 if (NextUnreserved == InvalidCycle)
1655 // For bottom-up scheduling add the cycles needed for the current operation.
1657 NextUnreserved += Cycles;
1658 return NextUnreserved;
1661 /// Does this SU have a hazard within the current instruction group.
1663 /// The scheduler supports two modes of hazard recognition. The first is the
1664 /// ScheduleHazardRecognizer API. It is a fully general hazard recognizer that
1665 /// supports highly complicated in-order reservation tables
1666 /// (ScoreboardHazardRecognizer) and arbitraty target-specific logic.
1668 /// The second is a streamlined mechanism that checks for hazards based on
1669 /// simple counters that the scheduler itself maintains. It explicitly checks
1670 /// for instruction dispatch limitations, including the number of micro-ops that
1671 /// can dispatch per cycle.
1673 /// TODO: Also check whether the SU must start a new group.
1674 bool SchedBoundary::checkHazard(SUnit *SU) {
1675 if (HazardRec->isEnabled()
1676 && HazardRec->getHazardType(SU) != ScheduleHazardRecognizer::NoHazard) {
1679 unsigned uops = SchedModel->getNumMicroOps(SU->getInstr());
1680 if ((CurrMOps > 0) && (CurrMOps + uops > SchedModel->getIssueWidth())) {
1681 DEBUG(dbgs() << " SU(" << SU->NodeNum << ") uops="
1682 << SchedModel->getNumMicroOps(SU->getInstr()) << '\n');
1685 if (SchedModel->hasInstrSchedModel() && SU->hasReservedResource) {
1686 const MCSchedClassDesc *SC = DAG->getSchedClass(SU);
1687 for (TargetSchedModel::ProcResIter
1688 PI = SchedModel->getWriteProcResBegin(SC),
1689 PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) {
1690 if (getNextResourceCycle(PI->ProcResourceIdx, PI->Cycles) > CurrCycle)
1697 // Find the unscheduled node in ReadySUs with the highest latency.
1698 unsigned SchedBoundary::
1699 findMaxLatency(ArrayRef<SUnit*> ReadySUs) {
1700 SUnit *LateSU = nullptr;
1701 unsigned RemLatency = 0;
1702 for (ArrayRef<SUnit*>::iterator I = ReadySUs.begin(), E = ReadySUs.end();
1704 unsigned L = getUnscheduledLatency(*I);
1705 if (L > RemLatency) {
1711 DEBUG(dbgs() << Available.getName() << " RemLatency SU("
1712 << LateSU->NodeNum << ") " << RemLatency << "c\n");
1717 // Count resources in this zone and the remaining unscheduled
1718 // instruction. Return the max count, scaled. Set OtherCritIdx to the critical
1719 // resource index, or zero if the zone is issue limited.
1720 unsigned SchedBoundary::
1721 getOtherResourceCount(unsigned &OtherCritIdx) {
1723 if (!SchedModel->hasInstrSchedModel())
1726 unsigned OtherCritCount = Rem->RemIssueCount
1727 + (RetiredMOps * SchedModel->getMicroOpFactor());
1728 DEBUG(dbgs() << " " << Available.getName() << " + Remain MOps: "
1729 << OtherCritCount / SchedModel->getMicroOpFactor() << '\n');
1730 for (unsigned PIdx = 1, PEnd = SchedModel->getNumProcResourceKinds();
1731 PIdx != PEnd; ++PIdx) {
1732 unsigned OtherCount = getResourceCount(PIdx) + Rem->RemainingCounts[PIdx];
1733 if (OtherCount > OtherCritCount) {
1734 OtherCritCount = OtherCount;
1735 OtherCritIdx = PIdx;
1739 DEBUG(dbgs() << " " << Available.getName() << " + Remain CritRes: "
1740 << OtherCritCount / SchedModel->getResourceFactor(OtherCritIdx)
1741 << " " << SchedModel->getResourceName(OtherCritIdx) << "\n");
1743 return OtherCritCount;
1746 void SchedBoundary::releaseNode(SUnit *SU, unsigned ReadyCycle) {
1747 assert(SU->getInstr() && "Scheduled SUnit must have instr");
1750 MaxObservedStall = std::max(ReadyCycle - CurrCycle, MaxObservedStall);
1753 if (ReadyCycle < MinReadyCycle)
1754 MinReadyCycle = ReadyCycle;
1756 // Check for interlocks first. For the purpose of other heuristics, an
1757 // instruction that cannot issue appears as if it's not in the ReadyQueue.
1758 bool IsBuffered = SchedModel->getMicroOpBufferSize() != 0;
1759 if ((!IsBuffered && ReadyCycle > CurrCycle) || checkHazard(SU))
1764 // Record this node as an immediate dependent of the scheduled node.
1768 void SchedBoundary::releaseTopNode(SUnit *SU) {
1769 if (SU->isScheduled)
1772 releaseNode(SU, SU->TopReadyCycle);
1775 void SchedBoundary::releaseBottomNode(SUnit *SU) {
1776 if (SU->isScheduled)
1779 releaseNode(SU, SU->BotReadyCycle);
1782 /// Move the boundary of scheduled code by one cycle.
1783 void SchedBoundary::bumpCycle(unsigned NextCycle) {
1784 if (SchedModel->getMicroOpBufferSize() == 0) {
1785 assert(MinReadyCycle < UINT_MAX && "MinReadyCycle uninitialized");
1786 if (MinReadyCycle > NextCycle)
1787 NextCycle = MinReadyCycle;
1789 // Update the current micro-ops, which will issue in the next cycle.
1790 unsigned DecMOps = SchedModel->getIssueWidth() * (NextCycle - CurrCycle);
1791 CurrMOps = (CurrMOps <= DecMOps) ? 0 : CurrMOps - DecMOps;
1793 // Decrement DependentLatency based on the next cycle.
1794 if ((NextCycle - CurrCycle) > DependentLatency)
1795 DependentLatency = 0;
1797 DependentLatency -= (NextCycle - CurrCycle);
1799 if (!HazardRec->isEnabled()) {
1800 // Bypass HazardRec virtual calls.
1801 CurrCycle = NextCycle;
1804 // Bypass getHazardType calls in case of long latency.
1805 for (; CurrCycle != NextCycle; ++CurrCycle) {
1807 HazardRec->AdvanceCycle();
1809 HazardRec->RecedeCycle();
1812 CheckPending = true;
1813 unsigned LFactor = SchedModel->getLatencyFactor();
1815 (int)(getCriticalCount() - (getScheduledLatency() * LFactor))
1818 DEBUG(dbgs() << "Cycle: " << CurrCycle << ' ' << Available.getName() << '\n');
1821 void SchedBoundary::incExecutedResources(unsigned PIdx, unsigned Count) {
1822 ExecutedResCounts[PIdx] += Count;
1823 if (ExecutedResCounts[PIdx] > MaxExecutedResCount)
1824 MaxExecutedResCount = ExecutedResCounts[PIdx];
1827 /// Add the given processor resource to this scheduled zone.
1829 /// \param Cycles indicates the number of consecutive (non-pipelined) cycles
1830 /// during which this resource is consumed.
1832 /// \return the next cycle at which the instruction may execute without
1833 /// oversubscribing resources.
1834 unsigned SchedBoundary::
1835 countResource(unsigned PIdx, unsigned Cycles, unsigned NextCycle) {
1836 unsigned Factor = SchedModel->getResourceFactor(PIdx);
1837 unsigned Count = Factor * Cycles;
1838 DEBUG(dbgs() << " " << SchedModel->getResourceName(PIdx)
1839 << " +" << Cycles << "x" << Factor << "u\n");
1841 // Update Executed resources counts.
1842 incExecutedResources(PIdx, Count);
1843 assert(Rem->RemainingCounts[PIdx] >= Count && "resource double counted");
1844 Rem->RemainingCounts[PIdx] -= Count;
1846 // Check if this resource exceeds the current critical resource. If so, it
1847 // becomes the critical resource.
1848 if (ZoneCritResIdx != PIdx && (getResourceCount(PIdx) > getCriticalCount())) {
1849 ZoneCritResIdx = PIdx;
1850 DEBUG(dbgs() << " *** Critical resource "
1851 << SchedModel->getResourceName(PIdx) << ": "
1852 << getResourceCount(PIdx) / SchedModel->getLatencyFactor() << "c\n");
1854 // For reserved resources, record the highest cycle using the resource.
1855 unsigned NextAvailable = getNextResourceCycle(PIdx, Cycles);
1856 if (NextAvailable > CurrCycle) {
1857 DEBUG(dbgs() << " Resource conflict: "
1858 << SchedModel->getProcResource(PIdx)->Name << " reserved until @"
1859 << NextAvailable << "\n");
1861 return NextAvailable;
1864 /// Move the boundary of scheduled code by one SUnit.
1865 void SchedBoundary::bumpNode(SUnit *SU) {
1866 // Update the reservation table.
1867 if (HazardRec->isEnabled()) {
1868 if (!isTop() && SU->isCall) {
1869 // Calls are scheduled with their preceding instructions. For bottom-up
1870 // scheduling, clear the pipeline state before emitting.
1873 HazardRec->EmitInstruction(SU);
1875 // checkHazard should prevent scheduling multiple instructions per cycle that
1876 // exceed the issue width.
1877 const MCSchedClassDesc *SC = DAG->getSchedClass(SU);
1878 unsigned IncMOps = SchedModel->getNumMicroOps(SU->getInstr());
1880 (CurrMOps == 0 || (CurrMOps + IncMOps) <= SchedModel->getIssueWidth()) &&
1881 "Cannot schedule this instruction's MicroOps in the current cycle.");
1883 unsigned ReadyCycle = (isTop() ? SU->TopReadyCycle : SU->BotReadyCycle);
1884 DEBUG(dbgs() << " Ready @" << ReadyCycle << "c\n");
1886 unsigned NextCycle = CurrCycle;
1887 switch (SchedModel->getMicroOpBufferSize()) {
1889 assert(ReadyCycle <= CurrCycle && "Broken PendingQueue");
1892 if (ReadyCycle > NextCycle) {
1893 NextCycle = ReadyCycle;
1894 DEBUG(dbgs() << " *** Stall until: " << ReadyCycle << "\n");
1898 // We don't currently model the OOO reorder buffer, so consider all
1899 // scheduled MOps to be "retired". We do loosely model in-order resource
1900 // latency. If this instruction uses an in-order resource, account for any
1901 // likely stall cycles.
1902 if (SU->isUnbuffered && ReadyCycle > NextCycle)
1903 NextCycle = ReadyCycle;
1906 RetiredMOps += IncMOps;
1908 // Update resource counts and critical resource.
1909 if (SchedModel->hasInstrSchedModel()) {
1910 unsigned DecRemIssue = IncMOps * SchedModel->getMicroOpFactor();
1911 assert(Rem->RemIssueCount >= DecRemIssue && "MOps double counted");
1912 Rem->RemIssueCount -= DecRemIssue;
1913 if (ZoneCritResIdx) {
1914 // Scale scheduled micro-ops for comparing with the critical resource.
1915 unsigned ScaledMOps =
1916 RetiredMOps * SchedModel->getMicroOpFactor();
1918 // If scaled micro-ops are now more than the previous critical resource by
1919 // a full cycle, then micro-ops issue becomes critical.
1920 if ((int)(ScaledMOps - getResourceCount(ZoneCritResIdx))
1921 >= (int)SchedModel->getLatencyFactor()) {
1923 DEBUG(dbgs() << " *** Critical resource NumMicroOps: "
1924 << ScaledMOps / SchedModel->getLatencyFactor() << "c\n");
1927 for (TargetSchedModel::ProcResIter
1928 PI = SchedModel->getWriteProcResBegin(SC),
1929 PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) {
1931 countResource(PI->ProcResourceIdx, PI->Cycles, NextCycle);
1932 if (RCycle > NextCycle)
1935 if (SU->hasReservedResource) {
1936 // For reserved resources, record the highest cycle using the resource.
1937 // For top-down scheduling, this is the cycle in which we schedule this
1938 // instruction plus the number of cycles the operations reserves the
1939 // resource. For bottom-up is it simply the instruction's cycle.
1940 for (TargetSchedModel::ProcResIter
1941 PI = SchedModel->getWriteProcResBegin(SC),
1942 PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) {
1943 unsigned PIdx = PI->ProcResourceIdx;
1944 if (SchedModel->getProcResource(PIdx)->BufferSize == 0) {
1945 ReservedCycles[PIdx] = isTop() ? NextCycle + PI->Cycles : NextCycle;
1947 MaxObservedStall = std::max(PI->Cycles, MaxObservedStall);
1953 // Update ExpectedLatency and DependentLatency.
1954 unsigned &TopLatency = isTop() ? ExpectedLatency : DependentLatency;
1955 unsigned &BotLatency = isTop() ? DependentLatency : ExpectedLatency;
1956 if (SU->getDepth() > TopLatency) {
1957 TopLatency = SU->getDepth();
1958 DEBUG(dbgs() << " " << Available.getName()
1959 << " TopLatency SU(" << SU->NodeNum << ") " << TopLatency << "c\n");
1961 if (SU->getHeight() > BotLatency) {
1962 BotLatency = SU->getHeight();
1963 DEBUG(dbgs() << " " << Available.getName()
1964 << " BotLatency SU(" << SU->NodeNum << ") " << BotLatency << "c\n");
1966 // If we stall for any reason, bump the cycle.
1967 if (NextCycle > CurrCycle) {
1968 bumpCycle(NextCycle);
1971 // After updating ZoneCritResIdx and ExpectedLatency, check if we're
1972 // resource limited. If a stall occurred, bumpCycle does this.
1973 unsigned LFactor = SchedModel->getLatencyFactor();
1975 (int)(getCriticalCount() - (getScheduledLatency() * LFactor))
1978 // Update CurrMOps after calling bumpCycle to handle stalls, since bumpCycle
1979 // resets CurrMOps. Loop to handle instructions with more MOps than issue in
1980 // one cycle. Since we commonly reach the max MOps here, opportunistically
1981 // bump the cycle to avoid uselessly checking everything in the readyQ.
1982 CurrMOps += IncMOps;
1983 while (CurrMOps >= SchedModel->getIssueWidth()) {
1984 DEBUG(dbgs() << " *** Max MOps " << CurrMOps
1985 << " at cycle " << CurrCycle << '\n');
1986 bumpCycle(++NextCycle);
1988 DEBUG(dumpScheduledState());
1991 /// Release pending ready nodes in to the available queue. This makes them
1992 /// visible to heuristics.
1993 void SchedBoundary::releasePending() {
1994 // If the available queue is empty, it is safe to reset MinReadyCycle.
1995 if (Available.empty())
1996 MinReadyCycle = UINT_MAX;
1998 // Check to see if any of the pending instructions are ready to issue. If
1999 // so, add them to the available queue.
2000 bool IsBuffered = SchedModel->getMicroOpBufferSize() != 0;
2001 for (unsigned i = 0, e = Pending.size(); i != e; ++i) {
2002 SUnit *SU = *(Pending.begin()+i);
2003 unsigned ReadyCycle = isTop() ? SU->TopReadyCycle : SU->BotReadyCycle;
2005 if (ReadyCycle < MinReadyCycle)
2006 MinReadyCycle = ReadyCycle;
2008 if (!IsBuffered && ReadyCycle > CurrCycle)
2011 if (checkHazard(SU))
2015 Pending.remove(Pending.begin()+i);
2018 DEBUG(if (!Pending.empty()) Pending.dump());
2019 CheckPending = false;
2022 /// Remove SU from the ready set for this boundary.
2023 void SchedBoundary::removeReady(SUnit *SU) {
2024 if (Available.isInQueue(SU))
2025 Available.remove(Available.find(SU));
2027 assert(Pending.isInQueue(SU) && "bad ready count");
2028 Pending.remove(Pending.find(SU));
2032 /// If this queue only has one ready candidate, return it. As a side effect,
2033 /// defer any nodes that now hit a hazard, and advance the cycle until at least
2034 /// one node is ready. If multiple instructions are ready, return NULL.
2035 SUnit *SchedBoundary::pickOnlyChoice() {
2040 // Defer any ready instrs that now have a hazard.
2041 for (ReadyQueue::iterator I = Available.begin(); I != Available.end();) {
2042 if (checkHazard(*I)) {
2044 I = Available.remove(I);
2050 for (unsigned i = 0; Available.empty(); ++i) {
2051 assert(i <= (HazardRec->getMaxLookAhead() + MaxObservedStall) &&
2052 "permanent hazard"); (void)i;
2053 bumpCycle(CurrCycle + 1);
2056 if (Available.size() == 1)
2057 return *Available.begin();
2062 // This is useful information to dump after bumpNode.
2063 // Note that the Queue contents are more useful before pickNodeFromQueue.
2064 void SchedBoundary::dumpScheduledState() {
2067 if (ZoneCritResIdx) {
2068 ResFactor = SchedModel->getResourceFactor(ZoneCritResIdx);
2069 ResCount = getResourceCount(ZoneCritResIdx);
2072 ResFactor = SchedModel->getMicroOpFactor();
2073 ResCount = RetiredMOps * SchedModel->getMicroOpFactor();
2075 unsigned LFactor = SchedModel->getLatencyFactor();
2076 dbgs() << Available.getName() << " @" << CurrCycle << "c\n"
2077 << " Retired: " << RetiredMOps;
2078 dbgs() << "\n Executed: " << getExecutedCount() / LFactor << "c";
2079 dbgs() << "\n Critical: " << ResCount / LFactor << "c, "
2080 << ResCount / ResFactor << " "
2081 << SchedModel->getResourceName(ZoneCritResIdx)
2082 << "\n ExpectedLatency: " << ExpectedLatency << "c\n"
2083 << (IsResourceLimited ? " - Resource" : " - Latency")
2088 //===----------------------------------------------------------------------===//
2089 // GenericScheduler - Generic implementation of MachineSchedStrategy.
2090 //===----------------------------------------------------------------------===//
2092 void GenericSchedulerBase::SchedCandidate::
2093 initResourceDelta(const ScheduleDAGMI *DAG,
2094 const TargetSchedModel *SchedModel) {
2095 if (!Policy.ReduceResIdx && !Policy.DemandResIdx)
2098 const MCSchedClassDesc *SC = DAG->getSchedClass(SU);
2099 for (TargetSchedModel::ProcResIter
2100 PI = SchedModel->getWriteProcResBegin(SC),
2101 PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) {
2102 if (PI->ProcResourceIdx == Policy.ReduceResIdx)
2103 ResDelta.CritResources += PI->Cycles;
2104 if (PI->ProcResourceIdx == Policy.DemandResIdx)
2105 ResDelta.DemandedResources += PI->Cycles;
2109 /// Set the CandPolicy given a scheduling zone given the current resources and
2110 /// latencies inside and outside the zone.
2111 void GenericSchedulerBase::setPolicy(CandPolicy &Policy,
2113 SchedBoundary &CurrZone,
2114 SchedBoundary *OtherZone) {
2115 // Apply preemptive heuristics based on the the total latency and resources
2116 // inside and outside this zone. Potential stalls should be considered before
2117 // following this policy.
2119 // Compute remaining latency. We need this both to determine whether the
2120 // overall schedule has become latency-limited and whether the instructions
2121 // outside this zone are resource or latency limited.
2123 // The "dependent" latency is updated incrementally during scheduling as the
2124 // max height/depth of scheduled nodes minus the cycles since it was
2126 // DLat = max (N.depth - (CurrCycle - N.ReadyCycle) for N in Zone
2128 // The "independent" latency is the max ready queue depth:
2129 // ILat = max N.depth for N in Available|Pending
2131 // RemainingLatency is the greater of independent and dependent latency.
2132 unsigned RemLatency = CurrZone.getDependentLatency();
2133 RemLatency = std::max(RemLatency,
2134 CurrZone.findMaxLatency(CurrZone.Available.elements()));
2135 RemLatency = std::max(RemLatency,
2136 CurrZone.findMaxLatency(CurrZone.Pending.elements()));
2138 // Compute the critical resource outside the zone.
2139 unsigned OtherCritIdx = 0;
2140 unsigned OtherCount =
2141 OtherZone ? OtherZone->getOtherResourceCount(OtherCritIdx) : 0;
2143 bool OtherResLimited = false;
2144 if (SchedModel->hasInstrSchedModel()) {
2145 unsigned LFactor = SchedModel->getLatencyFactor();
2146 OtherResLimited = (int)(OtherCount - (RemLatency * LFactor)) > (int)LFactor;
2148 // Schedule aggressively for latency in PostRA mode. We don't check for
2149 // acyclic latency during PostRA, and highly out-of-order processors will
2150 // skip PostRA scheduling.
2151 if (!OtherResLimited) {
2152 if (IsPostRA || (RemLatency + CurrZone.getCurrCycle() > Rem.CriticalPath)) {
2153 Policy.ReduceLatency |= true;
2154 DEBUG(dbgs() << " " << CurrZone.Available.getName()
2155 << " RemainingLatency " << RemLatency << " + "
2156 << CurrZone.getCurrCycle() << "c > CritPath "
2157 << Rem.CriticalPath << "\n");
2160 // If the same resource is limiting inside and outside the zone, do nothing.
2161 if (CurrZone.getZoneCritResIdx() == OtherCritIdx)
2165 if (CurrZone.isResourceLimited()) {
2166 dbgs() << " " << CurrZone.Available.getName() << " ResourceLimited: "
2167 << SchedModel->getResourceName(CurrZone.getZoneCritResIdx())
2170 if (OtherResLimited)
2171 dbgs() << " RemainingLimit: "
2172 << SchedModel->getResourceName(OtherCritIdx) << "\n";
2173 if (!CurrZone.isResourceLimited() && !OtherResLimited)
2174 dbgs() << " Latency limited both directions.\n");
2176 if (CurrZone.isResourceLimited() && !Policy.ReduceResIdx)
2177 Policy.ReduceResIdx = CurrZone.getZoneCritResIdx();
2179 if (OtherResLimited)
2180 Policy.DemandResIdx = OtherCritIdx;
2184 const char *GenericSchedulerBase::getReasonStr(
2185 GenericSchedulerBase::CandReason Reason) {
2187 case NoCand: return "NOCAND ";
2188 case PhysRegCopy: return "PREG-COPY";
2189 case RegExcess: return "REG-EXCESS";
2190 case RegCritical: return "REG-CRIT ";
2191 case Stall: return "STALL ";
2192 case Cluster: return "CLUSTER ";
2193 case Weak: return "WEAK ";
2194 case RegMax: return "REG-MAX ";
2195 case ResourceReduce: return "RES-REDUCE";
2196 case ResourceDemand: return "RES-DEMAND";
2197 case TopDepthReduce: return "TOP-DEPTH ";
2198 case TopPathReduce: return "TOP-PATH ";
2199 case BotHeightReduce:return "BOT-HEIGHT";
2200 case BotPathReduce: return "BOT-PATH ";
2201 case NextDefUse: return "DEF-USE ";
2202 case NodeOrder: return "ORDER ";
2204 llvm_unreachable("Unknown reason!");
2207 void GenericSchedulerBase::traceCandidate(const SchedCandidate &Cand) {
2209 unsigned ResIdx = 0;
2210 unsigned Latency = 0;
2211 switch (Cand.Reason) {
2215 P = Cand.RPDelta.Excess;
2218 P = Cand.RPDelta.CriticalMax;
2221 P = Cand.RPDelta.CurrentMax;
2223 case ResourceReduce:
2224 ResIdx = Cand.Policy.ReduceResIdx;
2226 case ResourceDemand:
2227 ResIdx = Cand.Policy.DemandResIdx;
2229 case TopDepthReduce:
2230 Latency = Cand.SU->getDepth();
2233 Latency = Cand.SU->getHeight();
2235 case BotHeightReduce:
2236 Latency = Cand.SU->getHeight();
2239 Latency = Cand.SU->getDepth();
2242 dbgs() << " SU(" << Cand.SU->NodeNum << ") " << getReasonStr(Cand.Reason);
2244 dbgs() << " " << TRI->getRegPressureSetName(P.getPSet())
2245 << ":" << P.getUnitInc() << " ";
2249 dbgs() << " " << SchedModel->getProcResource(ResIdx)->Name << " ";
2253 dbgs() << " " << Latency << " cycles ";
2260 /// Return true if this heuristic determines order.
2261 static bool tryLess(int TryVal, int CandVal,
2262 GenericSchedulerBase::SchedCandidate &TryCand,
2263 GenericSchedulerBase::SchedCandidate &Cand,
2264 GenericSchedulerBase::CandReason Reason) {
2265 if (TryVal < CandVal) {
2266 TryCand.Reason = Reason;
2269 if (TryVal > CandVal) {
2270 if (Cand.Reason > Reason)
2271 Cand.Reason = Reason;
2274 Cand.setRepeat(Reason);
2278 static bool tryGreater(int TryVal, int CandVal,
2279 GenericSchedulerBase::SchedCandidate &TryCand,
2280 GenericSchedulerBase::SchedCandidate &Cand,
2281 GenericSchedulerBase::CandReason Reason) {
2282 if (TryVal > CandVal) {
2283 TryCand.Reason = Reason;
2286 if (TryVal < CandVal) {
2287 if (Cand.Reason > Reason)
2288 Cand.Reason = Reason;
2291 Cand.setRepeat(Reason);
2295 static bool tryLatency(GenericSchedulerBase::SchedCandidate &TryCand,
2296 GenericSchedulerBase::SchedCandidate &Cand,
2297 SchedBoundary &Zone) {
2299 if (Cand.SU->getDepth() > Zone.getScheduledLatency()) {
2300 if (tryLess(TryCand.SU->getDepth(), Cand.SU->getDepth(),
2301 TryCand, Cand, GenericSchedulerBase::TopDepthReduce))
2304 if (tryGreater(TryCand.SU->getHeight(), Cand.SU->getHeight(),
2305 TryCand, Cand, GenericSchedulerBase::TopPathReduce))
2309 if (Cand.SU->getHeight() > Zone.getScheduledLatency()) {
2310 if (tryLess(TryCand.SU->getHeight(), Cand.SU->getHeight(),
2311 TryCand, Cand, GenericSchedulerBase::BotHeightReduce))
2314 if (tryGreater(TryCand.SU->getDepth(), Cand.SU->getDepth(),
2315 TryCand, Cand, GenericSchedulerBase::BotPathReduce))
2321 static void tracePick(const GenericSchedulerBase::SchedCandidate &Cand,
2323 DEBUG(dbgs() << "Pick " << (IsTop ? "Top " : "Bot ")
2324 << GenericSchedulerBase::getReasonStr(Cand.Reason) << '\n');
2327 void GenericScheduler::initialize(ScheduleDAGMI *dag) {
2328 assert(dag->hasVRegLiveness() &&
2329 "(PreRA)GenericScheduler needs vreg liveness");
2330 DAG = static_cast<ScheduleDAGMILive*>(dag);
2331 SchedModel = DAG->getSchedModel();
2334 Rem.init(DAG, SchedModel);
2335 Top.init(DAG, SchedModel, &Rem);
2336 Bot.init(DAG, SchedModel, &Rem);
2338 // Initialize resource counts.
2340 // Initialize the HazardRecognizers. If itineraries don't exist, are empty, or
2341 // are disabled, then these HazardRecs will be disabled.
2342 const InstrItineraryData *Itin = SchedModel->getInstrItineraries();
2343 const TargetMachine &TM = DAG->MF.getTarget();
2344 if (!Top.HazardRec) {
2346 TM.getInstrInfo()->CreateTargetMIHazardRecognizer(Itin, DAG);
2348 if (!Bot.HazardRec) {
2350 TM.getInstrInfo()->CreateTargetMIHazardRecognizer(Itin, DAG);
2354 /// Initialize the per-region scheduling policy.
2355 void GenericScheduler::initPolicy(MachineBasicBlock::iterator Begin,
2356 MachineBasicBlock::iterator End,
2357 unsigned NumRegionInstrs) {
2358 const TargetMachine &TM = Context->MF->getTarget();
2359 const TargetLowering *TLI = TM.getTargetLowering();
2361 // Avoid setting up the register pressure tracker for small regions to save
2362 // compile time. As a rough heuristic, only track pressure when the number of
2363 // schedulable instructions exceeds half the integer register file.
2364 RegionPolicy.ShouldTrackPressure = true;
2365 for (unsigned VT = MVT::i32; VT > (unsigned)MVT::i1; --VT) {
2366 MVT::SimpleValueType LegalIntVT = (MVT::SimpleValueType)VT;
2367 if (TLI->isTypeLegal(LegalIntVT)) {
2368 unsigned NIntRegs = Context->RegClassInfo->getNumAllocatableRegs(
2369 TLI->getRegClassFor(LegalIntVT));
2370 RegionPolicy.ShouldTrackPressure = NumRegionInstrs > (NIntRegs / 2);
2374 // For generic targets, we default to bottom-up, because it's simpler and more
2375 // compile-time optimizations have been implemented in that direction.
2376 RegionPolicy.OnlyBottomUp = true;
2378 // Allow the subtarget to override default policy.
2379 const TargetSubtargetInfo &ST = TM.getSubtarget<TargetSubtargetInfo>();
2380 ST.overrideSchedPolicy(RegionPolicy, Begin, End, NumRegionInstrs);
2382 // After subtarget overrides, apply command line options.
2383 if (!EnableRegPressure)
2384 RegionPolicy.ShouldTrackPressure = false;
2386 // Check -misched-topdown/bottomup can force or unforce scheduling direction.
2387 // e.g. -misched-bottomup=false allows scheduling in both directions.
2388 assert((!ForceTopDown || !ForceBottomUp) &&
2389 "-misched-topdown incompatible with -misched-bottomup");
2390 if (ForceBottomUp.getNumOccurrences() > 0) {
2391 RegionPolicy.OnlyBottomUp = ForceBottomUp;
2392 if (RegionPolicy.OnlyBottomUp)
2393 RegionPolicy.OnlyTopDown = false;
2395 if (ForceTopDown.getNumOccurrences() > 0) {
2396 RegionPolicy.OnlyTopDown = ForceTopDown;
2397 if (RegionPolicy.OnlyTopDown)
2398 RegionPolicy.OnlyBottomUp = false;
2402 /// Set IsAcyclicLatencyLimited if the acyclic path is longer than the cyclic
2403 /// critical path by more cycles than it takes to drain the instruction buffer.
2404 /// We estimate an upper bounds on in-flight instructions as:
2406 /// CyclesPerIteration = max( CyclicPath, Loop-Resource-Height )
2407 /// InFlightIterations = AcyclicPath / CyclesPerIteration
2408 /// InFlightResources = InFlightIterations * LoopResources
2410 /// TODO: Check execution resources in addition to IssueCount.
2411 void GenericScheduler::checkAcyclicLatency() {
2412 if (Rem.CyclicCritPath == 0 || Rem.CyclicCritPath >= Rem.CriticalPath)
2415 // Scaled number of cycles per loop iteration.
2416 unsigned IterCount =
2417 std::max(Rem.CyclicCritPath * SchedModel->getLatencyFactor(),
2419 // Scaled acyclic critical path.
2420 unsigned AcyclicCount = Rem.CriticalPath * SchedModel->getLatencyFactor();
2421 // InFlightCount = (AcyclicPath / IterCycles) * InstrPerLoop
2422 unsigned InFlightCount =
2423 (AcyclicCount * Rem.RemIssueCount + IterCount-1) / IterCount;
2424 unsigned BufferLimit =
2425 SchedModel->getMicroOpBufferSize() * SchedModel->getMicroOpFactor();
2427 Rem.IsAcyclicLatencyLimited = InFlightCount > BufferLimit;
2429 DEBUG(dbgs() << "IssueCycles="
2430 << Rem.RemIssueCount / SchedModel->getLatencyFactor() << "c "
2431 << "IterCycles=" << IterCount / SchedModel->getLatencyFactor()
2432 << "c NumIters=" << (AcyclicCount + IterCount-1) / IterCount
2433 << " InFlight=" << InFlightCount / SchedModel->getMicroOpFactor()
2434 << "m BufferLim=" << SchedModel->getMicroOpBufferSize() << "m\n";
2435 if (Rem.IsAcyclicLatencyLimited)
2436 dbgs() << " ACYCLIC LATENCY LIMIT\n");
2439 void GenericScheduler::registerRoots() {
2440 Rem.CriticalPath = DAG->ExitSU.getDepth();
2442 // Some roots may not feed into ExitSU. Check all of them in case.
2443 for (std::vector<SUnit*>::const_iterator
2444 I = Bot.Available.begin(), E = Bot.Available.end(); I != E; ++I) {
2445 if ((*I)->getDepth() > Rem.CriticalPath)
2446 Rem.CriticalPath = (*I)->getDepth();
2448 DEBUG(dbgs() << "Critical Path: " << Rem.CriticalPath << '\n');
2450 if (EnableCyclicPath) {
2451 Rem.CyclicCritPath = DAG->computeCyclicCriticalPath();
2452 checkAcyclicLatency();
2456 static bool tryPressure(const PressureChange &TryP,
2457 const PressureChange &CandP,
2458 GenericSchedulerBase::SchedCandidate &TryCand,
2459 GenericSchedulerBase::SchedCandidate &Cand,
2460 GenericSchedulerBase::CandReason Reason) {
2461 int TryRank = TryP.getPSetOrMax();
2462 int CandRank = CandP.getPSetOrMax();
2463 // If both candidates affect the same set, go with the smallest increase.
2464 if (TryRank == CandRank) {
2465 return tryLess(TryP.getUnitInc(), CandP.getUnitInc(), TryCand, Cand,
2468 // If one candidate decreases and the other increases, go with it.
2469 // Invalid candidates have UnitInc==0.
2470 if (tryLess(TryP.getUnitInc() < 0, CandP.getUnitInc() < 0, TryCand, Cand,
2474 // If the candidates are decreasing pressure, reverse priority.
2475 if (TryP.getUnitInc() < 0)
2476 std::swap(TryRank, CandRank);
2477 return tryGreater(TryRank, CandRank, TryCand, Cand, Reason);
2480 static unsigned getWeakLeft(const SUnit *SU, bool isTop) {
2481 return (isTop) ? SU->WeakPredsLeft : SU->WeakSuccsLeft;
2484 /// Minimize physical register live ranges. Regalloc wants them adjacent to
2485 /// their physreg def/use.
2487 /// FIXME: This is an unnecessary check on the critical path. Most are root/leaf
2488 /// copies which can be prescheduled. The rest (e.g. x86 MUL) could be bundled
2489 /// with the operation that produces or consumes the physreg. We'll do this when
2490 /// regalloc has support for parallel copies.
2491 static int biasPhysRegCopy(const SUnit *SU, bool isTop) {
2492 const MachineInstr *MI = SU->getInstr();
2496 unsigned ScheduledOper = isTop ? 1 : 0;
2497 unsigned UnscheduledOper = isTop ? 0 : 1;
2498 // If we have already scheduled the physreg produce/consumer, immediately
2499 // schedule the copy.
2500 if (TargetRegisterInfo::isPhysicalRegister(
2501 MI->getOperand(ScheduledOper).getReg()))
2503 // If the physreg is at the boundary, defer it. Otherwise schedule it
2504 // immediately to free the dependent. We can hoist the copy later.
2505 bool AtBoundary = isTop ? !SU->NumSuccsLeft : !SU->NumPredsLeft;
2506 if (TargetRegisterInfo::isPhysicalRegister(
2507 MI->getOperand(UnscheduledOper).getReg()))
2508 return AtBoundary ? -1 : 1;
2512 /// Apply a set of heursitics to a new candidate. Heuristics are currently
2513 /// hierarchical. This may be more efficient than a graduated cost model because
2514 /// we don't need to evaluate all aspects of the model for each node in the
2515 /// queue. But it's really done to make the heuristics easier to debug and
2516 /// statistically analyze.
2518 /// \param Cand provides the policy and current best candidate.
2519 /// \param TryCand refers to the next SUnit candidate, otherwise uninitialized.
2520 /// \param Zone describes the scheduled zone that we are extending.
2521 /// \param RPTracker describes reg pressure within the scheduled zone.
2522 /// \param TempTracker is a scratch pressure tracker to reuse in queries.
2523 void GenericScheduler::tryCandidate(SchedCandidate &Cand,
2524 SchedCandidate &TryCand,
2525 SchedBoundary &Zone,
2526 const RegPressureTracker &RPTracker,
2527 RegPressureTracker &TempTracker) {
2529 if (DAG->isTrackingPressure()) {
2530 // Always initialize TryCand's RPDelta.
2532 TempTracker.getMaxDownwardPressureDelta(
2533 TryCand.SU->getInstr(),
2535 DAG->getRegionCriticalPSets(),
2536 DAG->getRegPressure().MaxSetPressure);
2539 if (VerifyScheduling) {
2540 TempTracker.getMaxUpwardPressureDelta(
2541 TryCand.SU->getInstr(),
2542 &DAG->getPressureDiff(TryCand.SU),
2544 DAG->getRegionCriticalPSets(),
2545 DAG->getRegPressure().MaxSetPressure);
2548 RPTracker.getUpwardPressureDelta(
2549 TryCand.SU->getInstr(),
2550 DAG->getPressureDiff(TryCand.SU),
2552 DAG->getRegionCriticalPSets(),
2553 DAG->getRegPressure().MaxSetPressure);
2557 DEBUG(if (TryCand.RPDelta.Excess.isValid())
2558 dbgs() << " SU(" << TryCand.SU->NodeNum << ") "
2559 << TRI->getRegPressureSetName(TryCand.RPDelta.Excess.getPSet())
2560 << ":" << TryCand.RPDelta.Excess.getUnitInc() << "\n");
2562 // Initialize the candidate if needed.
2563 if (!Cand.isValid()) {
2564 TryCand.Reason = NodeOrder;
2568 if (tryGreater(biasPhysRegCopy(TryCand.SU, Zone.isTop()),
2569 biasPhysRegCopy(Cand.SU, Zone.isTop()),
2570 TryCand, Cand, PhysRegCopy))
2573 // Avoid exceeding the target's limit. If signed PSetID is negative, it is
2574 // invalid; convert it to INT_MAX to give it lowest priority.
2575 if (DAG->isTrackingPressure() && tryPressure(TryCand.RPDelta.Excess,
2576 Cand.RPDelta.Excess,
2577 TryCand, Cand, RegExcess))
2580 // Avoid increasing the max critical pressure in the scheduled region.
2581 if (DAG->isTrackingPressure() && tryPressure(TryCand.RPDelta.CriticalMax,
2582 Cand.RPDelta.CriticalMax,
2583 TryCand, Cand, RegCritical))
2586 // For loops that are acyclic path limited, aggressively schedule for latency.
2587 // This can result in very long dependence chains scheduled in sequence, so
2588 // once every cycle (when CurrMOps == 0), switch to normal heuristics.
2589 if (Rem.IsAcyclicLatencyLimited && !Zone.getCurrMOps()
2590 && tryLatency(TryCand, Cand, Zone))
2593 // Prioritize instructions that read unbuffered resources by stall cycles.
2594 if (tryLess(Zone.getLatencyStallCycles(TryCand.SU),
2595 Zone.getLatencyStallCycles(Cand.SU), TryCand, Cand, Stall))
2598 // Keep clustered nodes together to encourage downstream peephole
2599 // optimizations which may reduce resource requirements.
2601 // This is a best effort to set things up for a post-RA pass. Optimizations
2602 // like generating loads of multiple registers should ideally be done within
2603 // the scheduler pass by combining the loads during DAG postprocessing.
2604 const SUnit *NextClusterSU =
2605 Zone.isTop() ? DAG->getNextClusterSucc() : DAG->getNextClusterPred();
2606 if (tryGreater(TryCand.SU == NextClusterSU, Cand.SU == NextClusterSU,
2607 TryCand, Cand, Cluster))
2610 // Weak edges are for clustering and other constraints.
2611 if (tryLess(getWeakLeft(TryCand.SU, Zone.isTop()),
2612 getWeakLeft(Cand.SU, Zone.isTop()),
2613 TryCand, Cand, Weak)) {
2616 // Avoid increasing the max pressure of the entire region.
2617 if (DAG->isTrackingPressure() && tryPressure(TryCand.RPDelta.CurrentMax,
2618 Cand.RPDelta.CurrentMax,
2619 TryCand, Cand, RegMax))
2622 // Avoid critical resource consumption and balance the schedule.
2623 TryCand.initResourceDelta(DAG, SchedModel);
2624 if (tryLess(TryCand.ResDelta.CritResources, Cand.ResDelta.CritResources,
2625 TryCand, Cand, ResourceReduce))
2627 if (tryGreater(TryCand.ResDelta.DemandedResources,
2628 Cand.ResDelta.DemandedResources,
2629 TryCand, Cand, ResourceDemand))
2632 // Avoid serializing long latency dependence chains.
2633 // For acyclic path limited loops, latency was already checked above.
2634 if (Cand.Policy.ReduceLatency && !Rem.IsAcyclicLatencyLimited
2635 && tryLatency(TryCand, Cand, Zone)) {
2639 // Prefer immediate defs/users of the last scheduled instruction. This is a
2640 // local pressure avoidance strategy that also makes the machine code
2642 if (tryGreater(Zone.isNextSU(TryCand.SU), Zone.isNextSU(Cand.SU),
2643 TryCand, Cand, NextDefUse))
2646 // Fall through to original instruction order.
2647 if ((Zone.isTop() && TryCand.SU->NodeNum < Cand.SU->NodeNum)
2648 || (!Zone.isTop() && TryCand.SU->NodeNum > Cand.SU->NodeNum)) {
2649 TryCand.Reason = NodeOrder;
2653 /// Pick the best candidate from the queue.
2655 /// TODO: getMaxPressureDelta results can be mostly cached for each SUnit during
2656 /// DAG building. To adjust for the current scheduling location we need to
2657 /// maintain the number of vreg uses remaining to be top-scheduled.
2658 void GenericScheduler::pickNodeFromQueue(SchedBoundary &Zone,
2659 const RegPressureTracker &RPTracker,
2660 SchedCandidate &Cand) {
2661 ReadyQueue &Q = Zone.Available;
2665 // getMaxPressureDelta temporarily modifies the tracker.
2666 RegPressureTracker &TempTracker = const_cast<RegPressureTracker&>(RPTracker);
2668 for (ReadyQueue::iterator I = Q.begin(), E = Q.end(); I != E; ++I) {
2670 SchedCandidate TryCand(Cand.Policy);
2672 tryCandidate(Cand, TryCand, Zone, RPTracker, TempTracker);
2673 if (TryCand.Reason != NoCand) {
2674 // Initialize resource delta if needed in case future heuristics query it.
2675 if (TryCand.ResDelta == SchedResourceDelta())
2676 TryCand.initResourceDelta(DAG, SchedModel);
2677 Cand.setBest(TryCand);
2678 DEBUG(traceCandidate(Cand));
2683 /// Pick the best candidate node from either the top or bottom queue.
2684 SUnit *GenericScheduler::pickNodeBidirectional(bool &IsTopNode) {
2685 // Schedule as far as possible in the direction of no choice. This is most
2686 // efficient, but also provides the best heuristics for CriticalPSets.
2687 if (SUnit *SU = Bot.pickOnlyChoice()) {
2689 DEBUG(dbgs() << "Pick Bot NOCAND\n");
2692 if (SUnit *SU = Top.pickOnlyChoice()) {
2694 DEBUG(dbgs() << "Pick Top NOCAND\n");
2697 CandPolicy NoPolicy;
2698 SchedCandidate BotCand(NoPolicy);
2699 SchedCandidate TopCand(NoPolicy);
2700 // Set the bottom-up policy based on the state of the current bottom zone and
2701 // the instructions outside the zone, including the top zone.
2702 setPolicy(BotCand.Policy, /*IsPostRA=*/false, Bot, &Top);
2703 // Set the top-down policy based on the state of the current top zone and
2704 // the instructions outside the zone, including the bottom zone.
2705 setPolicy(TopCand.Policy, /*IsPostRA=*/false, Top, &Bot);
2707 // Prefer bottom scheduling when heuristics are silent.
2708 pickNodeFromQueue(Bot, DAG->getBotRPTracker(), BotCand);
2709 assert(BotCand.Reason != NoCand && "failed to find the first candidate");
2711 // If either Q has a single candidate that provides the least increase in
2712 // Excess pressure, we can immediately schedule from that Q.
2714 // RegionCriticalPSets summarizes the pressure within the scheduled region and
2715 // affects picking from either Q. If scheduling in one direction must
2716 // increase pressure for one of the excess PSets, then schedule in that
2717 // direction first to provide more freedom in the other direction.
2718 if ((BotCand.Reason == RegExcess && !BotCand.isRepeat(RegExcess))
2719 || (BotCand.Reason == RegCritical
2720 && !BotCand.isRepeat(RegCritical)))
2723 tracePick(BotCand, IsTopNode);
2726 // Check if the top Q has a better candidate.
2727 pickNodeFromQueue(Top, DAG->getTopRPTracker(), TopCand);
2728 assert(TopCand.Reason != NoCand && "failed to find the first candidate");
2730 // Choose the queue with the most important (lowest enum) reason.
2731 if (TopCand.Reason < BotCand.Reason) {
2733 tracePick(TopCand, IsTopNode);
2736 // Otherwise prefer the bottom candidate, in node order if all else failed.
2738 tracePick(BotCand, IsTopNode);
2742 /// Pick the best node to balance the schedule. Implements MachineSchedStrategy.
2743 SUnit *GenericScheduler::pickNode(bool &IsTopNode) {
2744 if (DAG->top() == DAG->bottom()) {
2745 assert(Top.Available.empty() && Top.Pending.empty() &&
2746 Bot.Available.empty() && Bot.Pending.empty() && "ReadyQ garbage");
2751 if (RegionPolicy.OnlyTopDown) {
2752 SU = Top.pickOnlyChoice();
2754 CandPolicy NoPolicy;
2755 SchedCandidate TopCand(NoPolicy);
2756 pickNodeFromQueue(Top, DAG->getTopRPTracker(), TopCand);
2757 assert(TopCand.Reason != NoCand && "failed to find a candidate");
2758 tracePick(TopCand, true);
2763 else if (RegionPolicy.OnlyBottomUp) {
2764 SU = Bot.pickOnlyChoice();
2766 CandPolicy NoPolicy;
2767 SchedCandidate BotCand(NoPolicy);
2768 pickNodeFromQueue(Bot, DAG->getBotRPTracker(), BotCand);
2769 assert(BotCand.Reason != NoCand && "failed to find a candidate");
2770 tracePick(BotCand, false);
2776 SU = pickNodeBidirectional(IsTopNode);
2778 } while (SU->isScheduled);
2780 if (SU->isTopReady())
2781 Top.removeReady(SU);
2782 if (SU->isBottomReady())
2783 Bot.removeReady(SU);
2785 DEBUG(dbgs() << "Scheduling SU(" << SU->NodeNum << ") " << *SU->getInstr());
2789 void GenericScheduler::reschedulePhysRegCopies(SUnit *SU, bool isTop) {
2791 MachineBasicBlock::iterator InsertPos = SU->getInstr();
2794 SmallVectorImpl<SDep> &Deps = isTop ? SU->Preds : SU->Succs;
2796 // Find already scheduled copies with a single physreg dependence and move
2797 // them just above the scheduled instruction.
2798 for (SmallVectorImpl<SDep>::iterator I = Deps.begin(), E = Deps.end();
2800 if (I->getKind() != SDep::Data || !TRI->isPhysicalRegister(I->getReg()))
2802 SUnit *DepSU = I->getSUnit();
2803 if (isTop ? DepSU->Succs.size() > 1 : DepSU->Preds.size() > 1)
2805 MachineInstr *Copy = DepSU->getInstr();
2806 if (!Copy->isCopy())
2808 DEBUG(dbgs() << " Rescheduling physreg copy ";
2809 I->getSUnit()->dump(DAG));
2810 DAG->moveInstruction(Copy, InsertPos);
2814 /// Update the scheduler's state after scheduling a node. This is the same node
2815 /// that was just returned by pickNode(). However, ScheduleDAGMILive needs to
2816 /// update it's state based on the current cycle before MachineSchedStrategy
2819 /// FIXME: Eventually, we may bundle physreg copies rather than rescheduling
2820 /// them here. See comments in biasPhysRegCopy.
2821 void GenericScheduler::schedNode(SUnit *SU, bool IsTopNode) {
2823 SU->TopReadyCycle = std::max(SU->TopReadyCycle, Top.getCurrCycle());
2825 if (SU->hasPhysRegUses)
2826 reschedulePhysRegCopies(SU, true);
2829 SU->BotReadyCycle = std::max(SU->BotReadyCycle, Bot.getCurrCycle());
2831 if (SU->hasPhysRegDefs)
2832 reschedulePhysRegCopies(SU, false);
2836 /// Create the standard converging machine scheduler. This will be used as the
2837 /// default scheduler if the target does not set a default.
2838 static ScheduleDAGInstrs *createGenericSchedLive(MachineSchedContext *C) {
2839 ScheduleDAGMILive *DAG = new ScheduleDAGMILive(C, make_unique<GenericScheduler>(C));
2840 // Register DAG post-processors.
2842 // FIXME: extend the mutation API to allow earlier mutations to instantiate
2843 // data and pass it to later mutations. Have a single mutation that gathers
2844 // the interesting nodes in one pass.
2845 DAG->addMutation(make_unique<CopyConstrain>(DAG->TII, DAG->TRI));
2846 if (EnableLoadCluster && DAG->TII->enableClusterLoads())
2847 DAG->addMutation(make_unique<LoadClusterMutation>(DAG->TII, DAG->TRI));
2848 if (EnableMacroFusion)
2849 DAG->addMutation(make_unique<MacroFusion>(DAG->TII));
2853 static MachineSchedRegistry
2854 GenericSchedRegistry("converge", "Standard converging scheduler.",
2855 createGenericSchedLive);
2857 //===----------------------------------------------------------------------===//
2858 // PostGenericScheduler - Generic PostRA implementation of MachineSchedStrategy.
2859 //===----------------------------------------------------------------------===//
2861 void PostGenericScheduler::initialize(ScheduleDAGMI *Dag) {
2863 SchedModel = DAG->getSchedModel();
2866 Rem.init(DAG, SchedModel);
2867 Top.init(DAG, SchedModel, &Rem);
2870 // Initialize the HazardRecognizers. If itineraries don't exist, are empty,
2871 // or are disabled, then these HazardRecs will be disabled.
2872 const InstrItineraryData *Itin = SchedModel->getInstrItineraries();
2873 const TargetMachine &TM = DAG->MF.getTarget();
2874 if (!Top.HazardRec) {
2876 TM.getInstrInfo()->CreateTargetMIHazardRecognizer(Itin, DAG);
2881 void PostGenericScheduler::registerRoots() {
2882 Rem.CriticalPath = DAG->ExitSU.getDepth();
2884 // Some roots may not feed into ExitSU. Check all of them in case.
2885 for (SmallVectorImpl<SUnit*>::const_iterator
2886 I = BotRoots.begin(), E = BotRoots.end(); I != E; ++I) {
2887 if ((*I)->getDepth() > Rem.CriticalPath)
2888 Rem.CriticalPath = (*I)->getDepth();
2890 DEBUG(dbgs() << "Critical Path: " << Rem.CriticalPath << '\n');
2893 /// Apply a set of heursitics to a new candidate for PostRA scheduling.
2895 /// \param Cand provides the policy and current best candidate.
2896 /// \param TryCand refers to the next SUnit candidate, otherwise uninitialized.
2897 void PostGenericScheduler::tryCandidate(SchedCandidate &Cand,
2898 SchedCandidate &TryCand) {
2900 // Initialize the candidate if needed.
2901 if (!Cand.isValid()) {
2902 TryCand.Reason = NodeOrder;
2906 // Prioritize instructions that read unbuffered resources by stall cycles.
2907 if (tryLess(Top.getLatencyStallCycles(TryCand.SU),
2908 Top.getLatencyStallCycles(Cand.SU), TryCand, Cand, Stall))
2911 // Avoid critical resource consumption and balance the schedule.
2912 if (tryLess(TryCand.ResDelta.CritResources, Cand.ResDelta.CritResources,
2913 TryCand, Cand, ResourceReduce))
2915 if (tryGreater(TryCand.ResDelta.DemandedResources,
2916 Cand.ResDelta.DemandedResources,
2917 TryCand, Cand, ResourceDemand))
2920 // Avoid serializing long latency dependence chains.
2921 if (Cand.Policy.ReduceLatency && tryLatency(TryCand, Cand, Top)) {
2925 // Fall through to original instruction order.
2926 if (TryCand.SU->NodeNum < Cand.SU->NodeNum)
2927 TryCand.Reason = NodeOrder;
2930 void PostGenericScheduler::pickNodeFromQueue(SchedCandidate &Cand) {
2931 ReadyQueue &Q = Top.Available;
2935 for (ReadyQueue::iterator I = Q.begin(), E = Q.end(); I != E; ++I) {
2936 SchedCandidate TryCand(Cand.Policy);
2938 TryCand.initResourceDelta(DAG, SchedModel);
2939 tryCandidate(Cand, TryCand);
2940 if (TryCand.Reason != NoCand) {
2941 Cand.setBest(TryCand);
2942 DEBUG(traceCandidate(Cand));
2947 /// Pick the next node to schedule.
2948 SUnit *PostGenericScheduler::pickNode(bool &IsTopNode) {
2949 if (DAG->top() == DAG->bottom()) {
2950 assert(Top.Available.empty() && Top.Pending.empty() && "ReadyQ garbage");
2955 SU = Top.pickOnlyChoice();
2957 CandPolicy NoPolicy;
2958 SchedCandidate TopCand(NoPolicy);
2959 // Set the top-down policy based on the state of the current top zone and
2960 // the instructions outside the zone, including the bottom zone.
2961 setPolicy(TopCand.Policy, /*IsPostRA=*/true, Top, nullptr);
2962 pickNodeFromQueue(TopCand);
2963 assert(TopCand.Reason != NoCand && "failed to find a candidate");
2964 tracePick(TopCand, true);
2967 } while (SU->isScheduled);
2970 Top.removeReady(SU);
2972 DEBUG(dbgs() << "Scheduling SU(" << SU->NodeNum << ") " << *SU->getInstr());
2976 /// Called after ScheduleDAGMI has scheduled an instruction and updated
2977 /// scheduled/remaining flags in the DAG nodes.
2978 void PostGenericScheduler::schedNode(SUnit *SU, bool IsTopNode) {
2979 SU->TopReadyCycle = std::max(SU->TopReadyCycle, Top.getCurrCycle());
2983 /// Create a generic scheduler with no vreg liveness or DAG mutation passes.
2984 static ScheduleDAGInstrs *createGenericSchedPostRA(MachineSchedContext *C) {
2985 return new ScheduleDAGMI(C, make_unique<PostGenericScheduler>(C), /*IsPostRA=*/true);
2988 //===----------------------------------------------------------------------===//
2989 // ILP Scheduler. Currently for experimental analysis of heuristics.
2990 //===----------------------------------------------------------------------===//
2993 /// \brief Order nodes by the ILP metric.
2995 const SchedDFSResult *DFSResult;
2996 const BitVector *ScheduledTrees;
2999 ILPOrder(bool MaxILP)
3000 : DFSResult(nullptr), ScheduledTrees(nullptr), MaximizeILP(MaxILP) {}
3002 /// \brief Apply a less-than relation on node priority.
3004 /// (Return true if A comes after B in the Q.)
3005 bool operator()(const SUnit *A, const SUnit *B) const {
3006 unsigned SchedTreeA = DFSResult->getSubtreeID(A);
3007 unsigned SchedTreeB = DFSResult->getSubtreeID(B);
3008 if (SchedTreeA != SchedTreeB) {
3009 // Unscheduled trees have lower priority.
3010 if (ScheduledTrees->test(SchedTreeA) != ScheduledTrees->test(SchedTreeB))
3011 return ScheduledTrees->test(SchedTreeB);
3013 // Trees with shallower connections have have lower priority.
3014 if (DFSResult->getSubtreeLevel(SchedTreeA)
3015 != DFSResult->getSubtreeLevel(SchedTreeB)) {
3016 return DFSResult->getSubtreeLevel(SchedTreeA)
3017 < DFSResult->getSubtreeLevel(SchedTreeB);
3021 return DFSResult->getILP(A) < DFSResult->getILP(B);
3023 return DFSResult->getILP(A) > DFSResult->getILP(B);
3027 /// \brief Schedule based on the ILP metric.
3028 class ILPScheduler : public MachineSchedStrategy {
3029 ScheduleDAGMILive *DAG;
3032 std::vector<SUnit*> ReadyQ;
3034 ILPScheduler(bool MaximizeILP): DAG(nullptr), Cmp(MaximizeILP) {}
3036 void initialize(ScheduleDAGMI *dag) override {
3037 assert(dag->hasVRegLiveness() && "ILPScheduler needs vreg liveness");
3038 DAG = static_cast<ScheduleDAGMILive*>(dag);
3039 DAG->computeDFSResult();
3040 Cmp.DFSResult = DAG->getDFSResult();
3041 Cmp.ScheduledTrees = &DAG->getScheduledTrees();
3045 void registerRoots() override {
3046 // Restore the heap in ReadyQ with the updated DFS results.
3047 std::make_heap(ReadyQ.begin(), ReadyQ.end(), Cmp);
3050 /// Implement MachineSchedStrategy interface.
3051 /// -----------------------------------------
3053 /// Callback to select the highest priority node from the ready Q.
3054 SUnit *pickNode(bool &IsTopNode) override {
3055 if (ReadyQ.empty()) return nullptr;
3056 std::pop_heap(ReadyQ.begin(), ReadyQ.end(), Cmp);
3057 SUnit *SU = ReadyQ.back();
3060 DEBUG(dbgs() << "Pick node " << "SU(" << SU->NodeNum << ") "
3061 << " ILP: " << DAG->getDFSResult()->getILP(SU)
3062 << " Tree: " << DAG->getDFSResult()->getSubtreeID(SU) << " @"
3063 << DAG->getDFSResult()->getSubtreeLevel(
3064 DAG->getDFSResult()->getSubtreeID(SU)) << '\n'
3065 << "Scheduling " << *SU->getInstr());
3069 /// \brief Scheduler callback to notify that a new subtree is scheduled.
3070 void scheduleTree(unsigned SubtreeID) override {
3071 std::make_heap(ReadyQ.begin(), ReadyQ.end(), Cmp);
3074 /// Callback after a node is scheduled. Mark a newly scheduled tree, notify
3075 /// DFSResults, and resort the priority Q.
3076 void schedNode(SUnit *SU, bool IsTopNode) override {
3077 assert(!IsTopNode && "SchedDFSResult needs bottom-up");
3080 void releaseTopNode(SUnit *) override { /*only called for top roots*/ }
3082 void releaseBottomNode(SUnit *SU) override {
3083 ReadyQ.push_back(SU);
3084 std::push_heap(ReadyQ.begin(), ReadyQ.end(), Cmp);
3089 static ScheduleDAGInstrs *createILPMaxScheduler(MachineSchedContext *C) {
3090 return new ScheduleDAGMILive(C, make_unique<ILPScheduler>(true));
3092 static ScheduleDAGInstrs *createILPMinScheduler(MachineSchedContext *C) {
3093 return new ScheduleDAGMILive(C, make_unique<ILPScheduler>(false));
3095 static MachineSchedRegistry ILPMaxRegistry(
3096 "ilpmax", "Schedule bottom-up for max ILP", createILPMaxScheduler);
3097 static MachineSchedRegistry ILPMinRegistry(
3098 "ilpmin", "Schedule bottom-up for min ILP", createILPMinScheduler);
3100 //===----------------------------------------------------------------------===//
3101 // Machine Instruction Shuffler for Correctness Testing
3102 //===----------------------------------------------------------------------===//
3106 /// Apply a less-than relation on the node order, which corresponds to the
3107 /// instruction order prior to scheduling. IsReverse implements greater-than.
3108 template<bool IsReverse>
3110 bool operator()(SUnit *A, SUnit *B) const {
3112 return A->NodeNum > B->NodeNum;
3114 return A->NodeNum < B->NodeNum;
3118 /// Reorder instructions as much as possible.
3119 class InstructionShuffler : public MachineSchedStrategy {
3123 // Using a less-than relation (SUnitOrder<false>) for the TopQ priority
3124 // gives nodes with a higher number higher priority causing the latest
3125 // instructions to be scheduled first.
3126 PriorityQueue<SUnit*, std::vector<SUnit*>, SUnitOrder<false> >
3128 // When scheduling bottom-up, use greater-than as the queue priority.
3129 PriorityQueue<SUnit*, std::vector<SUnit*>, SUnitOrder<true> >
3132 InstructionShuffler(bool alternate, bool topdown)
3133 : IsAlternating(alternate), IsTopDown(topdown) {}
3135 void initialize(ScheduleDAGMI*) override {
3140 /// Implement MachineSchedStrategy interface.
3141 /// -----------------------------------------
3143 SUnit *pickNode(bool &IsTopNode) override {
3147 if (TopQ.empty()) return nullptr;
3150 } while (SU->isScheduled);
3155 if (BottomQ.empty()) return nullptr;
3158 } while (SU->isScheduled);
3162 IsTopDown = !IsTopDown;
3166 void schedNode(SUnit *SU, bool IsTopNode) override {}
3168 void releaseTopNode(SUnit *SU) override {
3171 void releaseBottomNode(SUnit *SU) override {
3177 static ScheduleDAGInstrs *createInstructionShuffler(MachineSchedContext *C) {
3178 bool Alternate = !ForceTopDown && !ForceBottomUp;
3179 bool TopDown = !ForceBottomUp;
3180 assert((TopDown || !ForceTopDown) &&
3181 "-misched-topdown incompatible with -misched-bottomup");
3182 return new ScheduleDAGMILive(C, make_unique<InstructionShuffler>(Alternate, TopDown));
3184 static MachineSchedRegistry ShufflerRegistry(
3185 "shuffle", "Shuffle machine instructions alternating directions",
3186 createInstructionShuffler);
3189 //===----------------------------------------------------------------------===//
3190 // GraphWriter support for ScheduleDAGMILive.
3191 //===----------------------------------------------------------------------===//
3196 template<> struct GraphTraits<
3197 ScheduleDAGMI*> : public GraphTraits<ScheduleDAG*> {};
3200 struct DOTGraphTraits<ScheduleDAGMI*> : public DefaultDOTGraphTraits {
3202 DOTGraphTraits (bool isSimple=false) : DefaultDOTGraphTraits(isSimple) {}
3204 static std::string getGraphName(const ScheduleDAG *G) {
3205 return G->MF.getName();
3208 static bool renderGraphFromBottomUp() {
3212 static bool isNodeHidden(const SUnit *Node) {
3213 return (Node->Preds.size() > 10 || Node->Succs.size() > 10);
3216 static bool hasNodeAddressLabel(const SUnit *Node,
3217 const ScheduleDAG *Graph) {
3221 /// If you want to override the dot attributes printed for a particular
3222 /// edge, override this method.
3223 static std::string getEdgeAttributes(const SUnit *Node,
3225 const ScheduleDAG *Graph) {
3226 if (EI.isArtificialDep())
3227 return "color=cyan,style=dashed";
3229 return "color=blue,style=dashed";
3233 static std::string getNodeLabel(const SUnit *SU, const ScheduleDAG *G) {
3235 raw_string_ostream SS(Str);
3236 const ScheduleDAGMI *DAG = static_cast<const ScheduleDAGMI*>(G);
3237 const SchedDFSResult *DFS = DAG->hasVRegLiveness() ?
3238 static_cast<const ScheduleDAGMILive*>(G)->getDFSResult() : nullptr;
3239 SS << "SU:" << SU->NodeNum;
3241 SS << " I:" << DFS->getNumInstrs(SU);
3244 static std::string getNodeDescription(const SUnit *SU, const ScheduleDAG *G) {
3245 return G->getGraphNodeLabel(SU);
3248 static std::string getNodeAttributes(const SUnit *N, const ScheduleDAG *G) {
3249 std::string Str("shape=Mrecord");
3250 const ScheduleDAGMI *DAG = static_cast<const ScheduleDAGMI*>(G);
3251 const SchedDFSResult *DFS = DAG->hasVRegLiveness() ?
3252 static_cast<const ScheduleDAGMILive*>(G)->getDFSResult() : nullptr;
3254 Str += ",style=filled,fillcolor=\"#";
3255 Str += DOT::getColorString(DFS->getSubtreeID(N));
3264 /// viewGraph - Pop up a ghostview window with the reachable parts of the DAG
3265 /// rendered using 'dot'.
3267 void ScheduleDAGMI::viewGraph(const Twine &Name, const Twine &Title) {
3269 ViewGraph(this, Name, false, Title);
3271 errs() << "ScheduleDAGMI::viewGraph is only available in debug builds on "
3272 << "systems with Graphviz or gv!\n";
3276 /// Out-of-line implementation with no arguments is handy for gdb.
3277 void ScheduleDAGMI::viewGraph() {
3278 viewGraph(getDAGName(), "Scheduling-Units Graph for " + getDAGName());