1 //===- MachineScheduler.cpp - Machine Instruction Scheduler ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // MachineScheduler schedules machine instructions after phi elimination. It
11 // preserves LiveIntervals so it can be invoked before register allocation.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "misched"
17 #include "ScheduleDAGInstrs.h"
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "llvm/CodeGen/MachinePassRegistry.h"
20 #include "llvm/CodeGen/Passes.h"
21 #include "llvm/Analysis/AliasAnalysis.h"
22 #include "llvm/Target/TargetInstrInfo.h"
23 #include "llvm/Support/CommandLine.h"
24 #include "llvm/Support/Debug.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/raw_ostream.h"
27 #include "llvm/ADT/OwningPtr.h"
33 //===----------------------------------------------------------------------===//
34 // Machine Instruction Scheduling Pass and Registry
35 //===----------------------------------------------------------------------===//
38 /// MachineScheduler runs after coalescing and before register allocation.
39 class MachineScheduler : public MachineFunctionPass {
42 const TargetInstrInfo *TII;
43 const MachineLoopInfo *MLI;
44 const MachineDominatorTree *MDT;
49 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
51 virtual void releaseMemory() {}
53 virtual bool runOnMachineFunction(MachineFunction&);
55 virtual void print(raw_ostream &O, const Module* = 0) const;
57 static char ID; // Class identification, replacement for typeinfo
61 char MachineScheduler::ID = 0;
63 char &llvm::MachineSchedulerID = MachineScheduler::ID;
65 INITIALIZE_PASS_BEGIN(MachineScheduler, "misched",
66 "Machine Instruction Scheduler", false, false)
67 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
68 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
69 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
70 INITIALIZE_PASS_END(MachineScheduler, "misched",
71 "Machine Instruction Scheduler", false, false)
73 MachineScheduler::MachineScheduler()
74 : MachineFunctionPass(ID), MF(0), MLI(0), MDT(0) {
75 initializeMachineSchedulerPass(*PassRegistry::getPassRegistry());
78 void MachineScheduler::getAnalysisUsage(AnalysisUsage &AU) const {
80 AU.addRequiredID(MachineDominatorsID);
81 AU.addRequired<MachineLoopInfo>();
82 AU.addRequired<AliasAnalysis>();
83 AU.addPreserved<AliasAnalysis>();
84 AU.addRequired<SlotIndexes>();
85 AU.addPreserved<SlotIndexes>();
86 AU.addRequired<LiveIntervals>();
87 AU.addPreserved<LiveIntervals>();
88 MachineFunctionPass::getAnalysisUsage(AU);
92 /// MachineSchedRegistry provides a selection of available machine instruction
94 class MachineSchedRegistry : public MachinePassRegistryNode {
96 typedef ScheduleDAGInstrs *(*ScheduleDAGCtor)(MachineScheduler *);
98 // RegisterPassParser requires a (misnamed) FunctionPassCtor type.
99 typedef ScheduleDAGCtor FunctionPassCtor;
101 static MachinePassRegistry Registry;
103 MachineSchedRegistry(const char *N, const char *D, ScheduleDAGCtor C)
104 : MachinePassRegistryNode(N, D, (MachinePassCtor)C) {
107 ~MachineSchedRegistry() { Registry.Remove(this); }
111 MachineSchedRegistry *getNext() const {
112 return (MachineSchedRegistry *)MachinePassRegistryNode::getNext();
114 static MachineSchedRegistry *getList() {
115 return (MachineSchedRegistry *)Registry.getList();
117 static ScheduleDAGCtor getDefault() {
118 return (ScheduleDAGCtor)Registry.getDefault();
120 static void setDefault(ScheduleDAGCtor C) {
121 Registry.setDefault((MachinePassCtor)C);
123 static void setListener(MachinePassRegistryListener *L) {
124 Registry.setListener(L);
129 MachinePassRegistry MachineSchedRegistry::Registry;
131 static ScheduleDAGInstrs *createDefaultMachineSched(MachineScheduler *P);
133 /// MachineSchedOpt allows command line selection of the scheduler.
134 static cl::opt<MachineSchedRegistry::ScheduleDAGCtor, false,
135 RegisterPassParser<MachineSchedRegistry> >
136 MachineSchedOpt("misched",
137 cl::init(&createDefaultMachineSched), cl::Hidden,
138 cl::desc("Machine instruction scheduler to use"));
140 //===----------------------------------------------------------------------===//
141 // Machine Instruction Scheduling Common Implementation
142 //===----------------------------------------------------------------------===//
145 /// ScheduleTopDownLive is an implementation of ScheduleDAGInstrs that schedules
146 /// machine instructions while updating LiveIntervals.
147 class ScheduleTopDownLive : public ScheduleDAGInstrs {
149 MachineScheduler *Pass;
151 ScheduleTopDownLive(MachineScheduler *P):
152 ScheduleDAGInstrs(*P->MF, *P->MLI, *P->MDT, /*IsPostRA=*/false, P->LIS),
155 /// ScheduleDAGInstrs callback.
158 /// Interface implemented by the selected top-down liveinterval scheduler.
160 /// Pick the next node to schedule, or return NULL.
161 virtual SUnit *pickNode() = 0;
163 /// When all preceeding dependencies have been resolved, free this node for
165 virtual void releaseNode(SUnit *SU) = 0;
168 void releaseSucc(SUnit *SU, SDep *SuccEdge);
169 void releaseSuccessors(SUnit *SU);
173 /// ReleaseSucc - Decrement the NumPredsLeft count of a successor. When
174 /// NumPredsLeft reaches zero, release the successor node.
175 void ScheduleTopDownLive::releaseSucc(SUnit *SU, SDep *SuccEdge) {
176 SUnit *SuccSU = SuccEdge->getSUnit();
179 if (SuccSU->NumPredsLeft == 0) {
180 dbgs() << "*** Scheduling failed! ***\n";
182 dbgs() << " has been released too many times!\n";
186 --SuccSU->NumPredsLeft;
187 if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU)
191 /// releaseSuccessors - Call releaseSucc on each of SU's successors.
192 void ScheduleTopDownLive::releaseSuccessors(SUnit *SU) {
193 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
195 releaseSucc(SU, &*I);
199 /// Schedule - This is called back from ScheduleDAGInstrs::Run() when it's
200 /// time to do some work.
201 void ScheduleTopDownLive::Schedule() {
202 BuildSchedGraph(&Pass->getAnalysis<AliasAnalysis>());
204 DEBUG(dbgs() << "********** MI Scheduling **********\n");
205 DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
206 SUnits[su].dumpAll(this));
208 // Release any successors of the special Entry node. It is currently unused,
209 // but we keep up appearances.
210 releaseSuccessors(&EntrySU);
212 // Release all DAG roots for scheduling.
213 for (std::vector<SUnit>::iterator I = SUnits.begin(), E = SUnits.end();
215 // A SUnit is ready to schedule if it has no predecessors.
216 if (I->Preds.empty())
221 while (SUnit *SU = pickNode()) {
222 DEBUG(dbgs() << "*** Scheduling Instruction:\n"; SU->dump(this));
224 // Move the instruction to its new location in the instruction stream.
225 MachineInstr *MI = SU->getInstr();
226 if (&*InsertPos == MI)
229 BB->splice(InsertPos, BB, MI);
230 Pass->LIS->handleMove(MI);
231 if (Begin == InsertPos)
235 // Release dependent instructions for scheduling.
236 releaseSuccessors(SU);
240 bool MachineScheduler::runOnMachineFunction(MachineFunction &mf) {
241 // Initialize the context of the pass.
243 MLI = &getAnalysis<MachineLoopInfo>();
244 MDT = &getAnalysis<MachineDominatorTree>();
245 LIS = &getAnalysis<LiveIntervals>();
246 TII = MF->getTarget().getInstrInfo();
248 // Select the scheduler, or set the default.
249 MachineSchedRegistry::ScheduleDAGCtor Ctor =
250 MachineSchedRegistry::getDefault();
252 Ctor = MachineSchedOpt;
253 MachineSchedRegistry::setDefault(Ctor);
255 // Instantiate the selected scheduler.
256 OwningPtr<ScheduleDAGInstrs> Scheduler(Ctor(this));
258 // Visit all machine basic blocks.
259 for (MachineFunction::iterator MBB = MF->begin(), MBBEnd = MF->end();
260 MBB != MBBEnd; ++MBB) {
262 // Break the block into scheduling regions [I, RegionEnd), and schedule each
263 // region as soon as it is discovered.
264 unsigned RemainingCount = MBB->size();
265 for(MachineBasicBlock::iterator RegionEnd = MBB->end();
266 RegionEnd != MBB->begin();) {
267 // The next region starts above the previous region. Look backward in the
268 // instruction stream until we find the nearest boundary.
269 MachineBasicBlock::iterator I = RegionEnd;
270 for(;I != MBB->begin(); --I, --RemainingCount) {
271 if (TII->isSchedulingBoundary(llvm::prior(I), MBB, *MF))
274 if (I == RegionEnd) {
275 // Skip empty scheduling regions.
276 RegionEnd = llvm::prior(RegionEnd);
280 // Skip regions with one instruction.
281 if (I == llvm::prior(RegionEnd)) {
282 RegionEnd = llvm::prior(RegionEnd);
285 DEBUG(dbgs() << "MachineScheduling " << MF->getFunction()->getName()
286 << ":BB#" << MBB->getNumber() << "\n From: " << *I << " To: ";
287 if (RegionEnd != MBB->end()) dbgs() << *RegionEnd;
288 else dbgs() << "End";
289 dbgs() << " Remaining: " << RemainingCount << "\n");
291 // Inform ScheduleDAGInstrs of the region being scheduled. It calls back
292 // to our Schedule() method.
293 Scheduler->Run(MBB, I, RegionEnd, MBB->size());
294 RegionEnd = Scheduler->Begin;
296 assert(RemainingCount == 0 && "Instruction count mismatch!");
301 void MachineScheduler::print(raw_ostream &O, const Module* m) const {
305 //===----------------------------------------------------------------------===//
306 // Placeholder for extending the machine instruction scheduler.
307 //===----------------------------------------------------------------------===//
310 class DefaultMachineScheduler : public ScheduleDAGInstrs {
311 MachineScheduler *Pass;
313 DefaultMachineScheduler(MachineScheduler *P):
314 ScheduleDAGInstrs(*P->MF, *P->MLI, *P->MDT, /*IsPostRA=*/false, P->LIS),
317 /// Schedule - This is called back from ScheduleDAGInstrs::Run() when it's
318 /// time to do some work.
323 static ScheduleDAGInstrs *createDefaultMachineSched(MachineScheduler *P) {
324 return new DefaultMachineScheduler(P);
326 static MachineSchedRegistry
327 SchedDefaultRegistry("default", "Activate the scheduler pass, "
328 "but don't reorder instructions",
329 createDefaultMachineSched);
332 /// Schedule - This is called back from ScheduleDAGInstrs::Run() when it's
333 /// time to do some work.
334 void DefaultMachineScheduler::Schedule() {
335 BuildSchedGraph(&Pass->getAnalysis<AliasAnalysis>());
337 DEBUG(dbgs() << "********** MI Scheduling **********\n");
338 DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
339 SUnits[su].dumpAll(this));
341 // TODO: Put interesting things here.
343 // When this is fully implemented, it will become a subclass of
344 // ScheduleTopDownLive. So this driver will disappear.
347 //===----------------------------------------------------------------------===//
348 // Machine Instruction Shuffler for Correctness Testing
349 //===----------------------------------------------------------------------===//
353 // Nodes with a higher number have higher priority. This way we attempt to
354 // schedule the latest instructions earliest.
356 // TODO: Relies on the property of the BuildSchedGraph that results in SUnits
357 // being ordered in sequence top-down.
358 struct ShuffleSUnitOrder {
359 bool operator()(SUnit *A, SUnit *B) const {
360 return A->NodeNum < B->NodeNum;
364 /// Reorder instructions as much as possible.
365 class InstructionShuffler : public ScheduleTopDownLive {
366 std::priority_queue<SUnit*, std::vector<SUnit*>, ShuffleSUnitOrder> Queue;
368 InstructionShuffler(MachineScheduler *P):
369 ScheduleTopDownLive(P) {}
371 /// ScheduleTopDownLive Interface
373 virtual SUnit *pickNode() {
374 if (Queue.empty()) return NULL;
375 SUnit *SU = Queue.top();
380 virtual void releaseNode(SUnit *SU) {
386 static ScheduleDAGInstrs *createInstructionShuffler(MachineScheduler *P) {
387 return new InstructionShuffler(P);
389 static MachineSchedRegistry ShufflerRegistry("shuffle",
390 "Shuffle machine instructions",
391 createInstructionShuffler);