1 //===- MachineScheduler.cpp - Machine Instruction Scheduler ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // MachineScheduler schedules machine instructions after phi elimination. It
11 // preserves LiveIntervals so it can be invoked before register allocation.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "misched"
17 #include "llvm/CodeGen/MachineScheduler.h"
18 #include "llvm/ADT/OwningPtr.h"
19 #include "llvm/ADT/PriorityQueue.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
22 #include "llvm/CodeGen/Passes.h"
23 #include "llvm/CodeGen/RegisterClassInfo.h"
24 #include "llvm/CodeGen/ScheduleDFS.h"
25 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/ErrorHandling.h"
29 #include "llvm/Support/GraphWriter.h"
30 #include "llvm/Support/raw_ostream.h"
36 cl::opt<bool> ForceTopDown("misched-topdown", cl::Hidden,
37 cl::desc("Force top-down list scheduling"));
38 cl::opt<bool> ForceBottomUp("misched-bottomup", cl::Hidden,
39 cl::desc("Force bottom-up list scheduling"));
43 static cl::opt<bool> ViewMISchedDAGs("view-misched-dags", cl::Hidden,
44 cl::desc("Pop up a window to show MISched dags after they are processed"));
46 static cl::opt<unsigned> MISchedCutoff("misched-cutoff", cl::Hidden,
47 cl::desc("Stop scheduling after N instructions"), cl::init(~0U));
49 static bool ViewMISchedDAGs = false;
52 // Experimental heuristics
53 static cl::opt<bool> EnableLoadCluster("misched-cluster", cl::Hidden,
54 cl::desc("Enable load clustering."), cl::init(true));
56 // Experimental heuristics
57 static cl::opt<bool> EnableMacroFusion("misched-fusion", cl::Hidden,
58 cl::desc("Enable scheduling for macro fusion."), cl::init(true));
60 static cl::opt<bool> VerifyScheduling("verify-misched", cl::Hidden,
61 cl::desc("Verify machine instrs before and after machine scheduling"));
63 // DAG subtrees must have at least this many nodes.
64 static const unsigned MinSubtreeSize = 8;
66 //===----------------------------------------------------------------------===//
67 // Machine Instruction Scheduling Pass and Registry
68 //===----------------------------------------------------------------------===//
70 MachineSchedContext::MachineSchedContext():
71 MF(0), MLI(0), MDT(0), PassConfig(0), AA(0), LIS(0) {
72 RegClassInfo = new RegisterClassInfo();
75 MachineSchedContext::~MachineSchedContext() {
80 /// MachineScheduler runs after coalescing and before register allocation.
81 class MachineScheduler : public MachineSchedContext,
82 public MachineFunctionPass {
86 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
88 virtual void releaseMemory() {}
90 virtual bool runOnMachineFunction(MachineFunction&);
92 virtual void print(raw_ostream &O, const Module* = 0) const;
94 static char ID; // Class identification, replacement for typeinfo
98 char MachineScheduler::ID = 0;
100 char &llvm::MachineSchedulerID = MachineScheduler::ID;
102 INITIALIZE_PASS_BEGIN(MachineScheduler, "misched",
103 "Machine Instruction Scheduler", false, false)
104 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
105 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
106 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
107 INITIALIZE_PASS_END(MachineScheduler, "misched",
108 "Machine Instruction Scheduler", false, false)
110 MachineScheduler::MachineScheduler()
111 : MachineFunctionPass(ID) {
112 initializeMachineSchedulerPass(*PassRegistry::getPassRegistry());
115 void MachineScheduler::getAnalysisUsage(AnalysisUsage &AU) const {
116 AU.setPreservesCFG();
117 AU.addRequiredID(MachineDominatorsID);
118 AU.addRequired<MachineLoopInfo>();
119 AU.addRequired<AliasAnalysis>();
120 AU.addRequired<TargetPassConfig>();
121 AU.addRequired<SlotIndexes>();
122 AU.addPreserved<SlotIndexes>();
123 AU.addRequired<LiveIntervals>();
124 AU.addPreserved<LiveIntervals>();
125 MachineFunctionPass::getAnalysisUsage(AU);
128 MachinePassRegistry MachineSchedRegistry::Registry;
130 /// A dummy default scheduler factory indicates whether the scheduler
131 /// is overridden on the command line.
132 static ScheduleDAGInstrs *useDefaultMachineSched(MachineSchedContext *C) {
136 /// MachineSchedOpt allows command line selection of the scheduler.
137 static cl::opt<MachineSchedRegistry::ScheduleDAGCtor, false,
138 RegisterPassParser<MachineSchedRegistry> >
139 MachineSchedOpt("misched",
140 cl::init(&useDefaultMachineSched), cl::Hidden,
141 cl::desc("Machine instruction scheduler to use"));
143 static MachineSchedRegistry
144 DefaultSchedRegistry("default", "Use the target's default scheduler choice.",
145 useDefaultMachineSched);
147 /// Forward declare the standard machine scheduler. This will be used as the
148 /// default scheduler if the target does not set a default.
149 static ScheduleDAGInstrs *createConvergingSched(MachineSchedContext *C);
152 /// Decrement this iterator until reaching the top or a non-debug instr.
153 static MachineBasicBlock::iterator
154 priorNonDebug(MachineBasicBlock::iterator I, MachineBasicBlock::iterator Beg) {
155 assert(I != Beg && "reached the top of the region, cannot decrement");
157 if (!I->isDebugValue())
163 /// If this iterator is a debug value, increment until reaching the End or a
164 /// non-debug instruction.
165 static MachineBasicBlock::iterator
166 nextIfDebug(MachineBasicBlock::iterator I, MachineBasicBlock::iterator End) {
167 for(; I != End; ++I) {
168 if (!I->isDebugValue())
174 /// Top-level MachineScheduler pass driver.
176 /// Visit blocks in function order. Divide each block into scheduling regions
177 /// and visit them bottom-up. Visiting regions bottom-up is not required, but is
178 /// consistent with the DAG builder, which traverses the interior of the
179 /// scheduling regions bottom-up.
181 /// This design avoids exposing scheduling boundaries to the DAG builder,
182 /// simplifying the DAG builder's support for "special" target instructions.
183 /// At the same time the design allows target schedulers to operate across
184 /// scheduling boundaries, for example to bundle the boudary instructions
185 /// without reordering them. This creates complexity, because the target
186 /// scheduler must update the RegionBegin and RegionEnd positions cached by
187 /// ScheduleDAGInstrs whenever adding or removing instructions. A much simpler
188 /// design would be to split blocks at scheduling boundaries, but LLVM has a
189 /// general bias against block splitting purely for implementation simplicity.
190 bool MachineScheduler::runOnMachineFunction(MachineFunction &mf) {
191 DEBUG(dbgs() << "Before MISsched:\n"; mf.print(dbgs()));
193 // Initialize the context of the pass.
195 MLI = &getAnalysis<MachineLoopInfo>();
196 MDT = &getAnalysis<MachineDominatorTree>();
197 PassConfig = &getAnalysis<TargetPassConfig>();
198 AA = &getAnalysis<AliasAnalysis>();
200 LIS = &getAnalysis<LiveIntervals>();
201 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
203 if (VerifyScheduling) {
204 DEBUG(LIS->print(dbgs()));
205 MF->verify(this, "Before machine scheduling.");
207 RegClassInfo->runOnMachineFunction(*MF);
209 // Select the scheduler, or set the default.
210 MachineSchedRegistry::ScheduleDAGCtor Ctor = MachineSchedOpt;
211 if (Ctor == useDefaultMachineSched) {
212 // Get the default scheduler set by the target.
213 Ctor = MachineSchedRegistry::getDefault();
215 Ctor = createConvergingSched;
216 MachineSchedRegistry::setDefault(Ctor);
219 // Instantiate the selected scheduler.
220 OwningPtr<ScheduleDAGInstrs> Scheduler(Ctor(this));
222 // Visit all machine basic blocks.
224 // TODO: Visit blocks in global postorder or postorder within the bottom-up
225 // loop tree. Then we can optionally compute global RegPressure.
226 for (MachineFunction::iterator MBB = MF->begin(), MBBEnd = MF->end();
227 MBB != MBBEnd; ++MBB) {
229 Scheduler->startBlock(MBB);
231 // Break the block into scheduling regions [I, RegionEnd), and schedule each
232 // region as soon as it is discovered. RegionEnd points the scheduling
233 // boundary at the bottom of the region. The DAG does not include RegionEnd,
234 // but the region does (i.e. the next RegionEnd is above the previous
235 // RegionBegin). If the current block has no terminator then RegionEnd ==
236 // MBB->end() for the bottom region.
238 // The Scheduler may insert instructions during either schedule() or
239 // exitRegion(), even for empty regions. So the local iterators 'I' and
240 // 'RegionEnd' are invalid across these calls.
241 unsigned RemainingInstrs = MBB->size();
242 for(MachineBasicBlock::iterator RegionEnd = MBB->end();
243 RegionEnd != MBB->begin(); RegionEnd = Scheduler->begin()) {
245 // Avoid decrementing RegionEnd for blocks with no terminator.
246 if (RegionEnd != MBB->end()
247 || TII->isSchedulingBoundary(llvm::prior(RegionEnd), MBB, *MF)) {
249 // Count the boundary instruction.
253 // The next region starts above the previous region. Look backward in the
254 // instruction stream until we find the nearest boundary.
255 MachineBasicBlock::iterator I = RegionEnd;
256 for(;I != MBB->begin(); --I, --RemainingInstrs) {
257 if (TII->isSchedulingBoundary(llvm::prior(I), MBB, *MF))
260 // Notify the scheduler of the region, even if we may skip scheduling
261 // it. Perhaps it still needs to be bundled.
262 Scheduler->enterRegion(MBB, I, RegionEnd, RemainingInstrs);
264 // Skip empty scheduling regions (0 or 1 schedulable instructions).
265 if (I == RegionEnd || I == llvm::prior(RegionEnd)) {
266 // Close the current region. Bundle the terminator if needed.
267 // This invalidates 'RegionEnd' and 'I'.
268 Scheduler->exitRegion();
271 DEBUG(dbgs() << "********** MI Scheduling **********\n");
272 DEBUG(dbgs() << MF->getName()
273 << ":BB#" << MBB->getNumber() << " " << MBB->getName()
274 << "\n From: " << *I << " To: ";
275 if (RegionEnd != MBB->end()) dbgs() << *RegionEnd;
276 else dbgs() << "End";
277 dbgs() << " Remaining: " << RemainingInstrs << "\n");
279 // Schedule a region: possibly reorder instructions.
280 // This invalidates 'RegionEnd' and 'I'.
281 Scheduler->schedule();
283 // Close the current region.
284 Scheduler->exitRegion();
286 // Scheduling has invalidated the current iterator 'I'. Ask the
287 // scheduler for the top of it's scheduled region.
288 RegionEnd = Scheduler->begin();
290 assert(RemainingInstrs == 0 && "Instruction count mismatch!");
291 Scheduler->finishBlock();
293 Scheduler->finalizeSchedule();
294 DEBUG(LIS->print(dbgs()));
295 if (VerifyScheduling)
296 MF->verify(this, "After machine scheduling.");
300 void MachineScheduler::print(raw_ostream &O, const Module* m) const {
304 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
305 void ReadyQueue::dump() {
306 dbgs() << Name << ": ";
307 for (unsigned i = 0, e = Queue.size(); i < e; ++i)
308 dbgs() << Queue[i]->NodeNum << " ";
313 //===----------------------------------------------------------------------===//
314 // ScheduleDAGMI - Base class for MachineInstr scheduling with LiveIntervals
316 //===----------------------------------------------------------------------===//
318 ScheduleDAGMI::~ScheduleDAGMI() {
320 DeleteContainerPointers(Mutations);
324 bool ScheduleDAGMI::addEdge(SUnit *SuccSU, const SDep &PredDep) {
325 if (SuccSU != &ExitSU) {
326 // Do not use WillCreateCycle, it assumes SD scheduling.
327 // If Pred is reachable from Succ, then the edge creates a cycle.
328 if (Topo.IsReachable(PredDep.getSUnit(), SuccSU))
330 Topo.AddPred(SuccSU, PredDep.getSUnit());
332 SuccSU->addPred(PredDep, /*Required=*/!PredDep.isArtificial());
333 // Return true regardless of whether a new edge needed to be inserted.
337 /// ReleaseSucc - Decrement the NumPredsLeft count of a successor. When
338 /// NumPredsLeft reaches zero, release the successor node.
340 /// FIXME: Adjust SuccSU height based on MinLatency.
341 void ScheduleDAGMI::releaseSucc(SUnit *SU, SDep *SuccEdge) {
342 SUnit *SuccSU = SuccEdge->getSUnit();
344 if (SuccEdge->isWeak()) {
345 --SuccSU->WeakPredsLeft;
346 if (SuccEdge->isCluster())
347 NextClusterSucc = SuccSU;
351 if (SuccSU->NumPredsLeft == 0) {
352 dbgs() << "*** Scheduling failed! ***\n";
354 dbgs() << " has been released too many times!\n";
358 --SuccSU->NumPredsLeft;
359 if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU)
360 SchedImpl->releaseTopNode(SuccSU);
363 /// releaseSuccessors - Call releaseSucc on each of SU's successors.
364 void ScheduleDAGMI::releaseSuccessors(SUnit *SU) {
365 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
367 releaseSucc(SU, &*I);
371 /// ReleasePred - Decrement the NumSuccsLeft count of a predecessor. When
372 /// NumSuccsLeft reaches zero, release the predecessor node.
374 /// FIXME: Adjust PredSU height based on MinLatency.
375 void ScheduleDAGMI::releasePred(SUnit *SU, SDep *PredEdge) {
376 SUnit *PredSU = PredEdge->getSUnit();
378 if (PredEdge->isWeak()) {
379 --PredSU->WeakSuccsLeft;
380 if (PredEdge->isCluster())
381 NextClusterPred = PredSU;
385 if (PredSU->NumSuccsLeft == 0) {
386 dbgs() << "*** Scheduling failed! ***\n";
388 dbgs() << " has been released too many times!\n";
392 --PredSU->NumSuccsLeft;
393 if (PredSU->NumSuccsLeft == 0 && PredSU != &EntrySU)
394 SchedImpl->releaseBottomNode(PredSU);
397 /// releasePredecessors - Call releasePred on each of SU's predecessors.
398 void ScheduleDAGMI::releasePredecessors(SUnit *SU) {
399 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
401 releasePred(SU, &*I);
405 void ScheduleDAGMI::moveInstruction(MachineInstr *MI,
406 MachineBasicBlock::iterator InsertPos) {
407 // Advance RegionBegin if the first instruction moves down.
408 if (&*RegionBegin == MI)
411 // Update the instruction stream.
412 BB->splice(InsertPos, BB, MI);
414 // Update LiveIntervals
415 LIS->handleMove(MI, /*UpdateFlags=*/true);
417 // Recede RegionBegin if an instruction moves above the first.
418 if (RegionBegin == InsertPos)
422 bool ScheduleDAGMI::checkSchedLimit() {
424 if (NumInstrsScheduled == MISchedCutoff && MISchedCutoff != ~0U) {
425 CurrentTop = CurrentBottom;
428 ++NumInstrsScheduled;
433 /// enterRegion - Called back from MachineScheduler::runOnMachineFunction after
434 /// crossing a scheduling boundary. [begin, end) includes all instructions in
435 /// the region, including the boundary itself and single-instruction regions
436 /// that don't get scheduled.
437 void ScheduleDAGMI::enterRegion(MachineBasicBlock *bb,
438 MachineBasicBlock::iterator begin,
439 MachineBasicBlock::iterator end,
442 ScheduleDAGInstrs::enterRegion(bb, begin, end, endcount);
444 // For convenience remember the end of the liveness region.
446 (RegionEnd == bb->end()) ? RegionEnd : llvm::next(RegionEnd);
449 // Setup the register pressure trackers for the top scheduled top and bottom
450 // scheduled regions.
451 void ScheduleDAGMI::initRegPressure() {
452 TopRPTracker.init(&MF, RegClassInfo, LIS, BB, RegionBegin);
453 BotRPTracker.init(&MF, RegClassInfo, LIS, BB, LiveRegionEnd);
455 // Close the RPTracker to finalize live ins.
456 RPTracker.closeRegion();
458 DEBUG(RPTracker.getPressure().dump(TRI));
460 // Initialize the live ins and live outs.
461 TopRPTracker.addLiveRegs(RPTracker.getPressure().LiveInRegs);
462 BotRPTracker.addLiveRegs(RPTracker.getPressure().LiveOutRegs);
464 // Close one end of the tracker so we can call
465 // getMaxUpward/DownwardPressureDelta before advancing across any
466 // instructions. This converts currently live regs into live ins/outs.
467 TopRPTracker.closeTop();
468 BotRPTracker.closeBottom();
470 // Account for liveness generated by the region boundary.
471 if (LiveRegionEnd != RegionEnd)
472 BotRPTracker.recede();
474 assert(BotRPTracker.getPos() == RegionEnd && "Can't find the region bottom");
476 // Cache the list of excess pressure sets in this region. This will also track
477 // the max pressure in the scheduled code for these sets.
478 RegionCriticalPSets.clear();
479 const std::vector<unsigned> &RegionPressure =
480 RPTracker.getPressure().MaxSetPressure;
481 for (unsigned i = 0, e = RegionPressure.size(); i < e; ++i) {
482 unsigned Limit = TRI->getRegPressureSetLimit(i);
483 DEBUG(dbgs() << TRI->getRegPressureSetName(i)
485 << " Actual " << RegionPressure[i] << "\n");
486 if (RegionPressure[i] > Limit)
487 RegionCriticalPSets.push_back(PressureElement(i, 0));
489 DEBUG(dbgs() << "Excess PSets: ";
490 for (unsigned i = 0, e = RegionCriticalPSets.size(); i != e; ++i)
491 dbgs() << TRI->getRegPressureSetName(
492 RegionCriticalPSets[i].PSetID) << " ";
496 // FIXME: When the pressure tracker deals in pressure differences then we won't
497 // iterate over all RegionCriticalPSets[i].
499 updateScheduledPressure(const std::vector<unsigned> &NewMaxPressure) {
500 for (unsigned i = 0, e = RegionCriticalPSets.size(); i < e; ++i) {
501 unsigned ID = RegionCriticalPSets[i].PSetID;
502 int &MaxUnits = RegionCriticalPSets[i].UnitIncrease;
503 if ((int)NewMaxPressure[ID] > MaxUnits)
504 MaxUnits = NewMaxPressure[ID];
508 /// schedule - Called back from MachineScheduler::runOnMachineFunction
509 /// after setting up the current scheduling region. [RegionBegin, RegionEnd)
510 /// only includes instructions that have DAG nodes, not scheduling boundaries.
512 /// This is a skeletal driver, with all the functionality pushed into helpers,
513 /// so that it can be easilly extended by experimental schedulers. Generally,
514 /// implementing MachineSchedStrategy should be sufficient to implement a new
515 /// scheduling algorithm. However, if a scheduler further subclasses
516 /// ScheduleDAGMI then it will want to override this virtual method in order to
517 /// update any specialized state.
518 void ScheduleDAGMI::schedule() {
519 buildDAGWithRegPressure();
521 Topo.InitDAGTopologicalSorting();
525 SmallVector<SUnit*, 8> TopRoots, BotRoots;
526 findRootsAndBiasEdges(TopRoots, BotRoots);
528 // Initialize the strategy before modifying the DAG.
529 // This may initialize a DFSResult to be used for queue priority.
530 SchedImpl->initialize(this);
532 DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
533 SUnits[su].dumpAll(this));
534 if (ViewMISchedDAGs) viewGraph();
536 // Initialize ready queues now that the DAG and priority data are finalized.
537 initQueues(TopRoots, BotRoots);
539 bool IsTopNode = false;
540 while (SUnit *SU = SchedImpl->pickNode(IsTopNode)) {
541 assert(!SU->isScheduled && "Node already scheduled");
542 if (!checkSchedLimit())
545 scheduleMI(SU, IsTopNode);
547 updateQueues(SU, IsTopNode);
549 assert(CurrentTop == CurrentBottom && "Nonempty unscheduled zone.");
554 unsigned BBNum = begin()->getParent()->getNumber();
555 dbgs() << "*** Final schedule for BB#" << BBNum << " ***\n";
561 /// Build the DAG and setup three register pressure trackers.
562 void ScheduleDAGMI::buildDAGWithRegPressure() {
563 // Initialize the register pressure tracker used by buildSchedGraph.
564 RPTracker.init(&MF, RegClassInfo, LIS, BB, LiveRegionEnd);
566 // Account for liveness generate by the region boundary.
567 if (LiveRegionEnd != RegionEnd)
570 // Build the DAG, and compute current register pressure.
571 buildSchedGraph(AA, &RPTracker);
573 // Initialize top/bottom trackers after computing region pressure.
577 /// Apply each ScheduleDAGMutation step in order.
578 void ScheduleDAGMI::postprocessDAG() {
579 for (unsigned i = 0, e = Mutations.size(); i < e; ++i) {
580 Mutations[i]->apply(this);
584 void ScheduleDAGMI::computeDFSResult() {
586 DFSResult = new SchedDFSResult(/*BottomU*/true, MinSubtreeSize);
588 ScheduledTrees.clear();
589 DFSResult->resize(SUnits.size());
590 DFSResult->compute(SUnits);
591 ScheduledTrees.resize(DFSResult->getNumSubtrees());
594 void ScheduleDAGMI::findRootsAndBiasEdges(SmallVectorImpl<SUnit*> &TopRoots,
595 SmallVectorImpl<SUnit*> &BotRoots) {
596 for (std::vector<SUnit>::iterator
597 I = SUnits.begin(), E = SUnits.end(); I != E; ++I) {
599 assert(!SU->isBoundaryNode() && "Boundary node should not be in SUnits");
601 // Order predecessors so DFSResult follows the critical path.
602 SU->biasCriticalPath();
604 // A SUnit is ready to top schedule if it has no predecessors.
605 if (!I->NumPredsLeft)
606 TopRoots.push_back(SU);
607 // A SUnit is ready to bottom schedule if it has no successors.
608 if (!I->NumSuccsLeft)
609 BotRoots.push_back(SU);
611 ExitSU.biasCriticalPath();
614 /// Identify DAG roots and setup scheduler queues.
615 void ScheduleDAGMI::initQueues(ArrayRef<SUnit*> TopRoots,
616 ArrayRef<SUnit*> BotRoots) {
617 NextClusterSucc = NULL;
618 NextClusterPred = NULL;
620 // Release all DAG roots for scheduling, not including EntrySU/ExitSU.
622 // Nodes with unreleased weak edges can still be roots.
623 // Release top roots in forward order.
624 for (SmallVectorImpl<SUnit*>::const_iterator
625 I = TopRoots.begin(), E = TopRoots.end(); I != E; ++I) {
626 SchedImpl->releaseTopNode(*I);
628 // Release bottom roots in reverse order so the higher priority nodes appear
629 // first. This is more natural and slightly more efficient.
630 for (SmallVectorImpl<SUnit*>::const_reverse_iterator
631 I = BotRoots.rbegin(), E = BotRoots.rend(); I != E; ++I) {
632 SchedImpl->releaseBottomNode(*I);
635 releaseSuccessors(&EntrySU);
636 releasePredecessors(&ExitSU);
638 SchedImpl->registerRoots();
640 // Advance past initial DebugValues.
641 assert(TopRPTracker.getPos() == RegionBegin && "bad initial Top tracker");
642 CurrentTop = nextIfDebug(RegionBegin, RegionEnd);
643 TopRPTracker.setPos(CurrentTop);
645 CurrentBottom = RegionEnd;
648 /// Move an instruction and update register pressure.
649 void ScheduleDAGMI::scheduleMI(SUnit *SU, bool IsTopNode) {
650 // Move the instruction to its new location in the instruction stream.
651 MachineInstr *MI = SU->getInstr();
654 assert(SU->isTopReady() && "node still has unscheduled dependencies");
655 if (&*CurrentTop == MI)
656 CurrentTop = nextIfDebug(++CurrentTop, CurrentBottom);
658 moveInstruction(MI, CurrentTop);
659 TopRPTracker.setPos(MI);
662 // Update top scheduled pressure.
663 TopRPTracker.advance();
664 assert(TopRPTracker.getPos() == CurrentTop && "out of sync");
665 updateScheduledPressure(TopRPTracker.getPressure().MaxSetPressure);
668 assert(SU->isBottomReady() && "node still has unscheduled dependencies");
669 MachineBasicBlock::iterator priorII =
670 priorNonDebug(CurrentBottom, CurrentTop);
672 CurrentBottom = priorII;
674 if (&*CurrentTop == MI) {
675 CurrentTop = nextIfDebug(++CurrentTop, priorII);
676 TopRPTracker.setPos(CurrentTop);
678 moveInstruction(MI, CurrentBottom);
681 // Update bottom scheduled pressure.
682 BotRPTracker.recede();
683 assert(BotRPTracker.getPos() == CurrentBottom && "out of sync");
684 updateScheduledPressure(BotRPTracker.getPressure().MaxSetPressure);
688 /// Update scheduler queues after scheduling an instruction.
689 void ScheduleDAGMI::updateQueues(SUnit *SU, bool IsTopNode) {
690 // Release dependent instructions for scheduling.
692 releaseSuccessors(SU);
694 releasePredecessors(SU);
696 SU->isScheduled = true;
699 unsigned SubtreeID = DFSResult->getSubtreeID(SU);
700 if (!ScheduledTrees.test(SubtreeID)) {
701 ScheduledTrees.set(SubtreeID);
702 DFSResult->scheduleTree(SubtreeID);
703 SchedImpl->scheduleTree(SubtreeID);
707 // Notify the scheduling strategy after updating the DAG.
708 SchedImpl->schedNode(SU, IsTopNode);
711 /// Reinsert any remaining debug_values, just like the PostRA scheduler.
712 void ScheduleDAGMI::placeDebugValues() {
713 // If first instruction was a DBG_VALUE then put it back.
715 BB->splice(RegionBegin, BB, FirstDbgValue);
716 RegionBegin = FirstDbgValue;
719 for (std::vector<std::pair<MachineInstr *, MachineInstr *> >::iterator
720 DI = DbgValues.end(), DE = DbgValues.begin(); DI != DE; --DI) {
721 std::pair<MachineInstr *, MachineInstr *> P = *prior(DI);
722 MachineInstr *DbgValue = P.first;
723 MachineBasicBlock::iterator OrigPrevMI = P.second;
724 if (&*RegionBegin == DbgValue)
726 BB->splice(++OrigPrevMI, BB, DbgValue);
727 if (OrigPrevMI == llvm::prior(RegionEnd))
728 RegionEnd = DbgValue;
731 FirstDbgValue = NULL;
734 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
735 void ScheduleDAGMI::dumpSchedule() const {
736 for (MachineBasicBlock::iterator MI = begin(), ME = end(); MI != ME; ++MI) {
737 if (SUnit *SU = getSUnit(&(*MI)))
740 dbgs() << "Missing SUnit\n";
745 //===----------------------------------------------------------------------===//
746 // LoadClusterMutation - DAG post-processing to cluster loads.
747 //===----------------------------------------------------------------------===//
750 /// \brief Post-process the DAG to create cluster edges between neighboring
752 class LoadClusterMutation : public ScheduleDAGMutation {
757 LoadInfo(SUnit *su, unsigned reg, unsigned ofs)
758 : SU(su), BaseReg(reg), Offset(ofs) {}
760 static bool LoadInfoLess(const LoadClusterMutation::LoadInfo &LHS,
761 const LoadClusterMutation::LoadInfo &RHS);
763 const TargetInstrInfo *TII;
764 const TargetRegisterInfo *TRI;
766 LoadClusterMutation(const TargetInstrInfo *tii,
767 const TargetRegisterInfo *tri)
768 : TII(tii), TRI(tri) {}
770 virtual void apply(ScheduleDAGMI *DAG);
772 void clusterNeighboringLoads(ArrayRef<SUnit*> Loads, ScheduleDAGMI *DAG);
776 bool LoadClusterMutation::LoadInfoLess(
777 const LoadClusterMutation::LoadInfo &LHS,
778 const LoadClusterMutation::LoadInfo &RHS) {
779 if (LHS.BaseReg != RHS.BaseReg)
780 return LHS.BaseReg < RHS.BaseReg;
781 return LHS.Offset < RHS.Offset;
784 void LoadClusterMutation::clusterNeighboringLoads(ArrayRef<SUnit*> Loads,
785 ScheduleDAGMI *DAG) {
786 SmallVector<LoadClusterMutation::LoadInfo,32> LoadRecords;
787 for (unsigned Idx = 0, End = Loads.size(); Idx != End; ++Idx) {
788 SUnit *SU = Loads[Idx];
791 if (TII->getLdStBaseRegImmOfs(SU->getInstr(), BaseReg, Offset, TRI))
792 LoadRecords.push_back(LoadInfo(SU, BaseReg, Offset));
794 if (LoadRecords.size() < 2)
796 std::sort(LoadRecords.begin(), LoadRecords.end(), LoadInfoLess);
797 unsigned ClusterLength = 1;
798 for (unsigned Idx = 0, End = LoadRecords.size(); Idx < (End - 1); ++Idx) {
799 if (LoadRecords[Idx].BaseReg != LoadRecords[Idx+1].BaseReg) {
804 SUnit *SUa = LoadRecords[Idx].SU;
805 SUnit *SUb = LoadRecords[Idx+1].SU;
806 if (TII->shouldClusterLoads(SUa->getInstr(), SUb->getInstr(), ClusterLength)
807 && DAG->addEdge(SUb, SDep(SUa, SDep::Cluster))) {
809 DEBUG(dbgs() << "Cluster loads SU(" << SUa->NodeNum << ") - SU("
810 << SUb->NodeNum << ")\n");
811 // Copy successor edges from SUa to SUb. Interleaving computation
812 // dependent on SUa can prevent load combining due to register reuse.
813 // Predecessor edges do not need to be copied from SUb to SUa since nearby
814 // loads should have effectively the same inputs.
815 for (SUnit::const_succ_iterator
816 SI = SUa->Succs.begin(), SE = SUa->Succs.end(); SI != SE; ++SI) {
817 if (SI->getSUnit() == SUb)
819 DEBUG(dbgs() << " Copy Succ SU(" << SI->getSUnit()->NodeNum << ")\n");
820 DAG->addEdge(SI->getSUnit(), SDep(SUb, SDep::Artificial));
829 /// \brief Callback from DAG postProcessing to create cluster edges for loads.
830 void LoadClusterMutation::apply(ScheduleDAGMI *DAG) {
831 // Map DAG NodeNum to store chain ID.
832 DenseMap<unsigned, unsigned> StoreChainIDs;
833 // Map each store chain to a set of dependent loads.
834 SmallVector<SmallVector<SUnit*,4>, 32> StoreChainDependents;
835 for (unsigned Idx = 0, End = DAG->SUnits.size(); Idx != End; ++Idx) {
836 SUnit *SU = &DAG->SUnits[Idx];
837 if (!SU->getInstr()->mayLoad())
839 unsigned ChainPredID = DAG->SUnits.size();
840 for (SUnit::const_pred_iterator
841 PI = SU->Preds.begin(), PE = SU->Preds.end(); PI != PE; ++PI) {
843 ChainPredID = PI->getSUnit()->NodeNum;
847 // Check if this chain-like pred has been seen
848 // before. ChainPredID==MaxNodeID for loads at the top of the schedule.
849 unsigned NumChains = StoreChainDependents.size();
850 std::pair<DenseMap<unsigned, unsigned>::iterator, bool> Result =
851 StoreChainIDs.insert(std::make_pair(ChainPredID, NumChains));
853 StoreChainDependents.resize(NumChains + 1);
854 StoreChainDependents[Result.first->second].push_back(SU);
856 // Iterate over the store chains.
857 for (unsigned Idx = 0, End = StoreChainDependents.size(); Idx != End; ++Idx)
858 clusterNeighboringLoads(StoreChainDependents[Idx], DAG);
861 //===----------------------------------------------------------------------===//
862 // MacroFusion - DAG post-processing to encourage fusion of macro ops.
863 //===----------------------------------------------------------------------===//
866 /// \brief Post-process the DAG to create cluster edges between instructions
867 /// that may be fused by the processor into a single operation.
868 class MacroFusion : public ScheduleDAGMutation {
869 const TargetInstrInfo *TII;
871 MacroFusion(const TargetInstrInfo *tii): TII(tii) {}
873 virtual void apply(ScheduleDAGMI *DAG);
877 /// \brief Callback from DAG postProcessing to create cluster edges to encourage
878 /// fused operations.
879 void MacroFusion::apply(ScheduleDAGMI *DAG) {
880 // For now, assume targets can only fuse with the branch.
881 MachineInstr *Branch = DAG->ExitSU.getInstr();
885 for (unsigned Idx = DAG->SUnits.size(); Idx > 0;) {
886 SUnit *SU = &DAG->SUnits[--Idx];
887 if (!TII->shouldScheduleAdjacent(SU->getInstr(), Branch))
890 // Create a single weak edge from SU to ExitSU. The only effect is to cause
891 // bottom-up scheduling to heavily prioritize the clustered SU. There is no
892 // need to copy predecessor edges from ExitSU to SU, since top-down
893 // scheduling cannot prioritize ExitSU anyway. To defer top-down scheduling
894 // of SU, we could create an artificial edge from the deepest root, but it
895 // hasn't been needed yet.
896 bool Success = DAG->addEdge(&DAG->ExitSU, SDep(SU, SDep::Cluster));
898 assert(Success && "No DAG nodes should be reachable from ExitSU");
900 DEBUG(dbgs() << "Macro Fuse SU(" << SU->NodeNum << ")\n");
905 //===----------------------------------------------------------------------===//
906 // ConvergingScheduler - Implementation of the standard MachineSchedStrategy.
907 //===----------------------------------------------------------------------===//
910 /// ConvergingScheduler shrinks the unscheduled zone using heuristics to balance
912 class ConvergingScheduler : public MachineSchedStrategy {
914 /// Represent the type of SchedCandidate found within a single queue.
915 /// pickNodeBidirectional depends on these listed by decreasing priority.
917 NoCand, SingleExcess, SingleCritical, Cluster,
918 ResourceReduce, ResourceDemand, BotHeightReduce, BotPathReduce,
919 TopDepthReduce, TopPathReduce, SingleMax, MultiPressure, NextDefUse,
923 static const char *getReasonStr(ConvergingScheduler::CandReason Reason);
926 /// Policy for scheduling the next instruction in the candidate's zone.
929 unsigned ReduceResIdx;
930 unsigned DemandResIdx;
932 CandPolicy(): ReduceLatency(false), ReduceResIdx(0), DemandResIdx(0) {}
935 /// Status of an instruction's critical resource consumption.
936 struct SchedResourceDelta {
937 // Count critical resources in the scheduled region required by SU.
938 unsigned CritResources;
940 // Count critical resources from another region consumed by SU.
941 unsigned DemandedResources;
943 SchedResourceDelta(): CritResources(0), DemandedResources(0) {}
945 bool operator==(const SchedResourceDelta &RHS) const {
946 return CritResources == RHS.CritResources
947 && DemandedResources == RHS.DemandedResources;
949 bool operator!=(const SchedResourceDelta &RHS) const {
950 return !operator==(RHS);
954 /// Store the state used by ConvergingScheduler heuristics, required for the
955 /// lifetime of one invocation of pickNode().
956 struct SchedCandidate {
959 // The best SUnit candidate.
962 // The reason for this candidate.
965 // Register pressure values for the best candidate.
966 RegPressureDelta RPDelta;
968 // Critical resource consumption of the best candidate.
969 SchedResourceDelta ResDelta;
971 SchedCandidate(const CandPolicy &policy)
972 : Policy(policy), SU(NULL), Reason(NoCand) {}
974 bool isValid() const { return SU; }
976 // Copy the status of another candidate without changing policy.
977 void setBest(SchedCandidate &Best) {
978 assert(Best.Reason != NoCand && "uninitialized Sched candidate");
980 Reason = Best.Reason;
981 RPDelta = Best.RPDelta;
982 ResDelta = Best.ResDelta;
985 void initResourceDelta(const ScheduleDAGMI *DAG,
986 const TargetSchedModel *SchedModel);
989 /// Summarize the unscheduled region.
990 struct SchedRemainder {
991 // Critical path through the DAG in expected latency.
992 unsigned CriticalPath;
994 // Unscheduled resources
995 SmallVector<unsigned, 16> RemainingCounts;
996 // Critical resource for the unscheduled zone.
998 // Number of micro-ops left to schedule.
999 unsigned RemainingMicroOps;
1003 RemainingCounts.clear();
1005 RemainingMicroOps = 0;
1008 SchedRemainder() { reset(); }
1010 void init(ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel);
1012 unsigned getMaxRemainingCount(const TargetSchedModel *SchedModel) const {
1013 if (!SchedModel->hasInstrSchedModel())
1017 RemainingMicroOps * SchedModel->getMicroOpFactor(),
1018 RemainingCounts[CritResIdx]);
1022 /// Each Scheduling boundary is associated with ready queues. It tracks the
1023 /// current cycle in the direction of movement, and maintains the state
1024 /// of "hazards" and other interlocks at the current cycle.
1025 struct SchedBoundary {
1027 const TargetSchedModel *SchedModel;
1028 SchedRemainder *Rem;
1030 ReadyQueue Available;
1034 // For heuristics, keep a list of the nodes that immediately depend on the
1035 // most recently scheduled node.
1036 SmallPtrSet<const SUnit*, 8> NextSUs;
1038 ScheduleHazardRecognizer *HazardRec;
1041 unsigned IssueCount;
1043 /// MinReadyCycle - Cycle of the soonest available instruction.
1044 unsigned MinReadyCycle;
1046 // The expected latency of the critical path in this scheduled zone.
1047 unsigned ExpectedLatency;
1049 // Resources used in the scheduled zone beyond this boundary.
1050 SmallVector<unsigned, 16> ResourceCounts;
1052 // Cache the critical resources ID in this scheduled zone.
1053 unsigned CritResIdx;
1055 // Is the scheduled region resource limited vs. latency limited.
1056 bool IsResourceLimited;
1058 unsigned ExpectedCount;
1061 // Remember the greatest min operand latency.
1062 unsigned MaxMinLatency;
1066 // A new HazardRec is created for each DAG and owned by SchedBoundary.
1071 CheckPending = false;
1076 MinReadyCycle = UINT_MAX;
1077 ExpectedLatency = 0;
1078 ResourceCounts.resize(1);
1079 assert(!ResourceCounts[0] && "nonzero count for bad resource");
1081 IsResourceLimited = false;
1086 // Reserve a zero-count for invalid CritResIdx.
1087 ResourceCounts.resize(1);
1090 /// Pending queues extend the ready queues with the same ID and the
1091 /// PendingFlag set.
1092 SchedBoundary(unsigned ID, const Twine &Name):
1093 DAG(0), SchedModel(0), Rem(0), Available(ID, Name+".A"),
1094 Pending(ID << ConvergingScheduler::LogMaxQID, Name+".P"),
1099 ~SchedBoundary() { delete HazardRec; }
1101 void init(ScheduleDAGMI *dag, const TargetSchedModel *smodel,
1102 SchedRemainder *rem);
1104 bool isTop() const {
1105 return Available.getID() == ConvergingScheduler::TopQID;
1108 unsigned getUnscheduledLatency(SUnit *SU) const {
1110 return SU->getHeight();
1111 return SU->getDepth() + SU->Latency;
1114 unsigned getCriticalCount() const {
1115 return ResourceCounts[CritResIdx];
1118 bool checkHazard(SUnit *SU);
1120 void setLatencyPolicy(CandPolicy &Policy);
1122 void releaseNode(SUnit *SU, unsigned ReadyCycle);
1126 void countResource(unsigned PIdx, unsigned Cycles);
1128 void bumpNode(SUnit *SU);
1130 void releasePending();
1132 void removeReady(SUnit *SU);
1134 SUnit *pickOnlyChoice();
1139 const TargetSchedModel *SchedModel;
1140 const TargetRegisterInfo *TRI;
1142 // State of the top and bottom scheduled instruction boundaries.
1148 /// SUnit::NodeQueueId: 0 (none), 1 (top), 2 (bot), 3 (both)
1155 ConvergingScheduler():
1156 DAG(0), SchedModel(0), TRI(0), Top(TopQID, "TopQ"), Bot(BotQID, "BotQ") {}
1158 virtual void initialize(ScheduleDAGMI *dag);
1160 virtual SUnit *pickNode(bool &IsTopNode);
1162 virtual void schedNode(SUnit *SU, bool IsTopNode);
1164 virtual void releaseTopNode(SUnit *SU);
1166 virtual void releaseBottomNode(SUnit *SU);
1168 virtual void registerRoots();
1172 ConvergingScheduler::SchedBoundary &CriticalZone,
1173 ConvergingScheduler::SchedCandidate &CriticalCand,
1174 ConvergingScheduler::SchedBoundary &OppositeZone,
1175 ConvergingScheduler::SchedCandidate &OppositeCand);
1177 void checkResourceLimits(ConvergingScheduler::SchedCandidate &TopCand,
1178 ConvergingScheduler::SchedCandidate &BotCand);
1180 void tryCandidate(SchedCandidate &Cand,
1181 SchedCandidate &TryCand,
1182 SchedBoundary &Zone,
1183 const RegPressureTracker &RPTracker,
1184 RegPressureTracker &TempTracker);
1186 SUnit *pickNodeBidirectional(bool &IsTopNode);
1188 void pickNodeFromQueue(SchedBoundary &Zone,
1189 const RegPressureTracker &RPTracker,
1190 SchedCandidate &Candidate);
1193 void traceCandidate(const SchedCandidate &Cand, const SchedBoundary &Zone);
1198 void ConvergingScheduler::SchedRemainder::
1199 init(ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel) {
1201 if (!SchedModel->hasInstrSchedModel())
1203 RemainingCounts.resize(SchedModel->getNumProcResourceKinds());
1204 for (std::vector<SUnit>::iterator
1205 I = DAG->SUnits.begin(), E = DAG->SUnits.end(); I != E; ++I) {
1206 const MCSchedClassDesc *SC = DAG->getSchedClass(&*I);
1207 RemainingMicroOps += SchedModel->getNumMicroOps(I->getInstr(), SC);
1208 for (TargetSchedModel::ProcResIter
1209 PI = SchedModel->getWriteProcResBegin(SC),
1210 PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) {
1211 unsigned PIdx = PI->ProcResourceIdx;
1212 unsigned Factor = SchedModel->getResourceFactor(PIdx);
1213 RemainingCounts[PIdx] += (Factor * PI->Cycles);
1216 for (unsigned PIdx = 0, PEnd = SchedModel->getNumProcResourceKinds();
1217 PIdx != PEnd; ++PIdx) {
1218 if ((int)(RemainingCounts[PIdx] - RemainingCounts[CritResIdx])
1219 >= (int)SchedModel->getLatencyFactor()) {
1225 void ConvergingScheduler::SchedBoundary::
1226 init(ScheduleDAGMI *dag, const TargetSchedModel *smodel, SchedRemainder *rem) {
1229 SchedModel = smodel;
1231 if (SchedModel->hasInstrSchedModel())
1232 ResourceCounts.resize(SchedModel->getNumProcResourceKinds());
1235 void ConvergingScheduler::initialize(ScheduleDAGMI *dag) {
1237 SchedModel = DAG->getSchedModel();
1240 Rem.init(DAG, SchedModel);
1241 Top.init(DAG, SchedModel, &Rem);
1242 Bot.init(DAG, SchedModel, &Rem);
1244 DAG->computeDFSResult();
1246 // Initialize resource counts.
1248 // Initialize the HazardRecognizers. If itineraries don't exist, are empty, or
1249 // are disabled, then these HazardRecs will be disabled.
1250 const InstrItineraryData *Itin = SchedModel->getInstrItineraries();
1251 const TargetMachine &TM = DAG->MF.getTarget();
1252 Top.HazardRec = TM.getInstrInfo()->CreateTargetMIHazardRecognizer(Itin, DAG);
1253 Bot.HazardRec = TM.getInstrInfo()->CreateTargetMIHazardRecognizer(Itin, DAG);
1255 assert((!ForceTopDown || !ForceBottomUp) &&
1256 "-misched-topdown incompatible with -misched-bottomup");
1259 void ConvergingScheduler::releaseTopNode(SUnit *SU) {
1260 if (SU->isScheduled)
1263 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
1265 unsigned PredReadyCycle = I->getSUnit()->TopReadyCycle;
1266 unsigned MinLatency = I->getMinLatency();
1268 Top.MaxMinLatency = std::max(MinLatency, Top.MaxMinLatency);
1270 if (SU->TopReadyCycle < PredReadyCycle + MinLatency)
1271 SU->TopReadyCycle = PredReadyCycle + MinLatency;
1273 Top.releaseNode(SU, SU->TopReadyCycle);
1276 void ConvergingScheduler::releaseBottomNode(SUnit *SU) {
1277 if (SU->isScheduled)
1280 assert(SU->getInstr() && "Scheduled SUnit must have instr");
1282 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
1286 unsigned SuccReadyCycle = I->getSUnit()->BotReadyCycle;
1287 unsigned MinLatency = I->getMinLatency();
1289 Bot.MaxMinLatency = std::max(MinLatency, Bot.MaxMinLatency);
1291 if (SU->BotReadyCycle < SuccReadyCycle + MinLatency)
1292 SU->BotReadyCycle = SuccReadyCycle + MinLatency;
1294 Bot.releaseNode(SU, SU->BotReadyCycle);
1297 void ConvergingScheduler::registerRoots() {
1298 Rem.CriticalPath = DAG->ExitSU.getDepth();
1299 // Some roots may not feed into ExitSU. Check all of them in case.
1300 for (std::vector<SUnit*>::const_iterator
1301 I = Bot.Available.begin(), E = Bot.Available.end(); I != E; ++I) {
1302 if ((*I)->getDepth() > Rem.CriticalPath)
1303 Rem.CriticalPath = (*I)->getDepth();
1305 DEBUG(dbgs() << "Critical Path: " << Rem.CriticalPath << '\n');
1308 /// Does this SU have a hazard within the current instruction group.
1310 /// The scheduler supports two modes of hazard recognition. The first is the
1311 /// ScheduleHazardRecognizer API. It is a fully general hazard recognizer that
1312 /// supports highly complicated in-order reservation tables
1313 /// (ScoreboardHazardRecognizer) and arbitraty target-specific logic.
1315 /// The second is a streamlined mechanism that checks for hazards based on
1316 /// simple counters that the scheduler itself maintains. It explicitly checks
1317 /// for instruction dispatch limitations, including the number of micro-ops that
1318 /// can dispatch per cycle.
1320 /// TODO: Also check whether the SU must start a new group.
1321 bool ConvergingScheduler::SchedBoundary::checkHazard(SUnit *SU) {
1322 if (HazardRec->isEnabled())
1323 return HazardRec->getHazardType(SU) != ScheduleHazardRecognizer::NoHazard;
1325 unsigned uops = SchedModel->getNumMicroOps(SU->getInstr());
1326 if ((IssueCount > 0) && (IssueCount + uops > SchedModel->getIssueWidth())) {
1327 DEBUG(dbgs() << " SU(" << SU->NodeNum << ") uops="
1328 << SchedModel->getNumMicroOps(SU->getInstr()) << '\n');
1334 /// Compute the remaining latency to determine whether ILP should be increased.
1335 void ConvergingScheduler::SchedBoundary::setLatencyPolicy(CandPolicy &Policy) {
1336 // FIXME: compile time. In all, we visit four queues here one we should only
1337 // need to visit the one that was last popped if we cache the result.
1338 unsigned RemLatency = 0;
1339 for (ReadyQueue::iterator I = Available.begin(), E = Available.end();
1341 unsigned L = getUnscheduledLatency(*I);
1345 for (ReadyQueue::iterator I = Pending.begin(), E = Pending.end();
1347 unsigned L = getUnscheduledLatency(*I);
1351 unsigned CriticalPathLimit = Rem->CriticalPath + SchedModel->getILPWindow();
1352 if (RemLatency + ExpectedLatency >= CriticalPathLimit
1353 && RemLatency > Rem->getMaxRemainingCount(SchedModel)) {
1354 Policy.ReduceLatency = true;
1355 DEBUG(dbgs() << "Increase ILP: " << Available.getName() << '\n');
1359 void ConvergingScheduler::SchedBoundary::releaseNode(SUnit *SU,
1360 unsigned ReadyCycle) {
1362 if (ReadyCycle < MinReadyCycle)
1363 MinReadyCycle = ReadyCycle;
1365 // Check for interlocks first. For the purpose of other heuristics, an
1366 // instruction that cannot issue appears as if it's not in the ReadyQueue.
1367 if (ReadyCycle > CurrCycle || checkHazard(SU))
1372 // Record this node as an immediate dependent of the scheduled node.
1376 /// Move the boundary of scheduled code by one cycle.
1377 void ConvergingScheduler::SchedBoundary::bumpCycle() {
1378 unsigned Width = SchedModel->getIssueWidth();
1379 IssueCount = (IssueCount <= Width) ? 0 : IssueCount - Width;
1381 unsigned NextCycle = CurrCycle + 1;
1382 assert(MinReadyCycle < UINT_MAX && "MinReadyCycle uninitialized");
1383 if (MinReadyCycle > NextCycle) {
1385 NextCycle = MinReadyCycle;
1388 if (!HazardRec->isEnabled()) {
1389 // Bypass HazardRec virtual calls.
1390 CurrCycle = NextCycle;
1393 // Bypass getHazardType calls in case of long latency.
1394 for (; CurrCycle != NextCycle; ++CurrCycle) {
1396 HazardRec->AdvanceCycle();
1398 HazardRec->RecedeCycle();
1401 CheckPending = true;
1402 IsResourceLimited = getCriticalCount() > std::max(ExpectedLatency, CurrCycle);
1404 DEBUG(dbgs() << " *** " << Available.getName() << " cycle "
1405 << CurrCycle << '\n');
1408 /// Add the given processor resource to this scheduled zone.
1409 void ConvergingScheduler::SchedBoundary::countResource(unsigned PIdx,
1411 unsigned Factor = SchedModel->getResourceFactor(PIdx);
1412 DEBUG(dbgs() << " " << SchedModel->getProcResource(PIdx)->Name
1413 << " +(" << Cycles << "x" << Factor
1414 << ") / " << SchedModel->getLatencyFactor() << '\n');
1416 unsigned Count = Factor * Cycles;
1417 ResourceCounts[PIdx] += Count;
1418 assert(Rem->RemainingCounts[PIdx] >= Count && "resource double counted");
1419 Rem->RemainingCounts[PIdx] -= Count;
1421 // Check if this resource exceeds the current critical resource by a full
1422 // cycle. If so, it becomes the critical resource.
1423 if ((int)(ResourceCounts[PIdx] - ResourceCounts[CritResIdx])
1424 >= (int)SchedModel->getLatencyFactor()) {
1426 DEBUG(dbgs() << " *** Critical resource "
1427 << SchedModel->getProcResource(PIdx)->Name << " x"
1428 << ResourceCounts[PIdx] << '\n');
1432 /// Move the boundary of scheduled code by one SUnit.
1433 void ConvergingScheduler::SchedBoundary::bumpNode(SUnit *SU) {
1434 // Update the reservation table.
1435 if (HazardRec->isEnabled()) {
1436 if (!isTop() && SU->isCall) {
1437 // Calls are scheduled with their preceding instructions. For bottom-up
1438 // scheduling, clear the pipeline state before emitting.
1441 HazardRec->EmitInstruction(SU);
1443 // Update resource counts and critical resource.
1444 if (SchedModel->hasInstrSchedModel()) {
1445 const MCSchedClassDesc *SC = DAG->getSchedClass(SU);
1446 Rem->RemainingMicroOps -= SchedModel->getNumMicroOps(SU->getInstr(), SC);
1447 for (TargetSchedModel::ProcResIter
1448 PI = SchedModel->getWriteProcResBegin(SC),
1449 PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) {
1450 countResource(PI->ProcResourceIdx, PI->Cycles);
1454 if (SU->getDepth() > ExpectedLatency)
1455 ExpectedLatency = SU->getDepth();
1458 if (SU->getHeight() > ExpectedLatency)
1459 ExpectedLatency = SU->getHeight();
1462 IsResourceLimited = getCriticalCount() > std::max(ExpectedLatency, CurrCycle);
1464 // Check the instruction group dispatch limit.
1465 // TODO: Check if this SU must end a dispatch group.
1466 IssueCount += SchedModel->getNumMicroOps(SU->getInstr());
1468 // checkHazard prevents scheduling multiple instructions per cycle that exceed
1469 // issue width. However, we commonly reach the maximum. In this case
1470 // opportunistically bump the cycle to avoid uselessly checking everything in
1471 // the readyQ. Furthermore, a single instruction may produce more than one
1472 // cycle's worth of micro-ops.
1473 if (IssueCount >= SchedModel->getIssueWidth()) {
1474 DEBUG(dbgs() << " *** Max instrs at cycle " << CurrCycle << '\n');
1479 /// Release pending ready nodes in to the available queue. This makes them
1480 /// visible to heuristics.
1481 void ConvergingScheduler::SchedBoundary::releasePending() {
1482 // If the available queue is empty, it is safe to reset MinReadyCycle.
1483 if (Available.empty())
1484 MinReadyCycle = UINT_MAX;
1486 // Check to see if any of the pending instructions are ready to issue. If
1487 // so, add them to the available queue.
1488 for (unsigned i = 0, e = Pending.size(); i != e; ++i) {
1489 SUnit *SU = *(Pending.begin()+i);
1490 unsigned ReadyCycle = isTop() ? SU->TopReadyCycle : SU->BotReadyCycle;
1492 if (ReadyCycle < MinReadyCycle)
1493 MinReadyCycle = ReadyCycle;
1495 if (ReadyCycle > CurrCycle)
1498 if (checkHazard(SU))
1502 Pending.remove(Pending.begin()+i);
1505 DEBUG(if (!Pending.empty()) Pending.dump());
1506 CheckPending = false;
1509 /// Remove SU from the ready set for this boundary.
1510 void ConvergingScheduler::SchedBoundary::removeReady(SUnit *SU) {
1511 if (Available.isInQueue(SU))
1512 Available.remove(Available.find(SU));
1514 assert(Pending.isInQueue(SU) && "bad ready count");
1515 Pending.remove(Pending.find(SU));
1519 /// If this queue only has one ready candidate, return it. As a side effect,
1520 /// defer any nodes that now hit a hazard, and advance the cycle until at least
1521 /// one node is ready. If multiple instructions are ready, return NULL.
1522 SUnit *ConvergingScheduler::SchedBoundary::pickOnlyChoice() {
1526 if (IssueCount > 0) {
1527 // Defer any ready instrs that now have a hazard.
1528 for (ReadyQueue::iterator I = Available.begin(); I != Available.end();) {
1529 if (checkHazard(*I)) {
1531 I = Available.remove(I);
1537 for (unsigned i = 0; Available.empty(); ++i) {
1538 assert(i <= (HazardRec->getMaxLookAhead() + MaxMinLatency) &&
1539 "permanent hazard"); (void)i;
1543 if (Available.size() == 1)
1544 return *Available.begin();
1548 /// Record the candidate policy for opposite zones with different critical
1551 /// If the CriticalZone is latency limited, don't force a policy for the
1552 /// candidates here. Instead, setLatencyPolicy sets ReduceLatency if needed.
1553 void ConvergingScheduler::balanceZones(
1554 ConvergingScheduler::SchedBoundary &CriticalZone,
1555 ConvergingScheduler::SchedCandidate &CriticalCand,
1556 ConvergingScheduler::SchedBoundary &OppositeZone,
1557 ConvergingScheduler::SchedCandidate &OppositeCand) {
1559 if (!CriticalZone.IsResourceLimited)
1561 assert(SchedModel->hasInstrSchedModel() && "required schedmodel");
1563 SchedRemainder *Rem = CriticalZone.Rem;
1565 // If the critical zone is overconsuming a resource relative to the
1566 // remainder, try to reduce it.
1567 unsigned RemainingCritCount =
1568 Rem->RemainingCounts[CriticalZone.CritResIdx];
1569 if ((int)(Rem->getMaxRemainingCount(SchedModel) - RemainingCritCount)
1570 > (int)SchedModel->getLatencyFactor()) {
1571 CriticalCand.Policy.ReduceResIdx = CriticalZone.CritResIdx;
1572 DEBUG(dbgs() << "Balance " << CriticalZone.Available.getName() << " reduce "
1573 << SchedModel->getProcResource(CriticalZone.CritResIdx)->Name
1576 // If the other zone is underconsuming a resource relative to the full zone,
1577 // try to increase it.
1578 unsigned OppositeCount =
1579 OppositeZone.ResourceCounts[CriticalZone.CritResIdx];
1580 if ((int)(OppositeZone.ExpectedCount - OppositeCount)
1581 > (int)SchedModel->getLatencyFactor()) {
1582 OppositeCand.Policy.DemandResIdx = CriticalZone.CritResIdx;
1583 DEBUG(dbgs() << "Balance " << OppositeZone.Available.getName() << " demand "
1584 << SchedModel->getProcResource(OppositeZone.CritResIdx)->Name
1589 /// Determine if the scheduled zones exceed resource limits or critical path and
1590 /// set each candidate's ReduceHeight policy accordingly.
1591 void ConvergingScheduler::checkResourceLimits(
1592 ConvergingScheduler::SchedCandidate &TopCand,
1593 ConvergingScheduler::SchedCandidate &BotCand) {
1595 // Set ReduceLatency to true if needed.
1596 Bot.setLatencyPolicy(BotCand.Policy);
1597 Top.setLatencyPolicy(TopCand.Policy);
1599 // Handle resource-limited regions.
1600 if (Top.IsResourceLimited && Bot.IsResourceLimited
1601 && Top.CritResIdx == Bot.CritResIdx) {
1602 // If the scheduled critical resource in both zones is no longer the
1603 // critical remaining resource, attempt to reduce resource height both ways.
1604 if (Top.CritResIdx != Rem.CritResIdx) {
1605 TopCand.Policy.ReduceResIdx = Top.CritResIdx;
1606 BotCand.Policy.ReduceResIdx = Bot.CritResIdx;
1607 DEBUG(dbgs() << "Reduce scheduled "
1608 << SchedModel->getProcResource(Top.CritResIdx)->Name << '\n');
1612 // Handle latency-limited regions.
1613 if (!Top.IsResourceLimited && !Bot.IsResourceLimited) {
1614 // If the total scheduled expected latency exceeds the region's critical
1615 // path then reduce latency both ways.
1617 // Just because a zone is not resource limited does not mean it is latency
1618 // limited. Unbuffered resource, such as max micro-ops may cause CurrCycle
1619 // to exceed expected latency.
1620 if ((Top.ExpectedLatency + Bot.ExpectedLatency >= Rem.CriticalPath)
1621 && (Rem.CriticalPath > Top.CurrCycle + Bot.CurrCycle)) {
1622 TopCand.Policy.ReduceLatency = true;
1623 BotCand.Policy.ReduceLatency = true;
1624 DEBUG(dbgs() << "Reduce scheduled latency " << Top.ExpectedLatency
1625 << " + " << Bot.ExpectedLatency << '\n');
1629 // The critical resource is different in each zone, so request balancing.
1631 // Compute the cost of each zone.
1632 Top.ExpectedCount = std::max(Top.ExpectedLatency, Top.CurrCycle);
1633 Top.ExpectedCount = std::max(
1634 Top.getCriticalCount(),
1635 Top.ExpectedCount * SchedModel->getLatencyFactor());
1636 Bot.ExpectedCount = std::max(Bot.ExpectedLatency, Bot.CurrCycle);
1637 Bot.ExpectedCount = std::max(
1638 Bot.getCriticalCount(),
1639 Bot.ExpectedCount * SchedModel->getLatencyFactor());
1641 balanceZones(Top, TopCand, Bot, BotCand);
1642 balanceZones(Bot, BotCand, Top, TopCand);
1645 void ConvergingScheduler::SchedCandidate::
1646 initResourceDelta(const ScheduleDAGMI *DAG,
1647 const TargetSchedModel *SchedModel) {
1648 if (!Policy.ReduceResIdx && !Policy.DemandResIdx)
1651 const MCSchedClassDesc *SC = DAG->getSchedClass(SU);
1652 for (TargetSchedModel::ProcResIter
1653 PI = SchedModel->getWriteProcResBegin(SC),
1654 PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) {
1655 if (PI->ProcResourceIdx == Policy.ReduceResIdx)
1656 ResDelta.CritResources += PI->Cycles;
1657 if (PI->ProcResourceIdx == Policy.DemandResIdx)
1658 ResDelta.DemandedResources += PI->Cycles;
1662 /// Return true if this heuristic determines order.
1663 static bool tryLess(unsigned TryVal, unsigned CandVal,
1664 ConvergingScheduler::SchedCandidate &TryCand,
1665 ConvergingScheduler::SchedCandidate &Cand,
1666 ConvergingScheduler::CandReason Reason) {
1667 if (TryVal < CandVal) {
1668 TryCand.Reason = Reason;
1671 if (TryVal > CandVal) {
1672 if (Cand.Reason > Reason)
1673 Cand.Reason = Reason;
1679 static bool tryGreater(unsigned TryVal, unsigned CandVal,
1680 ConvergingScheduler::SchedCandidate &TryCand,
1681 ConvergingScheduler::SchedCandidate &Cand,
1682 ConvergingScheduler::CandReason Reason) {
1683 if (TryVal > CandVal) {
1684 TryCand.Reason = Reason;
1687 if (TryVal < CandVal) {
1688 if (Cand.Reason > Reason)
1689 Cand.Reason = Reason;
1695 static unsigned getWeakLeft(const SUnit *SU, bool isTop) {
1696 return (isTop) ? SU->WeakPredsLeft : SU->WeakSuccsLeft;
1699 /// Apply a set of heursitics to a new candidate. Heuristics are currently
1700 /// hierarchical. This may be more efficient than a graduated cost model because
1701 /// we don't need to evaluate all aspects of the model for each node in the
1702 /// queue. But it's really done to make the heuristics easier to debug and
1703 /// statistically analyze.
1705 /// \param Cand provides the policy and current best candidate.
1706 /// \param TryCand refers to the next SUnit candidate, otherwise uninitialized.
1707 /// \param Zone describes the scheduled zone that we are extending.
1708 /// \param RPTracker describes reg pressure within the scheduled zone.
1709 /// \param TempTracker is a scratch pressure tracker to reuse in queries.
1710 void ConvergingScheduler::tryCandidate(SchedCandidate &Cand,
1711 SchedCandidate &TryCand,
1712 SchedBoundary &Zone,
1713 const RegPressureTracker &RPTracker,
1714 RegPressureTracker &TempTracker) {
1716 // Always initialize TryCand's RPDelta.
1717 TempTracker.getMaxPressureDelta(TryCand.SU->getInstr(), TryCand.RPDelta,
1718 DAG->getRegionCriticalPSets(),
1719 DAG->getRegPressure().MaxSetPressure);
1721 // Initialize the candidate if needed.
1722 if (!Cand.isValid()) {
1723 TryCand.Reason = NodeOrder;
1726 // Avoid exceeding the target's limit.
1727 if (tryLess(TryCand.RPDelta.Excess.UnitIncrease,
1728 Cand.RPDelta.Excess.UnitIncrease, TryCand, Cand, SingleExcess))
1730 if (Cand.Reason == SingleExcess)
1731 Cand.Reason = MultiPressure;
1733 // Avoid increasing the max critical pressure in the scheduled region.
1734 if (tryLess(TryCand.RPDelta.CriticalMax.UnitIncrease,
1735 Cand.RPDelta.CriticalMax.UnitIncrease,
1736 TryCand, Cand, SingleCritical))
1738 if (Cand.Reason == SingleCritical)
1739 Cand.Reason = MultiPressure;
1741 // Keep clustered nodes together to encourage downstream peephole
1742 // optimizations which may reduce resource requirements.
1744 // This is a best effort to set things up for a post-RA pass. Optimizations
1745 // like generating loads of multiple registers should ideally be done within
1746 // the scheduler pass by combining the loads during DAG postprocessing.
1747 const SUnit *NextClusterSU =
1748 Zone.isTop() ? DAG->getNextClusterSucc() : DAG->getNextClusterPred();
1749 if (tryGreater(TryCand.SU == NextClusterSU, Cand.SU == NextClusterSU,
1750 TryCand, Cand, Cluster))
1752 // Currently, weak edges are for clustering, so we hard-code that reason.
1753 // However, deferring the current TryCand will not change Cand's reason.
1754 CandReason OrigReason = Cand.Reason;
1755 if (tryLess(getWeakLeft(TryCand.SU, Zone.isTop()),
1756 getWeakLeft(Cand.SU, Zone.isTop()),
1757 TryCand, Cand, Cluster)) {
1758 Cand.Reason = OrigReason;
1761 // Avoid critical resource consumption and balance the schedule.
1762 TryCand.initResourceDelta(DAG, SchedModel);
1763 if (tryLess(TryCand.ResDelta.CritResources, Cand.ResDelta.CritResources,
1764 TryCand, Cand, ResourceReduce))
1766 if (tryGreater(TryCand.ResDelta.DemandedResources,
1767 Cand.ResDelta.DemandedResources,
1768 TryCand, Cand, ResourceDemand))
1771 // Avoid serializing long latency dependence chains.
1772 if (Cand.Policy.ReduceLatency) {
1774 if (Cand.SU->getDepth() * SchedModel->getLatencyFactor()
1775 > Zone.ExpectedCount) {
1776 if (tryLess(TryCand.SU->getDepth(), Cand.SU->getDepth(),
1777 TryCand, Cand, TopDepthReduce))
1780 if (tryGreater(TryCand.SU->getHeight(), Cand.SU->getHeight(),
1781 TryCand, Cand, TopPathReduce))
1785 if (Cand.SU->getHeight() * SchedModel->getLatencyFactor()
1786 > Zone.ExpectedCount) {
1787 if (tryLess(TryCand.SU->getHeight(), Cand.SU->getHeight(),
1788 TryCand, Cand, BotHeightReduce))
1791 if (tryGreater(TryCand.SU->getDepth(), Cand.SU->getDepth(),
1792 TryCand, Cand, BotPathReduce))
1797 // Avoid increasing the max pressure of the entire region.
1798 if (tryLess(TryCand.RPDelta.CurrentMax.UnitIncrease,
1799 Cand.RPDelta.CurrentMax.UnitIncrease, TryCand, Cand, SingleMax))
1801 if (Cand.Reason == SingleMax)
1802 Cand.Reason = MultiPressure;
1804 // Prefer immediate defs/users of the last scheduled instruction. This is a
1805 // nice pressure avoidance strategy that also conserves the processor's
1806 // register renaming resources and keeps the machine code readable.
1807 if (tryGreater(Zone.NextSUs.count(TryCand.SU), Zone.NextSUs.count(Cand.SU),
1808 TryCand, Cand, NextDefUse))
1811 // Fall through to original instruction order.
1812 if ((Zone.isTop() && TryCand.SU->NodeNum < Cand.SU->NodeNum)
1813 || (!Zone.isTop() && TryCand.SU->NodeNum > Cand.SU->NodeNum)) {
1814 TryCand.Reason = NodeOrder;
1818 /// pickNodeFromQueue helper that returns true if the LHS reg pressure effect is
1819 /// more desirable than RHS from scheduling standpoint.
1820 static bool compareRPDelta(const RegPressureDelta &LHS,
1821 const RegPressureDelta &RHS) {
1822 // Compare each component of pressure in decreasing order of importance
1823 // without checking if any are valid. Invalid PressureElements are assumed to
1824 // have UnitIncrease==0, so are neutral.
1826 // Avoid increasing the max critical pressure in the scheduled region.
1827 if (LHS.Excess.UnitIncrease != RHS.Excess.UnitIncrease) {
1828 DEBUG(dbgs() << "RP excess top - bot: "
1829 << (LHS.Excess.UnitIncrease - RHS.Excess.UnitIncrease) << '\n');
1830 return LHS.Excess.UnitIncrease < RHS.Excess.UnitIncrease;
1832 // Avoid increasing the max critical pressure in the scheduled region.
1833 if (LHS.CriticalMax.UnitIncrease != RHS.CriticalMax.UnitIncrease) {
1834 DEBUG(dbgs() << "RP critical top - bot: "
1835 << (LHS.CriticalMax.UnitIncrease - RHS.CriticalMax.UnitIncrease)
1837 return LHS.CriticalMax.UnitIncrease < RHS.CriticalMax.UnitIncrease;
1839 // Avoid increasing the max pressure of the entire region.
1840 if (LHS.CurrentMax.UnitIncrease != RHS.CurrentMax.UnitIncrease) {
1841 DEBUG(dbgs() << "RP current top - bot: "
1842 << (LHS.CurrentMax.UnitIncrease - RHS.CurrentMax.UnitIncrease)
1844 return LHS.CurrentMax.UnitIncrease < RHS.CurrentMax.UnitIncrease;
1850 const char *ConvergingScheduler::getReasonStr(
1851 ConvergingScheduler::CandReason Reason) {
1853 case NoCand: return "NOCAND ";
1854 case SingleExcess: return "REG-EXCESS";
1855 case SingleCritical: return "REG-CRIT ";
1856 case Cluster: return "CLUSTER ";
1857 case SingleMax: return "REG-MAX ";
1858 case MultiPressure: return "REG-MULTI ";
1859 case ResourceReduce: return "RES-REDUCE";
1860 case ResourceDemand: return "RES-DEMAND";
1861 case TopDepthReduce: return "TOP-DEPTH ";
1862 case TopPathReduce: return "TOP-PATH ";
1863 case BotHeightReduce:return "BOT-HEIGHT";
1864 case BotPathReduce: return "BOT-PATH ";
1865 case NextDefUse: return "DEF-USE ";
1866 case NodeOrder: return "ORDER ";
1868 llvm_unreachable("Unknown reason!");
1871 void ConvergingScheduler::traceCandidate(const SchedCandidate &Cand,
1872 const SchedBoundary &Zone) {
1873 const char *Label = getReasonStr(Cand.Reason);
1875 unsigned ResIdx = 0;
1876 unsigned Latency = 0;
1877 switch (Cand.Reason) {
1881 P = Cand.RPDelta.Excess;
1883 case SingleCritical:
1884 P = Cand.RPDelta.CriticalMax;
1887 P = Cand.RPDelta.CurrentMax;
1889 case ResourceReduce:
1890 ResIdx = Cand.Policy.ReduceResIdx;
1892 case ResourceDemand:
1893 ResIdx = Cand.Policy.DemandResIdx;
1895 case TopDepthReduce:
1896 Latency = Cand.SU->getDepth();
1899 Latency = Cand.SU->getHeight();
1901 case BotHeightReduce:
1902 Latency = Cand.SU->getHeight();
1905 Latency = Cand.SU->getDepth();
1908 dbgs() << Label << " " << Zone.Available.getName() << " ";
1910 dbgs() << TRI->getRegPressureSetName(P.PSetID) << ":" << P.UnitIncrease
1915 dbgs() << SchedModel->getProcResource(ResIdx)->Name << " ";
1919 dbgs() << Latency << " cycles ";
1926 /// Pick the best candidate from the top queue.
1928 /// TODO: getMaxPressureDelta results can be mostly cached for each SUnit during
1929 /// DAG building. To adjust for the current scheduling location we need to
1930 /// maintain the number of vreg uses remaining to be top-scheduled.
1931 void ConvergingScheduler::pickNodeFromQueue(SchedBoundary &Zone,
1932 const RegPressureTracker &RPTracker,
1933 SchedCandidate &Cand) {
1934 ReadyQueue &Q = Zone.Available;
1938 // getMaxPressureDelta temporarily modifies the tracker.
1939 RegPressureTracker &TempTracker = const_cast<RegPressureTracker&>(RPTracker);
1941 for (ReadyQueue::iterator I = Q.begin(), E = Q.end(); I != E; ++I) {
1943 SchedCandidate TryCand(Cand.Policy);
1945 tryCandidate(Cand, TryCand, Zone, RPTracker, TempTracker);
1946 if (TryCand.Reason != NoCand) {
1947 // Initialize resource delta if needed in case future heuristics query it.
1948 if (TryCand.ResDelta == SchedResourceDelta())
1949 TryCand.initResourceDelta(DAG, SchedModel);
1950 Cand.setBest(TryCand);
1951 DEBUG(traceCandidate(Cand, Zone));
1956 static void tracePick(const ConvergingScheduler::SchedCandidate &Cand,
1958 DEBUG(dbgs() << "Pick " << (IsTop ? "top" : "bot")
1959 << " SU(" << Cand.SU->NodeNum << ") "
1960 << ConvergingScheduler::getReasonStr(Cand.Reason) << '\n');
1963 /// Pick the best candidate node from either the top or bottom queue.
1964 SUnit *ConvergingScheduler::pickNodeBidirectional(bool &IsTopNode) {
1965 // Schedule as far as possible in the direction of no choice. This is most
1966 // efficient, but also provides the best heuristics for CriticalPSets.
1967 if (SUnit *SU = Bot.pickOnlyChoice()) {
1971 if (SUnit *SU = Top.pickOnlyChoice()) {
1975 CandPolicy NoPolicy;
1976 SchedCandidate BotCand(NoPolicy);
1977 SchedCandidate TopCand(NoPolicy);
1978 checkResourceLimits(TopCand, BotCand);
1980 // Prefer bottom scheduling when heuristics are silent.
1981 pickNodeFromQueue(Bot, DAG->getBotRPTracker(), BotCand);
1982 assert(BotCand.Reason != NoCand && "failed to find the first candidate");
1984 // If either Q has a single candidate that provides the least increase in
1985 // Excess pressure, we can immediately schedule from that Q.
1987 // RegionCriticalPSets summarizes the pressure within the scheduled region and
1988 // affects picking from either Q. If scheduling in one direction must
1989 // increase pressure for one of the excess PSets, then schedule in that
1990 // direction first to provide more freedom in the other direction.
1991 if (BotCand.Reason == SingleExcess || BotCand.Reason == SingleCritical) {
1993 tracePick(BotCand, IsTopNode);
1996 // Check if the top Q has a better candidate.
1997 pickNodeFromQueue(Top, DAG->getTopRPTracker(), TopCand);
1998 assert(TopCand.Reason != NoCand && "failed to find the first candidate");
2000 // If either Q has a single candidate that minimizes pressure above the
2001 // original region's pressure pick it.
2002 if (TopCand.Reason <= SingleMax || BotCand.Reason <= SingleMax) {
2003 if (TopCand.Reason < BotCand.Reason) {
2005 tracePick(TopCand, IsTopNode);
2009 tracePick(BotCand, IsTopNode);
2012 // Check for a salient pressure difference and pick the best from either side.
2013 if (compareRPDelta(TopCand.RPDelta, BotCand.RPDelta)) {
2015 tracePick(TopCand, IsTopNode);
2018 // Otherwise prefer the bottom candidate, in node order if all else failed.
2019 if (TopCand.Reason < BotCand.Reason) {
2021 tracePick(TopCand, IsTopNode);
2025 tracePick(BotCand, IsTopNode);
2029 /// Pick the best node to balance the schedule. Implements MachineSchedStrategy.
2030 SUnit *ConvergingScheduler::pickNode(bool &IsTopNode) {
2031 if (DAG->top() == DAG->bottom()) {
2032 assert(Top.Available.empty() && Top.Pending.empty() &&
2033 Bot.Available.empty() && Bot.Pending.empty() && "ReadyQ garbage");
2039 SU = Top.pickOnlyChoice();
2041 CandPolicy NoPolicy;
2042 SchedCandidate TopCand(NoPolicy);
2043 pickNodeFromQueue(Top, DAG->getTopRPTracker(), TopCand);
2044 assert(TopCand.Reason != NoCand && "failed to find the first candidate");
2049 else if (ForceBottomUp) {
2050 SU = Bot.pickOnlyChoice();
2052 CandPolicy NoPolicy;
2053 SchedCandidate BotCand(NoPolicy);
2054 pickNodeFromQueue(Bot, DAG->getBotRPTracker(), BotCand);
2055 assert(BotCand.Reason != NoCand && "failed to find the first candidate");
2061 SU = pickNodeBidirectional(IsTopNode);
2063 } while (SU->isScheduled);
2065 if (SU->isTopReady())
2066 Top.removeReady(SU);
2067 if (SU->isBottomReady())
2068 Bot.removeReady(SU);
2070 DEBUG(dbgs() << "*** " << (IsTopNode ? "Top" : "Bottom")
2071 << " Scheduling Instruction in cycle "
2072 << (IsTopNode ? Top.CurrCycle : Bot.CurrCycle) << '\n';
2077 /// Update the scheduler's state after scheduling a node. This is the same node
2078 /// that was just returned by pickNode(). However, ScheduleDAGMI needs to update
2079 /// it's state based on the current cycle before MachineSchedStrategy does.
2080 void ConvergingScheduler::schedNode(SUnit *SU, bool IsTopNode) {
2082 SU->TopReadyCycle = Top.CurrCycle;
2086 SU->BotReadyCycle = Bot.CurrCycle;
2091 /// Create the standard converging machine scheduler. This will be used as the
2092 /// default scheduler if the target does not set a default.
2093 static ScheduleDAGInstrs *createConvergingSched(MachineSchedContext *C) {
2094 assert((!ForceTopDown || !ForceBottomUp) &&
2095 "-misched-topdown incompatible with -misched-bottomup");
2096 ScheduleDAGMI *DAG = new ScheduleDAGMI(C, new ConvergingScheduler());
2097 // Register DAG post-processors.
2098 if (EnableLoadCluster)
2099 DAG->addMutation(new LoadClusterMutation(DAG->TII, DAG->TRI));
2100 if (EnableMacroFusion)
2101 DAG->addMutation(new MacroFusion(DAG->TII));
2104 static MachineSchedRegistry
2105 ConvergingSchedRegistry("converge", "Standard converging scheduler.",
2106 createConvergingSched);
2108 //===----------------------------------------------------------------------===//
2109 // ILP Scheduler. Currently for experimental analysis of heuristics.
2110 //===----------------------------------------------------------------------===//
2113 /// \brief Order nodes by the ILP metric.
2115 const SchedDFSResult *DFSResult;
2116 const BitVector *ScheduledTrees;
2119 ILPOrder(bool MaxILP): DFSResult(0), ScheduledTrees(0), MaximizeILP(MaxILP) {}
2121 /// \brief Apply a less-than relation on node priority.
2123 /// (Return true if A comes after B in the Q.)
2124 bool operator()(const SUnit *A, const SUnit *B) const {
2125 unsigned SchedTreeA = DFSResult->getSubtreeID(A);
2126 unsigned SchedTreeB = DFSResult->getSubtreeID(B);
2127 if (SchedTreeA != SchedTreeB) {
2128 // Unscheduled trees have lower priority.
2129 if (ScheduledTrees->test(SchedTreeA) != ScheduledTrees->test(SchedTreeB))
2130 return ScheduledTrees->test(SchedTreeB);
2132 // Trees with shallower connections have have lower priority.
2133 if (DFSResult->getSubtreeLevel(SchedTreeA)
2134 != DFSResult->getSubtreeLevel(SchedTreeB)) {
2135 return DFSResult->getSubtreeLevel(SchedTreeA)
2136 < DFSResult->getSubtreeLevel(SchedTreeB);
2140 return DFSResult->getILP(A) < DFSResult->getILP(B);
2142 return DFSResult->getILP(A) > DFSResult->getILP(B);
2146 /// \brief Schedule based on the ILP metric.
2147 class ILPScheduler : public MachineSchedStrategy {
2148 /// In case all subtrees are eventually connected to a common root through
2149 /// data dependence (e.g. reduction), place an upper limit on their size.
2151 /// FIXME: A subtree limit is generally good, but in the situation commented
2152 /// above, where multiple similar subtrees feed a common root, we should
2153 /// only split at a point where the resulting subtrees will be balanced.
2154 /// (a motivating test case must be found).
2155 static const unsigned SubtreeLimit = 16;
2160 std::vector<SUnit*> ReadyQ;
2162 ILPScheduler(bool MaximizeILP): DAG(0), Cmp(MaximizeILP) {}
2164 virtual void initialize(ScheduleDAGMI *dag) {
2166 DAG->computeDFSResult();
2167 Cmp.DFSResult = DAG->getDFSResult();
2168 Cmp.ScheduledTrees = &DAG->getScheduledTrees();
2172 virtual void registerRoots() {
2173 // Restore the heap in ReadyQ with the updated DFS results.
2174 std::make_heap(ReadyQ.begin(), ReadyQ.end(), Cmp);
2177 /// Implement MachineSchedStrategy interface.
2178 /// -----------------------------------------
2180 /// Callback to select the highest priority node from the ready Q.
2181 virtual SUnit *pickNode(bool &IsTopNode) {
2182 if (ReadyQ.empty()) return NULL;
2183 pop_heap(ReadyQ.begin(), ReadyQ.end(), Cmp);
2184 SUnit *SU = ReadyQ.back();
2187 DEBUG(dbgs() << "*** Scheduling " << "SU(" << SU->NodeNum << "): "
2189 << " ILP: " << DAG->getDFSResult()->getILP(SU)
2190 << " Tree: " << DAG->getDFSResult()->getSubtreeID(SU) << " @"
2191 << DAG->getDFSResult()->getSubtreeLevel(
2192 DAG->getDFSResult()->getSubtreeID(SU)) << '\n');
2196 /// \brief Scheduler callback to notify that a new subtree is scheduled.
2197 virtual void scheduleTree(unsigned SubtreeID) {
2198 std::make_heap(ReadyQ.begin(), ReadyQ.end(), Cmp);
2201 /// Callback after a node is scheduled. Mark a newly scheduled tree, notify
2202 /// DFSResults, and resort the priority Q.
2203 virtual void schedNode(SUnit *SU, bool IsTopNode) {
2204 assert(!IsTopNode && "SchedDFSResult needs bottom-up");
2207 virtual void releaseTopNode(SUnit *) { /*only called for top roots*/ }
2209 virtual void releaseBottomNode(SUnit *SU) {
2210 ReadyQ.push_back(SU);
2211 std::push_heap(ReadyQ.begin(), ReadyQ.end(), Cmp);
2216 static ScheduleDAGInstrs *createILPMaxScheduler(MachineSchedContext *C) {
2217 return new ScheduleDAGMI(C, new ILPScheduler(true));
2219 static ScheduleDAGInstrs *createILPMinScheduler(MachineSchedContext *C) {
2220 return new ScheduleDAGMI(C, new ILPScheduler(false));
2222 static MachineSchedRegistry ILPMaxRegistry(
2223 "ilpmax", "Schedule bottom-up for max ILP", createILPMaxScheduler);
2224 static MachineSchedRegistry ILPMinRegistry(
2225 "ilpmin", "Schedule bottom-up for min ILP", createILPMinScheduler);
2227 //===----------------------------------------------------------------------===//
2228 // Machine Instruction Shuffler for Correctness Testing
2229 //===----------------------------------------------------------------------===//
2233 /// Apply a less-than relation on the node order, which corresponds to the
2234 /// instruction order prior to scheduling. IsReverse implements greater-than.
2235 template<bool IsReverse>
2237 bool operator()(SUnit *A, SUnit *B) const {
2239 return A->NodeNum > B->NodeNum;
2241 return A->NodeNum < B->NodeNum;
2245 /// Reorder instructions as much as possible.
2246 class InstructionShuffler : public MachineSchedStrategy {
2250 // Using a less-than relation (SUnitOrder<false>) for the TopQ priority
2251 // gives nodes with a higher number higher priority causing the latest
2252 // instructions to be scheduled first.
2253 PriorityQueue<SUnit*, std::vector<SUnit*>, SUnitOrder<false> >
2255 // When scheduling bottom-up, use greater-than as the queue priority.
2256 PriorityQueue<SUnit*, std::vector<SUnit*>, SUnitOrder<true> >
2259 InstructionShuffler(bool alternate, bool topdown)
2260 : IsAlternating(alternate), IsTopDown(topdown) {}
2262 virtual void initialize(ScheduleDAGMI *) {
2267 /// Implement MachineSchedStrategy interface.
2268 /// -----------------------------------------
2270 virtual SUnit *pickNode(bool &IsTopNode) {
2274 if (TopQ.empty()) return NULL;
2277 } while (SU->isScheduled);
2282 if (BottomQ.empty()) return NULL;
2285 } while (SU->isScheduled);
2289 IsTopDown = !IsTopDown;
2293 virtual void schedNode(SUnit *SU, bool IsTopNode) {}
2295 virtual void releaseTopNode(SUnit *SU) {
2298 virtual void releaseBottomNode(SUnit *SU) {
2304 static ScheduleDAGInstrs *createInstructionShuffler(MachineSchedContext *C) {
2305 bool Alternate = !ForceTopDown && !ForceBottomUp;
2306 bool TopDown = !ForceBottomUp;
2307 assert((TopDown || !ForceTopDown) &&
2308 "-misched-topdown incompatible with -misched-bottomup");
2309 return new ScheduleDAGMI(C, new InstructionShuffler(Alternate, TopDown));
2311 static MachineSchedRegistry ShufflerRegistry(
2312 "shuffle", "Shuffle machine instructions alternating directions",
2313 createInstructionShuffler);
2316 //===----------------------------------------------------------------------===//
2317 // GraphWriter support for ScheduleDAGMI.
2318 //===----------------------------------------------------------------------===//
2323 template<> struct GraphTraits<
2324 ScheduleDAGMI*> : public GraphTraits<ScheduleDAG*> {};
2327 struct DOTGraphTraits<ScheduleDAGMI*> : public DefaultDOTGraphTraits {
2329 DOTGraphTraits (bool isSimple=false) : DefaultDOTGraphTraits(isSimple) {}
2331 static std::string getGraphName(const ScheduleDAG *G) {
2332 return G->MF.getName();
2335 static bool renderGraphFromBottomUp() {
2339 static bool isNodeHidden(const SUnit *Node) {
2340 return (Node->NumPreds > 10 || Node->NumSuccs > 10);
2343 static bool hasNodeAddressLabel(const SUnit *Node,
2344 const ScheduleDAG *Graph) {
2348 /// If you want to override the dot attributes printed for a particular
2349 /// edge, override this method.
2350 static std::string getEdgeAttributes(const SUnit *Node,
2352 const ScheduleDAG *Graph) {
2353 if (EI.isArtificialDep())
2354 return "color=cyan,style=dashed";
2356 return "color=blue,style=dashed";
2360 static std::string getNodeLabel(const SUnit *SU, const ScheduleDAG *G) {
2362 raw_string_ostream SS(Str);
2363 SS << "SU(" << SU->NodeNum << ')';
2366 static std::string getNodeDescription(const SUnit *SU, const ScheduleDAG *G) {
2367 return G->getGraphNodeLabel(SU);
2370 static std::string getNodeAttributes(const SUnit *N,
2371 const ScheduleDAG *Graph) {
2372 std::string Str("shape=Mrecord");
2373 const SchedDFSResult *DFS =
2374 static_cast<const ScheduleDAGMI*>(Graph)->getDFSResult();
2376 Str += ",style=filled,fillcolor=\"#";
2377 Str += DOT::getColorString(DFS->getSubtreeID(N));
2386 /// viewGraph - Pop up a ghostview window with the reachable parts of the DAG
2387 /// rendered using 'dot'.
2389 void ScheduleDAGMI::viewGraph(const Twine &Name, const Twine &Title) {
2391 ViewGraph(this, Name, false, Title);
2393 errs() << "ScheduleDAGMI::viewGraph is only available in debug builds on "
2394 << "systems with Graphviz or gv!\n";
2398 /// Out-of-line implementation with no arguments is handy for gdb.
2399 void ScheduleDAGMI::viewGraph() {
2400 viewGraph(getDAGName(), "Scheduling-Units Graph for " + getDAGName());