1 //===- MachineScheduler.cpp - Machine Instruction Scheduler ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // MachineScheduler schedules machine instructions after phi elimination. It
11 // preserves LiveIntervals so it can be invoked before register allocation.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "misched"
17 #include "llvm/CodeGen/MachineScheduler.h"
18 #include "llvm/ADT/OwningPtr.h"
19 #include "llvm/ADT/PriorityQueue.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
22 #include "llvm/CodeGen/MachineDominators.h"
23 #include "llvm/CodeGen/MachineLoopInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/CodeGen/RegisterClassInfo.h"
27 #include "llvm/CodeGen/ScheduleDFS.h"
28 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/GraphWriter.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetInstrInfo.h"
40 cl::opt<bool> ForceTopDown("misched-topdown", cl::Hidden,
41 cl::desc("Force top-down list scheduling"));
42 cl::opt<bool> ForceBottomUp("misched-bottomup", cl::Hidden,
43 cl::desc("Force bottom-up list scheduling"));
47 static cl::opt<bool> ViewMISchedDAGs("view-misched-dags", cl::Hidden,
48 cl::desc("Pop up a window to show MISched dags after they are processed"));
50 static cl::opt<unsigned> MISchedCutoff("misched-cutoff", cl::Hidden,
51 cl::desc("Stop scheduling after N instructions"), cl::init(~0U));
53 static bool ViewMISchedDAGs = false;
56 static cl::opt<bool> EnableCyclicPath("misched-cyclicpath", cl::Hidden,
57 cl::desc("Enable cyclic critical path analysis."), cl::init(false));
59 static cl::opt<bool> EnableLoadCluster("misched-cluster", cl::Hidden,
60 cl::desc("Enable load clustering."), cl::init(true));
62 // Experimental heuristics
63 static cl::opt<bool> EnableMacroFusion("misched-fusion", cl::Hidden,
64 cl::desc("Enable scheduling for macro fusion."), cl::init(true));
66 static cl::opt<bool> VerifyScheduling("verify-misched", cl::Hidden,
67 cl::desc("Verify machine instrs before and after machine scheduling"));
69 // DAG subtrees must have at least this many nodes.
70 static const unsigned MinSubtreeSize = 8;
72 //===----------------------------------------------------------------------===//
73 // Machine Instruction Scheduling Pass and Registry
74 //===----------------------------------------------------------------------===//
76 MachineSchedContext::MachineSchedContext():
77 MF(0), MLI(0), MDT(0), PassConfig(0), AA(0), LIS(0) {
78 RegClassInfo = new RegisterClassInfo();
81 MachineSchedContext::~MachineSchedContext() {
86 /// MachineScheduler runs after coalescing and before register allocation.
87 class MachineScheduler : public MachineSchedContext,
88 public MachineFunctionPass {
92 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
94 virtual void releaseMemory() {}
96 virtual bool runOnMachineFunction(MachineFunction&);
98 virtual void print(raw_ostream &O, const Module* = 0) const;
100 static char ID; // Class identification, replacement for typeinfo
104 char MachineScheduler::ID = 0;
106 char &llvm::MachineSchedulerID = MachineScheduler::ID;
108 INITIALIZE_PASS_BEGIN(MachineScheduler, "misched",
109 "Machine Instruction Scheduler", false, false)
110 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
111 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
112 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
113 INITIALIZE_PASS_END(MachineScheduler, "misched",
114 "Machine Instruction Scheduler", false, false)
116 MachineScheduler::MachineScheduler()
117 : MachineFunctionPass(ID) {
118 initializeMachineSchedulerPass(*PassRegistry::getPassRegistry());
121 void MachineScheduler::getAnalysisUsage(AnalysisUsage &AU) const {
122 AU.setPreservesCFG();
123 AU.addRequiredID(MachineDominatorsID);
124 AU.addRequired<MachineLoopInfo>();
125 AU.addRequired<AliasAnalysis>();
126 AU.addRequired<TargetPassConfig>();
127 AU.addRequired<SlotIndexes>();
128 AU.addPreserved<SlotIndexes>();
129 AU.addRequired<LiveIntervals>();
130 AU.addPreserved<LiveIntervals>();
131 MachineFunctionPass::getAnalysisUsage(AU);
134 MachinePassRegistry MachineSchedRegistry::Registry;
136 /// A dummy default scheduler factory indicates whether the scheduler
137 /// is overridden on the command line.
138 static ScheduleDAGInstrs *useDefaultMachineSched(MachineSchedContext *C) {
142 /// MachineSchedOpt allows command line selection of the scheduler.
143 static cl::opt<MachineSchedRegistry::ScheduleDAGCtor, false,
144 RegisterPassParser<MachineSchedRegistry> >
145 MachineSchedOpt("misched",
146 cl::init(&useDefaultMachineSched), cl::Hidden,
147 cl::desc("Machine instruction scheduler to use"));
149 static MachineSchedRegistry
150 DefaultSchedRegistry("default", "Use the target's default scheduler choice.",
151 useDefaultMachineSched);
153 /// Forward declare the standard machine scheduler. This will be used as the
154 /// default scheduler if the target does not set a default.
155 static ScheduleDAGInstrs *createConvergingSched(MachineSchedContext *C);
158 /// Decrement this iterator until reaching the top or a non-debug instr.
159 static MachineBasicBlock::iterator
160 priorNonDebug(MachineBasicBlock::iterator I, MachineBasicBlock::iterator Beg) {
161 assert(I != Beg && "reached the top of the region, cannot decrement");
163 if (!I->isDebugValue())
169 /// If this iterator is a debug value, increment until reaching the End or a
170 /// non-debug instruction.
171 static MachineBasicBlock::iterator
172 nextIfDebug(MachineBasicBlock::iterator I, MachineBasicBlock::iterator End) {
173 for(; I != End; ++I) {
174 if (!I->isDebugValue())
180 /// Top-level MachineScheduler pass driver.
182 /// Visit blocks in function order. Divide each block into scheduling regions
183 /// and visit them bottom-up. Visiting regions bottom-up is not required, but is
184 /// consistent with the DAG builder, which traverses the interior of the
185 /// scheduling regions bottom-up.
187 /// This design avoids exposing scheduling boundaries to the DAG builder,
188 /// simplifying the DAG builder's support for "special" target instructions.
189 /// At the same time the design allows target schedulers to operate across
190 /// scheduling boundaries, for example to bundle the boudary instructions
191 /// without reordering them. This creates complexity, because the target
192 /// scheduler must update the RegionBegin and RegionEnd positions cached by
193 /// ScheduleDAGInstrs whenever adding or removing instructions. A much simpler
194 /// design would be to split blocks at scheduling boundaries, but LLVM has a
195 /// general bias against block splitting purely for implementation simplicity.
196 bool MachineScheduler::runOnMachineFunction(MachineFunction &mf) {
197 DEBUG(dbgs() << "Before MISsched:\n"; mf.print(dbgs()));
199 // Initialize the context of the pass.
201 MLI = &getAnalysis<MachineLoopInfo>();
202 MDT = &getAnalysis<MachineDominatorTree>();
203 PassConfig = &getAnalysis<TargetPassConfig>();
204 AA = &getAnalysis<AliasAnalysis>();
206 LIS = &getAnalysis<LiveIntervals>();
207 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
209 if (VerifyScheduling) {
211 MF->verify(this, "Before machine scheduling.");
213 RegClassInfo->runOnMachineFunction(*MF);
215 // Select the scheduler, or set the default.
216 MachineSchedRegistry::ScheduleDAGCtor Ctor = MachineSchedOpt;
217 if (Ctor == useDefaultMachineSched) {
218 // Get the default scheduler set by the target.
219 Ctor = MachineSchedRegistry::getDefault();
221 Ctor = createConvergingSched;
222 MachineSchedRegistry::setDefault(Ctor);
225 // Instantiate the selected scheduler.
226 OwningPtr<ScheduleDAGInstrs> Scheduler(Ctor(this));
228 // Visit all machine basic blocks.
230 // TODO: Visit blocks in global postorder or postorder within the bottom-up
231 // loop tree. Then we can optionally compute global RegPressure.
232 for (MachineFunction::iterator MBB = MF->begin(), MBBEnd = MF->end();
233 MBB != MBBEnd; ++MBB) {
235 Scheduler->startBlock(MBB);
237 // Break the block into scheduling regions [I, RegionEnd), and schedule each
238 // region as soon as it is discovered. RegionEnd points the scheduling
239 // boundary at the bottom of the region. The DAG does not include RegionEnd,
240 // but the region does (i.e. the next RegionEnd is above the previous
241 // RegionBegin). If the current block has no terminator then RegionEnd ==
242 // MBB->end() for the bottom region.
244 // The Scheduler may insert instructions during either schedule() or
245 // exitRegion(), even for empty regions. So the local iterators 'I' and
246 // 'RegionEnd' are invalid across these calls.
247 unsigned RemainingInstrs = MBB->size();
248 for(MachineBasicBlock::iterator RegionEnd = MBB->end();
249 RegionEnd != MBB->begin(); RegionEnd = Scheduler->begin()) {
251 // Avoid decrementing RegionEnd for blocks with no terminator.
252 if (RegionEnd != MBB->end()
253 || TII->isSchedulingBoundary(llvm::prior(RegionEnd), MBB, *MF)) {
255 // Count the boundary instruction.
259 // The next region starts above the previous region. Look backward in the
260 // instruction stream until we find the nearest boundary.
261 unsigned NumRegionInstrs = 0;
262 MachineBasicBlock::iterator I = RegionEnd;
263 for(;I != MBB->begin(); --I, --RemainingInstrs, ++NumRegionInstrs) {
264 if (TII->isSchedulingBoundary(llvm::prior(I), MBB, *MF))
267 // Notify the scheduler of the region, even if we may skip scheduling
268 // it. Perhaps it still needs to be bundled.
269 Scheduler->enterRegion(MBB, I, RegionEnd, NumRegionInstrs);
271 // Skip empty scheduling regions (0 or 1 schedulable instructions).
272 if (I == RegionEnd || I == llvm::prior(RegionEnd)) {
273 // Close the current region. Bundle the terminator if needed.
274 // This invalidates 'RegionEnd' and 'I'.
275 Scheduler->exitRegion();
278 DEBUG(dbgs() << "********** MI Scheduling **********\n");
279 DEBUG(dbgs() << MF->getName()
280 << ":BB#" << MBB->getNumber() << " " << MBB->getName()
281 << "\n From: " << *I << " To: ";
282 if (RegionEnd != MBB->end()) dbgs() << *RegionEnd;
283 else dbgs() << "End";
284 dbgs() << " RegionInstrs: " << NumRegionInstrs
285 << " Remaining: " << RemainingInstrs << "\n");
287 // Schedule a region: possibly reorder instructions.
288 // This invalidates 'RegionEnd' and 'I'.
289 Scheduler->schedule();
291 // Close the current region.
292 Scheduler->exitRegion();
294 // Scheduling has invalidated the current iterator 'I'. Ask the
295 // scheduler for the top of it's scheduled region.
296 RegionEnd = Scheduler->begin();
298 assert(RemainingInstrs == 0 && "Instruction count mismatch!");
299 Scheduler->finishBlock();
301 Scheduler->finalizeSchedule();
303 if (VerifyScheduling)
304 MF->verify(this, "After machine scheduling.");
308 void MachineScheduler::print(raw_ostream &O, const Module* m) const {
312 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
313 void ReadyQueue::dump() {
314 dbgs() << Name << ": ";
315 for (unsigned i = 0, e = Queue.size(); i < e; ++i)
316 dbgs() << Queue[i]->NodeNum << " ";
321 //===----------------------------------------------------------------------===//
322 // ScheduleDAGMI - Base class for MachineInstr scheduling with LiveIntervals
324 //===----------------------------------------------------------------------===//
326 ScheduleDAGMI::~ScheduleDAGMI() {
328 DeleteContainerPointers(Mutations);
332 bool ScheduleDAGMI::canAddEdge(SUnit *SuccSU, SUnit *PredSU) {
333 return SuccSU == &ExitSU || !Topo.IsReachable(PredSU, SuccSU);
336 bool ScheduleDAGMI::addEdge(SUnit *SuccSU, const SDep &PredDep) {
337 if (SuccSU != &ExitSU) {
338 // Do not use WillCreateCycle, it assumes SD scheduling.
339 // If Pred is reachable from Succ, then the edge creates a cycle.
340 if (Topo.IsReachable(PredDep.getSUnit(), SuccSU))
342 Topo.AddPred(SuccSU, PredDep.getSUnit());
344 SuccSU->addPred(PredDep, /*Required=*/!PredDep.isArtificial());
345 // Return true regardless of whether a new edge needed to be inserted.
349 /// ReleaseSucc - Decrement the NumPredsLeft count of a successor. When
350 /// NumPredsLeft reaches zero, release the successor node.
352 /// FIXME: Adjust SuccSU height based on MinLatency.
353 void ScheduleDAGMI::releaseSucc(SUnit *SU, SDep *SuccEdge) {
354 SUnit *SuccSU = SuccEdge->getSUnit();
356 if (SuccEdge->isWeak()) {
357 --SuccSU->WeakPredsLeft;
358 if (SuccEdge->isCluster())
359 NextClusterSucc = SuccSU;
363 if (SuccSU->NumPredsLeft == 0) {
364 dbgs() << "*** Scheduling failed! ***\n";
366 dbgs() << " has been released too many times!\n";
370 --SuccSU->NumPredsLeft;
371 if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU)
372 SchedImpl->releaseTopNode(SuccSU);
375 /// releaseSuccessors - Call releaseSucc on each of SU's successors.
376 void ScheduleDAGMI::releaseSuccessors(SUnit *SU) {
377 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
379 releaseSucc(SU, &*I);
383 /// ReleasePred - Decrement the NumSuccsLeft count of a predecessor. When
384 /// NumSuccsLeft reaches zero, release the predecessor node.
386 /// FIXME: Adjust PredSU height based on MinLatency.
387 void ScheduleDAGMI::releasePred(SUnit *SU, SDep *PredEdge) {
388 SUnit *PredSU = PredEdge->getSUnit();
390 if (PredEdge->isWeak()) {
391 --PredSU->WeakSuccsLeft;
392 if (PredEdge->isCluster())
393 NextClusterPred = PredSU;
397 if (PredSU->NumSuccsLeft == 0) {
398 dbgs() << "*** Scheduling failed! ***\n";
400 dbgs() << " has been released too many times!\n";
404 --PredSU->NumSuccsLeft;
405 if (PredSU->NumSuccsLeft == 0 && PredSU != &EntrySU)
406 SchedImpl->releaseBottomNode(PredSU);
409 /// releasePredecessors - Call releasePred on each of SU's predecessors.
410 void ScheduleDAGMI::releasePredecessors(SUnit *SU) {
411 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
413 releasePred(SU, &*I);
417 /// This is normally called from the main scheduler loop but may also be invoked
418 /// by the scheduling strategy to perform additional code motion.
419 void ScheduleDAGMI::moveInstruction(MachineInstr *MI,
420 MachineBasicBlock::iterator InsertPos) {
421 // Advance RegionBegin if the first instruction moves down.
422 if (&*RegionBegin == MI)
425 // Update the instruction stream.
426 BB->splice(InsertPos, BB, MI);
428 // Update LiveIntervals
429 LIS->handleMove(MI, /*UpdateFlags=*/true);
431 // Recede RegionBegin if an instruction moves above the first.
432 if (RegionBegin == InsertPos)
436 bool ScheduleDAGMI::checkSchedLimit() {
438 if (NumInstrsScheduled == MISchedCutoff && MISchedCutoff != ~0U) {
439 CurrentTop = CurrentBottom;
442 ++NumInstrsScheduled;
447 /// enterRegion - Called back from MachineScheduler::runOnMachineFunction after
448 /// crossing a scheduling boundary. [begin, end) includes all instructions in
449 /// the region, including the boundary itself and single-instruction regions
450 /// that don't get scheduled.
451 void ScheduleDAGMI::enterRegion(MachineBasicBlock *bb,
452 MachineBasicBlock::iterator begin,
453 MachineBasicBlock::iterator end,
454 unsigned regioninstrs)
456 ScheduleDAGInstrs::enterRegion(bb, begin, end, regioninstrs);
458 // For convenience remember the end of the liveness region.
460 (RegionEnd == bb->end()) ? RegionEnd : llvm::next(RegionEnd);
463 // Setup the register pressure trackers for the top scheduled top and bottom
464 // scheduled regions.
465 void ScheduleDAGMI::initRegPressure() {
466 TopRPTracker.init(&MF, RegClassInfo, LIS, BB, RegionBegin);
467 BotRPTracker.init(&MF, RegClassInfo, LIS, BB, LiveRegionEnd);
469 // Close the RPTracker to finalize live ins.
470 RPTracker.closeRegion();
472 DEBUG(RPTracker.dump());
474 // Initialize the live ins and live outs.
475 TopRPTracker.addLiveRegs(RPTracker.getPressure().LiveInRegs);
476 BotRPTracker.addLiveRegs(RPTracker.getPressure().LiveOutRegs);
478 // Close one end of the tracker so we can call
479 // getMaxUpward/DownwardPressureDelta before advancing across any
480 // instructions. This converts currently live regs into live ins/outs.
481 TopRPTracker.closeTop();
482 BotRPTracker.closeBottom();
484 BotRPTracker.initLiveThru(RPTracker);
485 if (!BotRPTracker.getLiveThru().empty()) {
486 TopRPTracker.initLiveThru(BotRPTracker.getLiveThru());
487 DEBUG(dbgs() << "Live Thru: ";
488 dumpRegSetPressure(BotRPTracker.getLiveThru(), TRI));
491 // Account for liveness generated by the region boundary.
492 if (LiveRegionEnd != RegionEnd)
493 BotRPTracker.recede();
495 assert(BotRPTracker.getPos() == RegionEnd && "Can't find the region bottom");
497 // Cache the list of excess pressure sets in this region. This will also track
498 // the max pressure in the scheduled code for these sets.
499 RegionCriticalPSets.clear();
500 const std::vector<unsigned> &RegionPressure =
501 RPTracker.getPressure().MaxSetPressure;
502 for (unsigned i = 0, e = RegionPressure.size(); i < e; ++i) {
503 unsigned Limit = RegClassInfo->getRegPressureSetLimit(i);
504 if (RegionPressure[i] > Limit) {
505 DEBUG(dbgs() << TRI->getRegPressureSetName(i)
506 << " Limit " << Limit
507 << " Actual " << RegionPressure[i] << "\n");
508 RegionCriticalPSets.push_back(PressureElement(i, 0));
511 DEBUG(dbgs() << "Excess PSets: ";
512 for (unsigned i = 0, e = RegionCriticalPSets.size(); i != e; ++i)
513 dbgs() << TRI->getRegPressureSetName(
514 RegionCriticalPSets[i].PSetID) << " ";
518 // FIXME: When the pressure tracker deals in pressure differences then we won't
519 // iterate over all RegionCriticalPSets[i].
521 updateScheduledPressure(const std::vector<unsigned> &NewMaxPressure) {
522 for (unsigned i = 0, e = RegionCriticalPSets.size(); i < e; ++i) {
523 unsigned ID = RegionCriticalPSets[i].PSetID;
524 int &MaxUnits = RegionCriticalPSets[i].UnitIncrease;
525 if ((int)NewMaxPressure[ID] > MaxUnits)
526 MaxUnits = NewMaxPressure[ID];
529 for (unsigned i = 0, e = NewMaxPressure.size(); i < e; ++i) {
530 unsigned Limit = RegClassInfo->getRegPressureSetLimit(i);
531 if (NewMaxPressure[i] > Limit ) {
532 dbgs() << " " << TRI->getRegPressureSetName(i) << ": "
533 << NewMaxPressure[i] << " > " << Limit << "\n";
538 /// schedule - Called back from MachineScheduler::runOnMachineFunction
539 /// after setting up the current scheduling region. [RegionBegin, RegionEnd)
540 /// only includes instructions that have DAG nodes, not scheduling boundaries.
542 /// This is a skeletal driver, with all the functionality pushed into helpers,
543 /// so that it can be easilly extended by experimental schedulers. Generally,
544 /// implementing MachineSchedStrategy should be sufficient to implement a new
545 /// scheduling algorithm. However, if a scheduler further subclasses
546 /// ScheduleDAGMI then it will want to override this virtual method in order to
547 /// update any specialized state.
548 void ScheduleDAGMI::schedule() {
549 buildDAGWithRegPressure();
551 Topo.InitDAGTopologicalSorting();
555 SmallVector<SUnit*, 8> TopRoots, BotRoots;
556 findRootsAndBiasEdges(TopRoots, BotRoots);
558 // Initialize the strategy before modifying the DAG.
559 // This may initialize a DFSResult to be used for queue priority.
560 SchedImpl->initialize(this);
562 DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
563 SUnits[su].dumpAll(this));
564 if (ViewMISchedDAGs) viewGraph();
566 // Initialize ready queues now that the DAG and priority data are finalized.
567 initQueues(TopRoots, BotRoots);
569 bool IsTopNode = false;
570 while (SUnit *SU = SchedImpl->pickNode(IsTopNode)) {
571 assert(!SU->isScheduled && "Node already scheduled");
572 if (!checkSchedLimit())
575 scheduleMI(SU, IsTopNode);
577 updateQueues(SU, IsTopNode);
579 assert(CurrentTop == CurrentBottom && "Nonempty unscheduled zone.");
584 unsigned BBNum = begin()->getParent()->getNumber();
585 dbgs() << "*** Final schedule for BB#" << BBNum << " ***\n";
591 /// Build the DAG and setup three register pressure trackers.
592 void ScheduleDAGMI::buildDAGWithRegPressure() {
593 // Initialize the register pressure tracker used by buildSchedGraph.
594 RPTracker.init(&MF, RegClassInfo, LIS, BB, LiveRegionEnd,
595 /*TrackUntiedDefs=*/true);
597 // Account for liveness generate by the region boundary.
598 if (LiveRegionEnd != RegionEnd)
601 // Build the DAG, and compute current register pressure.
602 buildSchedGraph(AA, &RPTracker);
604 // Initialize top/bottom trackers after computing region pressure.
608 /// Apply each ScheduleDAGMutation step in order.
609 void ScheduleDAGMI::postprocessDAG() {
610 for (unsigned i = 0, e = Mutations.size(); i < e; ++i) {
611 Mutations[i]->apply(this);
615 void ScheduleDAGMI::computeDFSResult() {
617 DFSResult = new SchedDFSResult(/*BottomU*/true, MinSubtreeSize);
619 ScheduledTrees.clear();
620 DFSResult->resize(SUnits.size());
621 DFSResult->compute(SUnits);
622 ScheduledTrees.resize(DFSResult->getNumSubtrees());
625 void ScheduleDAGMI::findRootsAndBiasEdges(SmallVectorImpl<SUnit*> &TopRoots,
626 SmallVectorImpl<SUnit*> &BotRoots) {
627 for (std::vector<SUnit>::iterator
628 I = SUnits.begin(), E = SUnits.end(); I != E; ++I) {
630 assert(!SU->isBoundaryNode() && "Boundary node should not be in SUnits");
632 // Order predecessors so DFSResult follows the critical path.
633 SU->biasCriticalPath();
635 // A SUnit is ready to top schedule if it has no predecessors.
636 if (!I->NumPredsLeft)
637 TopRoots.push_back(SU);
638 // A SUnit is ready to bottom schedule if it has no successors.
639 if (!I->NumSuccsLeft)
640 BotRoots.push_back(SU);
642 ExitSU.biasCriticalPath();
645 /// Identify DAG roots and setup scheduler queues.
646 void ScheduleDAGMI::initQueues(ArrayRef<SUnit*> TopRoots,
647 ArrayRef<SUnit*> BotRoots) {
648 NextClusterSucc = NULL;
649 NextClusterPred = NULL;
651 // Release all DAG roots for scheduling, not including EntrySU/ExitSU.
653 // Nodes with unreleased weak edges can still be roots.
654 // Release top roots in forward order.
655 for (SmallVectorImpl<SUnit*>::const_iterator
656 I = TopRoots.begin(), E = TopRoots.end(); I != E; ++I) {
657 SchedImpl->releaseTopNode(*I);
659 // Release bottom roots in reverse order so the higher priority nodes appear
660 // first. This is more natural and slightly more efficient.
661 for (SmallVectorImpl<SUnit*>::const_reverse_iterator
662 I = BotRoots.rbegin(), E = BotRoots.rend(); I != E; ++I) {
663 SchedImpl->releaseBottomNode(*I);
666 releaseSuccessors(&EntrySU);
667 releasePredecessors(&ExitSU);
669 SchedImpl->registerRoots();
671 // Advance past initial DebugValues.
672 assert(TopRPTracker.getPos() == RegionBegin && "bad initial Top tracker");
673 CurrentTop = nextIfDebug(RegionBegin, RegionEnd);
674 TopRPTracker.setPos(CurrentTop);
676 CurrentBottom = RegionEnd;
679 /// Move an instruction and update register pressure.
680 void ScheduleDAGMI::scheduleMI(SUnit *SU, bool IsTopNode) {
681 // Move the instruction to its new location in the instruction stream.
682 MachineInstr *MI = SU->getInstr();
685 assert(SU->isTopReady() && "node still has unscheduled dependencies");
686 if (&*CurrentTop == MI)
687 CurrentTop = nextIfDebug(++CurrentTop, CurrentBottom);
689 moveInstruction(MI, CurrentTop);
690 TopRPTracker.setPos(MI);
693 // Update top scheduled pressure.
694 TopRPTracker.advance();
695 assert(TopRPTracker.getPos() == CurrentTop && "out of sync");
696 updateScheduledPressure(TopRPTracker.getPressure().MaxSetPressure);
699 assert(SU->isBottomReady() && "node still has unscheduled dependencies");
700 MachineBasicBlock::iterator priorII =
701 priorNonDebug(CurrentBottom, CurrentTop);
703 CurrentBottom = priorII;
705 if (&*CurrentTop == MI) {
706 CurrentTop = nextIfDebug(++CurrentTop, priorII);
707 TopRPTracker.setPos(CurrentTop);
709 moveInstruction(MI, CurrentBottom);
712 // Update bottom scheduled pressure.
713 BotRPTracker.recede();
714 assert(BotRPTracker.getPos() == CurrentBottom && "out of sync");
715 updateScheduledPressure(BotRPTracker.getPressure().MaxSetPressure);
719 /// Update scheduler queues after scheduling an instruction.
720 void ScheduleDAGMI::updateQueues(SUnit *SU, bool IsTopNode) {
721 // Release dependent instructions for scheduling.
723 releaseSuccessors(SU);
725 releasePredecessors(SU);
727 SU->isScheduled = true;
730 unsigned SubtreeID = DFSResult->getSubtreeID(SU);
731 if (!ScheduledTrees.test(SubtreeID)) {
732 ScheduledTrees.set(SubtreeID);
733 DFSResult->scheduleTree(SubtreeID);
734 SchedImpl->scheduleTree(SubtreeID);
738 // Notify the scheduling strategy after updating the DAG.
739 SchedImpl->schedNode(SU, IsTopNode);
742 /// Reinsert any remaining debug_values, just like the PostRA scheduler.
743 void ScheduleDAGMI::placeDebugValues() {
744 // If first instruction was a DBG_VALUE then put it back.
746 BB->splice(RegionBegin, BB, FirstDbgValue);
747 RegionBegin = FirstDbgValue;
750 for (std::vector<std::pair<MachineInstr *, MachineInstr *> >::iterator
751 DI = DbgValues.end(), DE = DbgValues.begin(); DI != DE; --DI) {
752 std::pair<MachineInstr *, MachineInstr *> P = *prior(DI);
753 MachineInstr *DbgValue = P.first;
754 MachineBasicBlock::iterator OrigPrevMI = P.second;
755 if (&*RegionBegin == DbgValue)
757 BB->splice(++OrigPrevMI, BB, DbgValue);
758 if (OrigPrevMI == llvm::prior(RegionEnd))
759 RegionEnd = DbgValue;
762 FirstDbgValue = NULL;
765 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
766 void ScheduleDAGMI::dumpSchedule() const {
767 for (MachineBasicBlock::iterator MI = begin(), ME = end(); MI != ME; ++MI) {
768 if (SUnit *SU = getSUnit(&(*MI)))
771 dbgs() << "Missing SUnit\n";
776 //===----------------------------------------------------------------------===//
777 // LoadClusterMutation - DAG post-processing to cluster loads.
778 //===----------------------------------------------------------------------===//
781 /// \brief Post-process the DAG to create cluster edges between neighboring
783 class LoadClusterMutation : public ScheduleDAGMutation {
788 LoadInfo(SUnit *su, unsigned reg, unsigned ofs)
789 : SU(su), BaseReg(reg), Offset(ofs) {}
791 static bool LoadInfoLess(const LoadClusterMutation::LoadInfo &LHS,
792 const LoadClusterMutation::LoadInfo &RHS);
794 const TargetInstrInfo *TII;
795 const TargetRegisterInfo *TRI;
797 LoadClusterMutation(const TargetInstrInfo *tii,
798 const TargetRegisterInfo *tri)
799 : TII(tii), TRI(tri) {}
801 virtual void apply(ScheduleDAGMI *DAG);
803 void clusterNeighboringLoads(ArrayRef<SUnit*> Loads, ScheduleDAGMI *DAG);
807 bool LoadClusterMutation::LoadInfoLess(
808 const LoadClusterMutation::LoadInfo &LHS,
809 const LoadClusterMutation::LoadInfo &RHS) {
810 if (LHS.BaseReg != RHS.BaseReg)
811 return LHS.BaseReg < RHS.BaseReg;
812 return LHS.Offset < RHS.Offset;
815 void LoadClusterMutation::clusterNeighboringLoads(ArrayRef<SUnit*> Loads,
816 ScheduleDAGMI *DAG) {
817 SmallVector<LoadClusterMutation::LoadInfo,32> LoadRecords;
818 for (unsigned Idx = 0, End = Loads.size(); Idx != End; ++Idx) {
819 SUnit *SU = Loads[Idx];
822 if (TII->getLdStBaseRegImmOfs(SU->getInstr(), BaseReg, Offset, TRI))
823 LoadRecords.push_back(LoadInfo(SU, BaseReg, Offset));
825 if (LoadRecords.size() < 2)
827 std::sort(LoadRecords.begin(), LoadRecords.end(), LoadInfoLess);
828 unsigned ClusterLength = 1;
829 for (unsigned Idx = 0, End = LoadRecords.size(); Idx < (End - 1); ++Idx) {
830 if (LoadRecords[Idx].BaseReg != LoadRecords[Idx+1].BaseReg) {
835 SUnit *SUa = LoadRecords[Idx].SU;
836 SUnit *SUb = LoadRecords[Idx+1].SU;
837 if (TII->shouldClusterLoads(SUa->getInstr(), SUb->getInstr(), ClusterLength)
838 && DAG->addEdge(SUb, SDep(SUa, SDep::Cluster))) {
840 DEBUG(dbgs() << "Cluster loads SU(" << SUa->NodeNum << ") - SU("
841 << SUb->NodeNum << ")\n");
842 // Copy successor edges from SUa to SUb. Interleaving computation
843 // dependent on SUa can prevent load combining due to register reuse.
844 // Predecessor edges do not need to be copied from SUb to SUa since nearby
845 // loads should have effectively the same inputs.
846 for (SUnit::const_succ_iterator
847 SI = SUa->Succs.begin(), SE = SUa->Succs.end(); SI != SE; ++SI) {
848 if (SI->getSUnit() == SUb)
850 DEBUG(dbgs() << " Copy Succ SU(" << SI->getSUnit()->NodeNum << ")\n");
851 DAG->addEdge(SI->getSUnit(), SDep(SUb, SDep::Artificial));
860 /// \brief Callback from DAG postProcessing to create cluster edges for loads.
861 void LoadClusterMutation::apply(ScheduleDAGMI *DAG) {
862 // Map DAG NodeNum to store chain ID.
863 DenseMap<unsigned, unsigned> StoreChainIDs;
864 // Map each store chain to a set of dependent loads.
865 SmallVector<SmallVector<SUnit*,4>, 32> StoreChainDependents;
866 for (unsigned Idx = 0, End = DAG->SUnits.size(); Idx != End; ++Idx) {
867 SUnit *SU = &DAG->SUnits[Idx];
868 if (!SU->getInstr()->mayLoad())
870 unsigned ChainPredID = DAG->SUnits.size();
871 for (SUnit::const_pred_iterator
872 PI = SU->Preds.begin(), PE = SU->Preds.end(); PI != PE; ++PI) {
874 ChainPredID = PI->getSUnit()->NodeNum;
878 // Check if this chain-like pred has been seen
879 // before. ChainPredID==MaxNodeID for loads at the top of the schedule.
880 unsigned NumChains = StoreChainDependents.size();
881 std::pair<DenseMap<unsigned, unsigned>::iterator, bool> Result =
882 StoreChainIDs.insert(std::make_pair(ChainPredID, NumChains));
884 StoreChainDependents.resize(NumChains + 1);
885 StoreChainDependents[Result.first->second].push_back(SU);
887 // Iterate over the store chains.
888 for (unsigned Idx = 0, End = StoreChainDependents.size(); Idx != End; ++Idx)
889 clusterNeighboringLoads(StoreChainDependents[Idx], DAG);
892 //===----------------------------------------------------------------------===//
893 // MacroFusion - DAG post-processing to encourage fusion of macro ops.
894 //===----------------------------------------------------------------------===//
897 /// \brief Post-process the DAG to create cluster edges between instructions
898 /// that may be fused by the processor into a single operation.
899 class MacroFusion : public ScheduleDAGMutation {
900 const TargetInstrInfo *TII;
902 MacroFusion(const TargetInstrInfo *tii): TII(tii) {}
904 virtual void apply(ScheduleDAGMI *DAG);
908 /// \brief Callback from DAG postProcessing to create cluster edges to encourage
909 /// fused operations.
910 void MacroFusion::apply(ScheduleDAGMI *DAG) {
911 // For now, assume targets can only fuse with the branch.
912 MachineInstr *Branch = DAG->ExitSU.getInstr();
916 for (unsigned Idx = DAG->SUnits.size(); Idx > 0;) {
917 SUnit *SU = &DAG->SUnits[--Idx];
918 if (!TII->shouldScheduleAdjacent(SU->getInstr(), Branch))
921 // Create a single weak edge from SU to ExitSU. The only effect is to cause
922 // bottom-up scheduling to heavily prioritize the clustered SU. There is no
923 // need to copy predecessor edges from ExitSU to SU, since top-down
924 // scheduling cannot prioritize ExitSU anyway. To defer top-down scheduling
925 // of SU, we could create an artificial edge from the deepest root, but it
926 // hasn't been needed yet.
927 bool Success = DAG->addEdge(&DAG->ExitSU, SDep(SU, SDep::Cluster));
929 assert(Success && "No DAG nodes should be reachable from ExitSU");
931 DEBUG(dbgs() << "Macro Fuse SU(" << SU->NodeNum << ")\n");
936 //===----------------------------------------------------------------------===//
937 // CopyConstrain - DAG post-processing to encourage copy elimination.
938 //===----------------------------------------------------------------------===//
941 /// \brief Post-process the DAG to create weak edges from all uses of a copy to
942 /// the one use that defines the copy's source vreg, most likely an induction
943 /// variable increment.
944 class CopyConstrain : public ScheduleDAGMutation {
946 SlotIndex RegionBeginIdx;
947 // RegionEndIdx is the slot index of the last non-debug instruction in the
948 // scheduling region. So we may have RegionBeginIdx == RegionEndIdx.
949 SlotIndex RegionEndIdx;
951 CopyConstrain(const TargetInstrInfo *, const TargetRegisterInfo *) {}
953 virtual void apply(ScheduleDAGMI *DAG);
956 void constrainLocalCopy(SUnit *CopySU, ScheduleDAGMI *DAG);
960 /// constrainLocalCopy handles two possibilities:
965 /// I3: dst = src (copy)
966 /// (create pred->succ edges I0->I1, I2->I1)
969 /// I0: dst = src (copy)
973 /// (create pred->succ edges I1->I2, I3->I2)
975 /// Although the MachineScheduler is currently constrained to single blocks,
976 /// this algorithm should handle extended blocks. An EBB is a set of
977 /// contiguously numbered blocks such that the previous block in the EBB is
978 /// always the single predecessor.
979 void CopyConstrain::constrainLocalCopy(SUnit *CopySU, ScheduleDAGMI *DAG) {
980 LiveIntervals *LIS = DAG->getLIS();
981 MachineInstr *Copy = CopySU->getInstr();
983 // Check for pure vreg copies.
984 unsigned SrcReg = Copy->getOperand(1).getReg();
985 if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
988 unsigned DstReg = Copy->getOperand(0).getReg();
989 if (!TargetRegisterInfo::isVirtualRegister(DstReg))
992 // Check if either the dest or source is local. If it's live across a back
993 // edge, it's not local. Note that if both vregs are live across the back
994 // edge, we cannot successfully contrain the copy without cyclic scheduling.
995 unsigned LocalReg = DstReg;
996 unsigned GlobalReg = SrcReg;
997 LiveInterval *LocalLI = &LIS->getInterval(LocalReg);
998 if (!LocalLI->isLocal(RegionBeginIdx, RegionEndIdx)) {
1001 LocalLI = &LIS->getInterval(LocalReg);
1002 if (!LocalLI->isLocal(RegionBeginIdx, RegionEndIdx))
1005 LiveInterval *GlobalLI = &LIS->getInterval(GlobalReg);
1007 // Find the global segment after the start of the local LI.
1008 LiveInterval::iterator GlobalSegment = GlobalLI->find(LocalLI->beginIndex());
1009 // If GlobalLI does not overlap LocalLI->start, then a copy directly feeds a
1010 // local live range. We could create edges from other global uses to the local
1011 // start, but the coalescer should have already eliminated these cases, so
1012 // don't bother dealing with it.
1013 if (GlobalSegment == GlobalLI->end())
1016 // If GlobalSegment is killed at the LocalLI->start, the call to find()
1017 // returned the next global segment. But if GlobalSegment overlaps with
1018 // LocalLI->start, then advance to the next segement. If a hole in GlobalLI
1019 // exists in LocalLI's vicinity, GlobalSegment will be the end of the hole.
1020 if (GlobalSegment->contains(LocalLI->beginIndex()))
1023 if (GlobalSegment == GlobalLI->end())
1026 // Check if GlobalLI contains a hole in the vicinity of LocalLI.
1027 if (GlobalSegment != GlobalLI->begin()) {
1028 // Two address defs have no hole.
1029 if (SlotIndex::isSameInstr(llvm::prior(GlobalSegment)->end,
1030 GlobalSegment->start)) {
1033 // If the prior global segment may be defined by the same two-address
1034 // instruction that also defines LocalLI, then can't make a hole here.
1035 if (SlotIndex::isSameInstr(llvm::prior(GlobalSegment)->start,
1036 LocalLI->beginIndex())) {
1039 // If GlobalLI has a prior segment, it must be live into the EBB. Otherwise
1040 // it would be a disconnected component in the live range.
1041 assert(llvm::prior(GlobalSegment)->start < LocalLI->beginIndex() &&
1042 "Disconnected LRG within the scheduling region.");
1044 MachineInstr *GlobalDef = LIS->getInstructionFromIndex(GlobalSegment->start);
1048 SUnit *GlobalSU = DAG->getSUnit(GlobalDef);
1052 // GlobalDef is the bottom of the GlobalLI hole. Open the hole by
1053 // constraining the uses of the last local def to precede GlobalDef.
1054 SmallVector<SUnit*,8> LocalUses;
1055 const VNInfo *LastLocalVN = LocalLI->getVNInfoBefore(LocalLI->endIndex());
1056 MachineInstr *LastLocalDef = LIS->getInstructionFromIndex(LastLocalVN->def);
1057 SUnit *LastLocalSU = DAG->getSUnit(LastLocalDef);
1058 for (SUnit::const_succ_iterator
1059 I = LastLocalSU->Succs.begin(), E = LastLocalSU->Succs.end();
1061 if (I->getKind() != SDep::Data || I->getReg() != LocalReg)
1063 if (I->getSUnit() == GlobalSU)
1065 if (!DAG->canAddEdge(GlobalSU, I->getSUnit()))
1067 LocalUses.push_back(I->getSUnit());
1069 // Open the top of the GlobalLI hole by constraining any earlier global uses
1070 // to precede the start of LocalLI.
1071 SmallVector<SUnit*,8> GlobalUses;
1072 MachineInstr *FirstLocalDef =
1073 LIS->getInstructionFromIndex(LocalLI->beginIndex());
1074 SUnit *FirstLocalSU = DAG->getSUnit(FirstLocalDef);
1075 for (SUnit::const_pred_iterator
1076 I = GlobalSU->Preds.begin(), E = GlobalSU->Preds.end(); I != E; ++I) {
1077 if (I->getKind() != SDep::Anti || I->getReg() != GlobalReg)
1079 if (I->getSUnit() == FirstLocalSU)
1081 if (!DAG->canAddEdge(FirstLocalSU, I->getSUnit()))
1083 GlobalUses.push_back(I->getSUnit());
1085 DEBUG(dbgs() << "Constraining copy SU(" << CopySU->NodeNum << ")\n");
1086 // Add the weak edges.
1087 for (SmallVectorImpl<SUnit*>::const_iterator
1088 I = LocalUses.begin(), E = LocalUses.end(); I != E; ++I) {
1089 DEBUG(dbgs() << " Local use SU(" << (*I)->NodeNum << ") -> SU("
1090 << GlobalSU->NodeNum << ")\n");
1091 DAG->addEdge(GlobalSU, SDep(*I, SDep::Weak));
1093 for (SmallVectorImpl<SUnit*>::const_iterator
1094 I = GlobalUses.begin(), E = GlobalUses.end(); I != E; ++I) {
1095 DEBUG(dbgs() << " Global use SU(" << (*I)->NodeNum << ") -> SU("
1096 << FirstLocalSU->NodeNum << ")\n");
1097 DAG->addEdge(FirstLocalSU, SDep(*I, SDep::Weak));
1101 /// \brief Callback from DAG postProcessing to create weak edges to encourage
1102 /// copy elimination.
1103 void CopyConstrain::apply(ScheduleDAGMI *DAG) {
1104 MachineBasicBlock::iterator FirstPos = nextIfDebug(DAG->begin(), DAG->end());
1105 if (FirstPos == DAG->end())
1107 RegionBeginIdx = DAG->getLIS()->getInstructionIndex(&*FirstPos);
1108 RegionEndIdx = DAG->getLIS()->getInstructionIndex(
1109 &*priorNonDebug(DAG->end(), DAG->begin()));
1111 for (unsigned Idx = 0, End = DAG->SUnits.size(); Idx != End; ++Idx) {
1112 SUnit *SU = &DAG->SUnits[Idx];
1113 if (!SU->getInstr()->isCopy())
1116 constrainLocalCopy(SU, DAG);
1120 //===----------------------------------------------------------------------===//
1121 // ConvergingScheduler - Implementation of the generic MachineSchedStrategy.
1122 //===----------------------------------------------------------------------===//
1125 /// ConvergingScheduler shrinks the unscheduled zone using heuristics to balance
1127 class ConvergingScheduler : public MachineSchedStrategy {
1129 /// Represent the type of SchedCandidate found within a single queue.
1130 /// pickNodeBidirectional depends on these listed by decreasing priority.
1132 NoCand, PhysRegCopy, RegExcess, RegCritical, Cluster, Weak, RegMax,
1133 ResourceReduce, ResourceDemand, BotHeightReduce, BotPathReduce,
1134 TopDepthReduce, TopPathReduce, NextDefUse, NodeOrder};
1137 static const char *getReasonStr(ConvergingScheduler::CandReason Reason);
1140 /// Policy for scheduling the next instruction in the candidate's zone.
1143 unsigned ReduceResIdx;
1144 unsigned DemandResIdx;
1146 CandPolicy(): ReduceLatency(false), ReduceResIdx(0), DemandResIdx(0) {}
1149 /// Status of an instruction's critical resource consumption.
1150 struct SchedResourceDelta {
1151 // Count critical resources in the scheduled region required by SU.
1152 unsigned CritResources;
1154 // Count critical resources from another region consumed by SU.
1155 unsigned DemandedResources;
1157 SchedResourceDelta(): CritResources(0), DemandedResources(0) {}
1159 bool operator==(const SchedResourceDelta &RHS) const {
1160 return CritResources == RHS.CritResources
1161 && DemandedResources == RHS.DemandedResources;
1163 bool operator!=(const SchedResourceDelta &RHS) const {
1164 return !operator==(RHS);
1168 /// Store the state used by ConvergingScheduler heuristics, required for the
1169 /// lifetime of one invocation of pickNode().
1170 struct SchedCandidate {
1173 // The best SUnit candidate.
1176 // The reason for this candidate.
1179 // Set of reasons that apply to multiple candidates.
1180 uint32_t RepeatReasonSet;
1182 // Register pressure values for the best candidate.
1183 RegPressureDelta RPDelta;
1185 // Critical resource consumption of the best candidate.
1186 SchedResourceDelta ResDelta;
1188 SchedCandidate(const CandPolicy &policy)
1189 : Policy(policy), SU(NULL), Reason(NoCand), RepeatReasonSet(0) {}
1191 bool isValid() const { return SU; }
1193 // Copy the status of another candidate without changing policy.
1194 void setBest(SchedCandidate &Best) {
1195 assert(Best.Reason != NoCand && "uninitialized Sched candidate");
1197 Reason = Best.Reason;
1198 RPDelta = Best.RPDelta;
1199 ResDelta = Best.ResDelta;
1202 bool isRepeat(CandReason R) { return RepeatReasonSet & (1 << R); }
1203 void setRepeat(CandReason R) { RepeatReasonSet |= (1 << R); }
1205 void initResourceDelta(const ScheduleDAGMI *DAG,
1206 const TargetSchedModel *SchedModel);
1209 /// Summarize the unscheduled region.
1210 struct SchedRemainder {
1211 // Critical path through the DAG in expected latency.
1212 unsigned CriticalPath;
1213 unsigned CyclicCritPath;
1215 // Scaled count of micro-ops left to schedule.
1216 unsigned RemIssueCount;
1218 bool IsAcyclicLatencyLimited;
1220 // Unscheduled resources
1221 SmallVector<unsigned, 16> RemainingCounts;
1227 IsAcyclicLatencyLimited = false;
1228 RemainingCounts.clear();
1231 SchedRemainder() { reset(); }
1233 void init(ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel);
1236 /// Each Scheduling boundary is associated with ready queues. It tracks the
1237 /// current cycle in the direction of movement, and maintains the state
1238 /// of "hazards" and other interlocks at the current cycle.
1239 struct SchedBoundary {
1241 const TargetSchedModel *SchedModel;
1242 SchedRemainder *Rem;
1244 ReadyQueue Available;
1248 // For heuristics, keep a list of the nodes that immediately depend on the
1249 // most recently scheduled node.
1250 SmallPtrSet<const SUnit*, 8> NextSUs;
1252 ScheduleHazardRecognizer *HazardRec;
1254 /// Number of cycles it takes to issue the instructions scheduled in this
1255 /// zone. It is defined as: scheduled-micro-ops / issue-width + stalls.
1256 /// See getStalls().
1259 /// Micro-ops issued in the current cycle
1262 /// MinReadyCycle - Cycle of the soonest available instruction.
1263 unsigned MinReadyCycle;
1265 // The expected latency of the critical path in this scheduled zone.
1266 unsigned ExpectedLatency;
1268 // The latency of dependence chains leading into this zone.
1269 // For each node scheduled bottom-up: DLat = max DLat, N.Depth.
1270 // For each cycle scheduled: DLat -= 1.
1271 unsigned DependentLatency;
1273 /// Count the scheduled (issued) micro-ops that can be retired by
1274 /// time=CurrCycle assuming the first scheduled instr is retired at time=0.
1275 unsigned RetiredMOps;
1277 // Count scheduled resources that have been executed. Resources are
1278 // considered executed if they become ready in the time that it takes to
1279 // saturate any resource including the one in question. Counts are scaled
1280 // for direct comparison with other resources. Counts can be compared with
1281 // MOps * getMicroOpFactor and Latency * getLatencyFactor.
1282 SmallVector<unsigned, 16> ExecutedResCounts;
1284 /// Cache the max count for a single resource.
1285 unsigned MaxExecutedResCount;
1287 // Cache the critical resources ID in this scheduled zone.
1288 unsigned ZoneCritResIdx;
1290 // Is the scheduled region resource limited vs. latency limited.
1291 bool IsResourceLimited;
1294 // Remember the greatest operand latency as an upper bound on the number of
1295 // times we should retry the pending queue because of a hazard.
1296 unsigned MaxObservedLatency;
1300 // A new HazardRec is created for each DAG and owned by SchedBoundary.
1305 CheckPending = false;
1310 MinReadyCycle = UINT_MAX;
1311 ExpectedLatency = 0;
1312 DependentLatency = 0;
1314 MaxExecutedResCount = 0;
1316 IsResourceLimited = false;
1318 MaxObservedLatency = 0;
1320 // Reserve a zero-count for invalid CritResIdx.
1321 ExecutedResCounts.resize(1);
1322 assert(!ExecutedResCounts[0] && "nonzero count for bad resource");
1325 /// Pending queues extend the ready queues with the same ID and the
1326 /// PendingFlag set.
1327 SchedBoundary(unsigned ID, const Twine &Name):
1328 DAG(0), SchedModel(0), Rem(0), Available(ID, Name+".A"),
1329 Pending(ID << ConvergingScheduler::LogMaxQID, Name+".P"),
1334 ~SchedBoundary() { delete HazardRec; }
1336 void init(ScheduleDAGMI *dag, const TargetSchedModel *smodel,
1337 SchedRemainder *rem);
1339 bool isTop() const {
1340 return Available.getID() == ConvergingScheduler::TopQID;
1344 const char *getResourceName(unsigned PIdx) {
1347 return SchedModel->getProcResource(PIdx)->Name;
1351 /// Get the number of latency cycles "covered" by the scheduled
1352 /// instructions. This is the larger of the critical path within the zone
1353 /// and the number of cycles required to issue the instructions.
1354 unsigned getScheduledLatency() const {
1355 return std::max(ExpectedLatency, CurrCycle);
1358 unsigned getUnscheduledLatency(SUnit *SU) const {
1359 return isTop() ? SU->getHeight() : SU->getDepth();
1362 unsigned getResourceCount(unsigned ResIdx) const {
1363 return ExecutedResCounts[ResIdx];
1366 /// Get the scaled count of scheduled micro-ops and resources, including
1367 /// executed resources.
1368 unsigned getCriticalCount() const {
1369 if (!ZoneCritResIdx)
1370 return RetiredMOps * SchedModel->getMicroOpFactor();
1371 return getResourceCount(ZoneCritResIdx);
1374 /// Get a scaled count for the minimum execution time of the scheduled
1375 /// micro-ops that are ready to execute by getExecutedCount. Notice the
1377 unsigned getExecutedCount() const {
1378 return std::max(CurrCycle * SchedModel->getLatencyFactor(),
1379 MaxExecutedResCount);
1382 bool checkHazard(SUnit *SU);
1384 unsigned findMaxLatency(ArrayRef<SUnit*> ReadySUs);
1386 unsigned getOtherResourceCount(unsigned &OtherCritIdx);
1388 void setPolicy(CandPolicy &Policy, SchedBoundary &OtherZone);
1390 void releaseNode(SUnit *SU, unsigned ReadyCycle);
1392 void bumpCycle(unsigned NextCycle);
1394 void incExecutedResources(unsigned PIdx, unsigned Count);
1396 unsigned countResource(unsigned PIdx, unsigned Cycles, unsigned ReadyCycle);
1398 void bumpNode(SUnit *SU);
1400 void releasePending();
1402 void removeReady(SUnit *SU);
1404 SUnit *pickOnlyChoice();
1407 void dumpScheduledState();
1413 const TargetSchedModel *SchedModel;
1414 const TargetRegisterInfo *TRI;
1416 // State of the top and bottom scheduled instruction boundaries.
1422 /// SUnit::NodeQueueId: 0 (none), 1 (top), 2 (bot), 3 (both)
1429 ConvergingScheduler():
1430 DAG(0), SchedModel(0), TRI(0), Top(TopQID, "TopQ"), Bot(BotQID, "BotQ") {}
1432 virtual void initialize(ScheduleDAGMI *dag);
1434 virtual SUnit *pickNode(bool &IsTopNode);
1436 virtual void schedNode(SUnit *SU, bool IsTopNode);
1438 virtual void releaseTopNode(SUnit *SU);
1440 virtual void releaseBottomNode(SUnit *SU);
1442 virtual void registerRoots();
1445 void checkAcyclicLatency();
1447 void tryCandidate(SchedCandidate &Cand,
1448 SchedCandidate &TryCand,
1449 SchedBoundary &Zone,
1450 const RegPressureTracker &RPTracker,
1451 RegPressureTracker &TempTracker);
1453 SUnit *pickNodeBidirectional(bool &IsTopNode);
1455 void pickNodeFromQueue(SchedBoundary &Zone,
1456 const RegPressureTracker &RPTracker,
1457 SchedCandidate &Candidate);
1459 void reschedulePhysRegCopies(SUnit *SU, bool isTop);
1462 void traceCandidate(const SchedCandidate &Cand);
1467 void ConvergingScheduler::SchedRemainder::
1468 init(ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel) {
1470 if (!SchedModel->hasInstrSchedModel())
1472 RemainingCounts.resize(SchedModel->getNumProcResourceKinds());
1473 for (std::vector<SUnit>::iterator
1474 I = DAG->SUnits.begin(), E = DAG->SUnits.end(); I != E; ++I) {
1475 const MCSchedClassDesc *SC = DAG->getSchedClass(&*I);
1476 RemIssueCount += SchedModel->getNumMicroOps(I->getInstr(), SC)
1477 * SchedModel->getMicroOpFactor();
1478 for (TargetSchedModel::ProcResIter
1479 PI = SchedModel->getWriteProcResBegin(SC),
1480 PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) {
1481 unsigned PIdx = PI->ProcResourceIdx;
1482 unsigned Factor = SchedModel->getResourceFactor(PIdx);
1483 RemainingCounts[PIdx] += (Factor * PI->Cycles);
1488 void ConvergingScheduler::SchedBoundary::
1489 init(ScheduleDAGMI *dag, const TargetSchedModel *smodel, SchedRemainder *rem) {
1492 SchedModel = smodel;
1494 if (SchedModel->hasInstrSchedModel())
1495 ExecutedResCounts.resize(SchedModel->getNumProcResourceKinds());
1498 void ConvergingScheduler::initialize(ScheduleDAGMI *dag) {
1500 SchedModel = DAG->getSchedModel();
1503 Rem.init(DAG, SchedModel);
1504 Top.init(DAG, SchedModel, &Rem);
1505 Bot.init(DAG, SchedModel, &Rem);
1507 // Initialize resource counts.
1509 // Initialize the HazardRecognizers. If itineraries don't exist, are empty, or
1510 // are disabled, then these HazardRecs will be disabled.
1511 const InstrItineraryData *Itin = SchedModel->getInstrItineraries();
1512 const TargetMachine &TM = DAG->MF.getTarget();
1513 Top.HazardRec = TM.getInstrInfo()->CreateTargetMIHazardRecognizer(Itin, DAG);
1514 Bot.HazardRec = TM.getInstrInfo()->CreateTargetMIHazardRecognizer(Itin, DAG);
1516 assert((!ForceTopDown || !ForceBottomUp) &&
1517 "-misched-topdown incompatible with -misched-bottomup");
1520 void ConvergingScheduler::releaseTopNode(SUnit *SU) {
1521 if (SU->isScheduled)
1524 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
1528 unsigned PredReadyCycle = I->getSUnit()->TopReadyCycle;
1529 unsigned Latency = I->getLatency();
1531 Top.MaxObservedLatency = std::max(Latency, Top.MaxObservedLatency);
1533 if (SU->TopReadyCycle < PredReadyCycle + Latency)
1534 SU->TopReadyCycle = PredReadyCycle + Latency;
1536 Top.releaseNode(SU, SU->TopReadyCycle);
1539 void ConvergingScheduler::releaseBottomNode(SUnit *SU) {
1540 if (SU->isScheduled)
1543 assert(SU->getInstr() && "Scheduled SUnit must have instr");
1545 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
1549 unsigned SuccReadyCycle = I->getSUnit()->BotReadyCycle;
1550 unsigned Latency = I->getLatency();
1552 Bot.MaxObservedLatency = std::max(Latency, Bot.MaxObservedLatency);
1554 if (SU->BotReadyCycle < SuccReadyCycle + Latency)
1555 SU->BotReadyCycle = SuccReadyCycle + Latency;
1557 Bot.releaseNode(SU, SU->BotReadyCycle);
1560 void ConvergingScheduler::checkAcyclicLatency() {
1561 if (Rem.CyclicCritPath == 0 || Rem.CyclicCritPath >= Rem.CriticalPath)
1564 unsigned BufferLimit =
1565 SchedModel->getMicroOpBufferSize() * SchedModel->getMicroOpFactor();
1566 unsigned LatencyLag = Rem.CriticalPath - Rem.CyclicCritPath;
1567 Rem.IsAcyclicLatencyLimited =
1568 (LatencyLag * SchedModel->getLatencyFactor()) > BufferLimit;
1570 DEBUG(dbgs() << "BufferLimit " << BufferLimit << "u / "
1571 << Rem.RemIssueCount << "u = "
1572 << (BufferLimit + Rem.RemIssueCount) / Rem.RemIssueCount << " iters. "
1573 << "Latency = " << LatencyLag << "c = "
1574 << LatencyLag * SchedModel->getLatencyFactor() << "u\n";
1575 if (Rem.IsAcyclicLatencyLimited)
1576 dbgs() << " ACYCLIC LATENCY LIMIT\n");
1579 void ConvergingScheduler::registerRoots() {
1580 Rem.CriticalPath = DAG->ExitSU.getDepth();
1582 if (EnableCyclicPath) {
1583 Rem.CyclicCritPath = DAG->computeCyclicCriticalPath();
1584 checkAcyclicLatency();
1586 // Some roots may not feed into ExitSU. Check all of them in case.
1587 for (std::vector<SUnit*>::const_iterator
1588 I = Bot.Available.begin(), E = Bot.Available.end(); I != E; ++I) {
1589 if ((*I)->getDepth() > Rem.CriticalPath)
1590 Rem.CriticalPath = (*I)->getDepth();
1592 DEBUG(dbgs() << "Critical Path: " << Rem.CriticalPath << '\n');
1595 /// Does this SU have a hazard within the current instruction group.
1597 /// The scheduler supports two modes of hazard recognition. The first is the
1598 /// ScheduleHazardRecognizer API. It is a fully general hazard recognizer that
1599 /// supports highly complicated in-order reservation tables
1600 /// (ScoreboardHazardRecognizer) and arbitraty target-specific logic.
1602 /// The second is a streamlined mechanism that checks for hazards based on
1603 /// simple counters that the scheduler itself maintains. It explicitly checks
1604 /// for instruction dispatch limitations, including the number of micro-ops that
1605 /// can dispatch per cycle.
1607 /// TODO: Also check whether the SU must start a new group.
1608 bool ConvergingScheduler::SchedBoundary::checkHazard(SUnit *SU) {
1609 if (HazardRec->isEnabled())
1610 return HazardRec->getHazardType(SU) != ScheduleHazardRecognizer::NoHazard;
1612 unsigned uops = SchedModel->getNumMicroOps(SU->getInstr());
1613 if ((CurrMOps > 0) && (CurrMOps + uops > SchedModel->getIssueWidth())) {
1614 DEBUG(dbgs() << " SU(" << SU->NodeNum << ") uops="
1615 << SchedModel->getNumMicroOps(SU->getInstr()) << '\n');
1621 // Find the unscheduled node in ReadySUs with the highest latency.
1622 unsigned ConvergingScheduler::SchedBoundary::
1623 findMaxLatency(ArrayRef<SUnit*> ReadySUs) {
1625 unsigned RemLatency = 0;
1626 for (ArrayRef<SUnit*>::iterator I = ReadySUs.begin(), E = ReadySUs.end();
1628 unsigned L = getUnscheduledLatency(*I);
1629 if (L > RemLatency) {
1635 DEBUG(dbgs() << Available.getName() << " RemLatency SU("
1636 << LateSU->NodeNum << ") " << RemLatency << "c\n");
1641 // Count resources in this zone and the remaining unscheduled
1642 // instruction. Return the max count, scaled. Set OtherCritIdx to the critical
1643 // resource index, or zero if the zone is issue limited.
1644 unsigned ConvergingScheduler::SchedBoundary::
1645 getOtherResourceCount(unsigned &OtherCritIdx) {
1647 if (!SchedModel->hasInstrSchedModel())
1650 unsigned OtherCritCount = Rem->RemIssueCount
1651 + (RetiredMOps * SchedModel->getMicroOpFactor());
1652 DEBUG(dbgs() << " " << Available.getName() << " + Remain MOps: "
1653 << OtherCritCount / SchedModel->getMicroOpFactor() << '\n');
1654 for (unsigned PIdx = 1, PEnd = SchedModel->getNumProcResourceKinds();
1655 PIdx != PEnd; ++PIdx) {
1656 unsigned OtherCount = getResourceCount(PIdx) + Rem->RemainingCounts[PIdx];
1657 if (OtherCount > OtherCritCount) {
1658 OtherCritCount = OtherCount;
1659 OtherCritIdx = PIdx;
1663 DEBUG(dbgs() << " " << Available.getName() << " + Remain CritRes: "
1664 << OtherCritCount / SchedModel->getResourceFactor(OtherCritIdx)
1665 << " " << getResourceName(OtherCritIdx) << "\n");
1667 return OtherCritCount;
1670 /// Set the CandPolicy for this zone given the current resources and latencies
1671 /// inside and outside the zone.
1672 void ConvergingScheduler::SchedBoundary::setPolicy(CandPolicy &Policy,
1673 SchedBoundary &OtherZone) {
1674 // Now that potential stalls have been considered, apply preemptive heuristics
1675 // based on the the total latency and resources inside and outside this
1678 // Compute remaining latency. We need this both to determine whether the
1679 // overall schedule has become latency-limited and whether the instructions
1680 // outside this zone are resource or latency limited.
1682 // The "dependent" latency is updated incrementally during scheduling as the
1683 // max height/depth of scheduled nodes minus the cycles since it was
1685 // DLat = max (N.depth - (CurrCycle - N.ReadyCycle) for N in Zone
1687 // The "independent" latency is the max ready queue depth:
1688 // ILat = max N.depth for N in Available|Pending
1690 // RemainingLatency is the greater of independent and dependent latency.
1691 unsigned RemLatency = DependentLatency;
1692 RemLatency = std::max(RemLatency, findMaxLatency(Available.elements()));
1693 RemLatency = std::max(RemLatency, findMaxLatency(Pending.elements()));
1695 // Compute the critical resource outside the zone.
1696 unsigned OtherCritIdx;
1697 unsigned OtherCount = OtherZone.getOtherResourceCount(OtherCritIdx);
1699 bool OtherResLimited = false;
1700 if (SchedModel->hasInstrSchedModel()) {
1701 unsigned LFactor = SchedModel->getLatencyFactor();
1702 OtherResLimited = (int)(OtherCount - (RemLatency * LFactor)) > (int)LFactor;
1704 if (!OtherResLimited && (RemLatency + CurrCycle > Rem->CriticalPath)) {
1705 Policy.ReduceLatency |= true;
1706 DEBUG(dbgs() << " " << Available.getName() << " RemainingLatency "
1707 << RemLatency << " + " << CurrCycle << "c > CritPath "
1708 << Rem->CriticalPath << "\n");
1710 // If the same resource is limiting inside and outside the zone, do nothing.
1711 if (ZoneCritResIdx == OtherCritIdx)
1715 if (IsResourceLimited) {
1716 dbgs() << " " << Available.getName() << " ResourceLimited: "
1717 << getResourceName(ZoneCritResIdx) << "\n";
1719 if (OtherResLimited)
1720 dbgs() << " RemainingLimit: " << getResourceName(OtherCritIdx) << "\n";
1721 if (!IsResourceLimited && !OtherResLimited)
1722 dbgs() << " Latency limited both directions.\n");
1724 if (IsResourceLimited && !Policy.ReduceResIdx)
1725 Policy.ReduceResIdx = ZoneCritResIdx;
1727 if (OtherResLimited)
1728 Policy.DemandResIdx = OtherCritIdx;
1731 void ConvergingScheduler::SchedBoundary::releaseNode(SUnit *SU,
1732 unsigned ReadyCycle) {
1733 if (ReadyCycle < MinReadyCycle)
1734 MinReadyCycle = ReadyCycle;
1736 // Check for interlocks first. For the purpose of other heuristics, an
1737 // instruction that cannot issue appears as if it's not in the ReadyQueue.
1738 bool IsBuffered = SchedModel->getMicroOpBufferSize() != 0;
1739 if ((!IsBuffered && ReadyCycle > CurrCycle) || checkHazard(SU))
1744 // Record this node as an immediate dependent of the scheduled node.
1748 /// Move the boundary of scheduled code by one cycle.
1749 void ConvergingScheduler::SchedBoundary::bumpCycle(unsigned NextCycle) {
1750 if (SchedModel->getMicroOpBufferSize() == 0) {
1751 assert(MinReadyCycle < UINT_MAX && "MinReadyCycle uninitialized");
1752 if (MinReadyCycle > NextCycle)
1753 NextCycle = MinReadyCycle;
1755 // Update the current micro-ops, which will issue in the next cycle.
1756 unsigned DecMOps = SchedModel->getIssueWidth() * (NextCycle - CurrCycle);
1757 CurrMOps = (CurrMOps <= DecMOps) ? 0 : CurrMOps - DecMOps;
1759 // Decrement DependentLatency based on the next cycle.
1760 if ((NextCycle - CurrCycle) > DependentLatency)
1761 DependentLatency = 0;
1763 DependentLatency -= (NextCycle - CurrCycle);
1765 if (!HazardRec->isEnabled()) {
1766 // Bypass HazardRec virtual calls.
1767 CurrCycle = NextCycle;
1770 // Bypass getHazardType calls in case of long latency.
1771 for (; CurrCycle != NextCycle; ++CurrCycle) {
1773 HazardRec->AdvanceCycle();
1775 HazardRec->RecedeCycle();
1778 CheckPending = true;
1779 unsigned LFactor = SchedModel->getLatencyFactor();
1781 (int)(getCriticalCount() - (getScheduledLatency() * LFactor))
1784 DEBUG(dbgs() << "Cycle: " << CurrCycle << ' ' << Available.getName() << '\n');
1787 void ConvergingScheduler::SchedBoundary::incExecutedResources(unsigned PIdx,
1789 ExecutedResCounts[PIdx] += Count;
1790 if (ExecutedResCounts[PIdx] > MaxExecutedResCount)
1791 MaxExecutedResCount = ExecutedResCounts[PIdx];
1794 /// Add the given processor resource to this scheduled zone.
1796 /// \param Cycles indicates the number of consecutive (non-pipelined) cycles
1797 /// during which this resource is consumed.
1799 /// \return the next cycle at which the instruction may execute without
1800 /// oversubscribing resources.
1801 unsigned ConvergingScheduler::SchedBoundary::
1802 countResource(unsigned PIdx, unsigned Cycles, unsigned ReadyCycle) {
1803 unsigned Factor = SchedModel->getResourceFactor(PIdx);
1804 unsigned Count = Factor * Cycles;
1805 DEBUG(dbgs() << " " << getResourceName(PIdx)
1806 << " +" << Cycles << "x" << Factor << "u\n");
1808 // Update Executed resources counts.
1809 incExecutedResources(PIdx, Count);
1810 assert(Rem->RemainingCounts[PIdx] >= Count && "resource double counted");
1811 Rem->RemainingCounts[PIdx] -= Count;
1813 // Check if this resource exceeds the current critical resource. If so, it
1814 // becomes the critical resource.
1815 if (ZoneCritResIdx != PIdx && (getResourceCount(PIdx) > getCriticalCount())) {
1816 ZoneCritResIdx = PIdx;
1817 DEBUG(dbgs() << " *** Critical resource "
1818 << getResourceName(PIdx) << ": "
1819 << getResourceCount(PIdx) / SchedModel->getLatencyFactor() << "c\n");
1821 // TODO: We don't yet model reserved resources. It's not hard though.
1825 /// Move the boundary of scheduled code by one SUnit.
1826 void ConvergingScheduler::SchedBoundary::bumpNode(SUnit *SU) {
1827 // Update the reservation table.
1828 if (HazardRec->isEnabled()) {
1829 if (!isTop() && SU->isCall) {
1830 // Calls are scheduled with their preceding instructions. For bottom-up
1831 // scheduling, clear the pipeline state before emitting.
1834 HazardRec->EmitInstruction(SU);
1836 const MCSchedClassDesc *SC = DAG->getSchedClass(SU);
1837 unsigned IncMOps = SchedModel->getNumMicroOps(SU->getInstr());
1838 CurrMOps += IncMOps;
1839 // checkHazard prevents scheduling multiple instructions per cycle that exceed
1840 // issue width. However, we commonly reach the maximum. In this case
1841 // opportunistically bump the cycle to avoid uselessly checking everything in
1842 // the readyQ. Furthermore, a single instruction may produce more than one
1843 // cycle's worth of micro-ops.
1845 // TODO: Also check if this SU must end a dispatch group.
1846 unsigned NextCycle = CurrCycle;
1847 if (CurrMOps >= SchedModel->getIssueWidth()) {
1849 DEBUG(dbgs() << " *** Max MOps " << CurrMOps
1850 << " at cycle " << CurrCycle << '\n');
1852 unsigned ReadyCycle = (isTop() ? SU->TopReadyCycle : SU->BotReadyCycle);
1853 DEBUG(dbgs() << " Ready @" << ReadyCycle << "c\n");
1855 switch (SchedModel->getMicroOpBufferSize()) {
1857 assert(ReadyCycle <= CurrCycle && "Broken PendingQueue");
1860 if (ReadyCycle > NextCycle) {
1861 NextCycle = ReadyCycle;
1862 DEBUG(dbgs() << " *** Stall until: " << ReadyCycle << "\n");
1866 // We don't currently model the OOO reorder buffer, so consider all
1867 // scheduled MOps to be "retired".
1870 RetiredMOps += IncMOps;
1872 // Update resource counts and critical resource.
1873 if (SchedModel->hasInstrSchedModel()) {
1874 unsigned DecRemIssue = IncMOps * SchedModel->getMicroOpFactor();
1875 assert(Rem->RemIssueCount >= DecRemIssue && "MOps double counted");
1876 Rem->RemIssueCount -= DecRemIssue;
1877 if (ZoneCritResIdx) {
1878 // Scale scheduled micro-ops for comparing with the critical resource.
1879 unsigned ScaledMOps =
1880 RetiredMOps * SchedModel->getMicroOpFactor();
1882 // If scaled micro-ops are now more than the previous critical resource by
1883 // a full cycle, then micro-ops issue becomes critical.
1884 if ((int)(ScaledMOps - getResourceCount(ZoneCritResIdx))
1885 >= (int)SchedModel->getLatencyFactor()) {
1887 DEBUG(dbgs() << " *** Critical resource NumMicroOps: "
1888 << ScaledMOps / SchedModel->getLatencyFactor() << "c\n");
1891 for (TargetSchedModel::ProcResIter
1892 PI = SchedModel->getWriteProcResBegin(SC),
1893 PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) {
1895 countResource(PI->ProcResourceIdx, PI->Cycles, ReadyCycle);
1896 if (RCycle > NextCycle)
1900 // Update ExpectedLatency and DependentLatency.
1901 unsigned &TopLatency = isTop() ? ExpectedLatency : DependentLatency;
1902 unsigned &BotLatency = isTop() ? DependentLatency : ExpectedLatency;
1903 if (SU->getDepth() > TopLatency) {
1904 TopLatency = SU->getDepth();
1905 DEBUG(dbgs() << " " << Available.getName()
1906 << " TopLatency SU(" << SU->NodeNum << ") " << TopLatency << "c\n");
1908 if (SU->getHeight() > BotLatency) {
1909 BotLatency = SU->getHeight();
1910 DEBUG(dbgs() << " " << Available.getName()
1911 << " BotLatency SU(" << SU->NodeNum << ") " << BotLatency << "c\n");
1913 // If we stall for any reason, bump the cycle.
1914 if (NextCycle > CurrCycle) {
1915 bumpCycle(NextCycle);
1918 // After updating ZoneCritResIdx and ExpectedLatency, check if we're
1919 // resource limited. If a stall occured, bumpCycle does this.
1920 unsigned LFactor = SchedModel->getLatencyFactor();
1922 (int)(getCriticalCount() - (getScheduledLatency() * LFactor))
1925 DEBUG(dumpScheduledState());
1928 /// Release pending ready nodes in to the available queue. This makes them
1929 /// visible to heuristics.
1930 void ConvergingScheduler::SchedBoundary::releasePending() {
1931 // If the available queue is empty, it is safe to reset MinReadyCycle.
1932 if (Available.empty())
1933 MinReadyCycle = UINT_MAX;
1935 // Check to see if any of the pending instructions are ready to issue. If
1936 // so, add them to the available queue.
1937 bool IsBuffered = SchedModel->getMicroOpBufferSize() != 0;
1938 for (unsigned i = 0, e = Pending.size(); i != e; ++i) {
1939 SUnit *SU = *(Pending.begin()+i);
1940 unsigned ReadyCycle = isTop() ? SU->TopReadyCycle : SU->BotReadyCycle;
1942 if (ReadyCycle < MinReadyCycle)
1943 MinReadyCycle = ReadyCycle;
1945 if (!IsBuffered && ReadyCycle > CurrCycle)
1948 if (checkHazard(SU))
1952 Pending.remove(Pending.begin()+i);
1955 DEBUG(if (!Pending.empty()) Pending.dump());
1956 CheckPending = false;
1959 /// Remove SU from the ready set for this boundary.
1960 void ConvergingScheduler::SchedBoundary::removeReady(SUnit *SU) {
1961 if (Available.isInQueue(SU))
1962 Available.remove(Available.find(SU));
1964 assert(Pending.isInQueue(SU) && "bad ready count");
1965 Pending.remove(Pending.find(SU));
1969 /// If this queue only has one ready candidate, return it. As a side effect,
1970 /// defer any nodes that now hit a hazard, and advance the cycle until at least
1971 /// one node is ready. If multiple instructions are ready, return NULL.
1972 SUnit *ConvergingScheduler::SchedBoundary::pickOnlyChoice() {
1977 // Defer any ready instrs that now have a hazard.
1978 for (ReadyQueue::iterator I = Available.begin(); I != Available.end();) {
1979 if (checkHazard(*I)) {
1981 I = Available.remove(I);
1987 for (unsigned i = 0; Available.empty(); ++i) {
1988 assert(i <= (HazardRec->getMaxLookAhead() + MaxObservedLatency) &&
1989 "permanent hazard"); (void)i;
1990 bumpCycle(CurrCycle + 1);
1993 if (Available.size() == 1)
1994 return *Available.begin();
1999 // This is useful information to dump after bumpNode.
2000 // Note that the Queue contents are more useful before pickNodeFromQueue.
2001 void ConvergingScheduler::SchedBoundary::dumpScheduledState() {
2004 if (ZoneCritResIdx) {
2005 ResFactor = SchedModel->getResourceFactor(ZoneCritResIdx);
2006 ResCount = getResourceCount(ZoneCritResIdx);
2009 ResFactor = SchedModel->getMicroOpFactor();
2010 ResCount = RetiredMOps * SchedModel->getMicroOpFactor();
2012 unsigned LFactor = SchedModel->getLatencyFactor();
2013 dbgs() << Available.getName() << " @" << CurrCycle << "c\n"
2014 << " Retired: " << RetiredMOps;
2015 dbgs() << "\n Executed: " << getExecutedCount() / LFactor << "c";
2016 dbgs() << "\n Critical: " << ResCount / LFactor << "c, "
2017 << ResCount / ResFactor << " " << getResourceName(ZoneCritResIdx)
2018 << "\n ExpectedLatency: " << ExpectedLatency << "c\n"
2019 << (IsResourceLimited ? " - Resource" : " - Latency")
2024 void ConvergingScheduler::SchedCandidate::
2025 initResourceDelta(const ScheduleDAGMI *DAG,
2026 const TargetSchedModel *SchedModel) {
2027 if (!Policy.ReduceResIdx && !Policy.DemandResIdx)
2030 const MCSchedClassDesc *SC = DAG->getSchedClass(SU);
2031 for (TargetSchedModel::ProcResIter
2032 PI = SchedModel->getWriteProcResBegin(SC),
2033 PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) {
2034 if (PI->ProcResourceIdx == Policy.ReduceResIdx)
2035 ResDelta.CritResources += PI->Cycles;
2036 if (PI->ProcResourceIdx == Policy.DemandResIdx)
2037 ResDelta.DemandedResources += PI->Cycles;
2042 /// Return true if this heuristic determines order.
2043 static bool tryLess(int TryVal, int CandVal,
2044 ConvergingScheduler::SchedCandidate &TryCand,
2045 ConvergingScheduler::SchedCandidate &Cand,
2046 ConvergingScheduler::CandReason Reason) {
2047 if (TryVal < CandVal) {
2048 TryCand.Reason = Reason;
2051 if (TryVal > CandVal) {
2052 if (Cand.Reason > Reason)
2053 Cand.Reason = Reason;
2056 Cand.setRepeat(Reason);
2060 static bool tryGreater(int TryVal, int CandVal,
2061 ConvergingScheduler::SchedCandidate &TryCand,
2062 ConvergingScheduler::SchedCandidate &Cand,
2063 ConvergingScheduler::CandReason Reason) {
2064 if (TryVal > CandVal) {
2065 TryCand.Reason = Reason;
2068 if (TryVal < CandVal) {
2069 if (Cand.Reason > Reason)
2070 Cand.Reason = Reason;
2073 Cand.setRepeat(Reason);
2077 static bool tryPressure(const PressureElement &TryP,
2078 const PressureElement &CandP,
2079 ConvergingScheduler::SchedCandidate &TryCand,
2080 ConvergingScheduler::SchedCandidate &Cand,
2081 ConvergingScheduler::CandReason Reason) {
2082 // If both candidates affect the same set, go with the smallest increase.
2083 if (TryP.PSetID == CandP.PSetID) {
2084 return tryLess(TryP.UnitIncrease, CandP.UnitIncrease, TryCand, Cand,
2087 // If one candidate decreases and the other increases, go with it.
2088 if (tryLess(TryP.UnitIncrease < 0, CandP.UnitIncrease < 0, TryCand, Cand,
2092 // If TryP has lower Rank, it has a higher priority.
2093 int TryRank = TryP.PSetRank();
2094 int CandRank = CandP.PSetRank();
2095 // If the candidates are decreasing pressure, reverse priority.
2096 if (TryP.UnitIncrease < 0)
2097 std::swap(TryRank, CandRank);
2098 return tryGreater(TryRank, CandRank, TryCand, Cand, Reason);
2101 static unsigned getWeakLeft(const SUnit *SU, bool isTop) {
2102 return (isTop) ? SU->WeakPredsLeft : SU->WeakSuccsLeft;
2105 /// Minimize physical register live ranges. Regalloc wants them adjacent to
2106 /// their physreg def/use.
2108 /// FIXME: This is an unnecessary check on the critical path. Most are root/leaf
2109 /// copies which can be prescheduled. The rest (e.g. x86 MUL) could be bundled
2110 /// with the operation that produces or consumes the physreg. We'll do this when
2111 /// regalloc has support for parallel copies.
2112 static int biasPhysRegCopy(const SUnit *SU, bool isTop) {
2113 const MachineInstr *MI = SU->getInstr();
2117 unsigned ScheduledOper = isTop ? 1 : 0;
2118 unsigned UnscheduledOper = isTop ? 0 : 1;
2119 // If we have already scheduled the physreg produce/consumer, immediately
2120 // schedule the copy.
2121 if (TargetRegisterInfo::isPhysicalRegister(
2122 MI->getOperand(ScheduledOper).getReg()))
2124 // If the physreg is at the boundary, defer it. Otherwise schedule it
2125 // immediately to free the dependent. We can hoist the copy later.
2126 bool AtBoundary = isTop ? !SU->NumSuccsLeft : !SU->NumPredsLeft;
2127 if (TargetRegisterInfo::isPhysicalRegister(
2128 MI->getOperand(UnscheduledOper).getReg()))
2129 return AtBoundary ? -1 : 1;
2133 static bool tryLatency(ConvergingScheduler::SchedCandidate &TryCand,
2134 ConvergingScheduler::SchedCandidate &Cand,
2135 ConvergingScheduler::SchedBoundary &Zone) {
2137 if (Cand.SU->getDepth() > Zone.getScheduledLatency()) {
2138 if (tryLess(TryCand.SU->getDepth(), Cand.SU->getDepth(),
2139 TryCand, Cand, ConvergingScheduler::TopDepthReduce))
2142 if (tryGreater(TryCand.SU->getHeight(), Cand.SU->getHeight(),
2143 TryCand, Cand, ConvergingScheduler::TopPathReduce))
2147 if (Cand.SU->getHeight() > Zone.getScheduledLatency()) {
2148 if (tryLess(TryCand.SU->getHeight(), Cand.SU->getHeight(),
2149 TryCand, Cand, ConvergingScheduler::BotHeightReduce))
2152 if (tryGreater(TryCand.SU->getDepth(), Cand.SU->getDepth(),
2153 TryCand, Cand, ConvergingScheduler::BotPathReduce))
2159 /// Apply a set of heursitics to a new candidate. Heuristics are currently
2160 /// hierarchical. This may be more efficient than a graduated cost model because
2161 /// we don't need to evaluate all aspects of the model for each node in the
2162 /// queue. But it's really done to make the heuristics easier to debug and
2163 /// statistically analyze.
2165 /// \param Cand provides the policy and current best candidate.
2166 /// \param TryCand refers to the next SUnit candidate, otherwise uninitialized.
2167 /// \param Zone describes the scheduled zone that we are extending.
2168 /// \param RPTracker describes reg pressure within the scheduled zone.
2169 /// \param TempTracker is a scratch pressure tracker to reuse in queries.
2170 void ConvergingScheduler::tryCandidate(SchedCandidate &Cand,
2171 SchedCandidate &TryCand,
2172 SchedBoundary &Zone,
2173 const RegPressureTracker &RPTracker,
2174 RegPressureTracker &TempTracker) {
2176 // Always initialize TryCand's RPDelta.
2177 TempTracker.getMaxPressureDelta(TryCand.SU->getInstr(), TryCand.RPDelta,
2178 DAG->getRegionCriticalPSets(),
2179 DAG->getRegPressure().MaxSetPressure);
2181 // Initialize the candidate if needed.
2182 if (!Cand.isValid()) {
2183 TryCand.Reason = NodeOrder;
2187 if (tryGreater(biasPhysRegCopy(TryCand.SU, Zone.isTop()),
2188 biasPhysRegCopy(Cand.SU, Zone.isTop()),
2189 TryCand, Cand, PhysRegCopy))
2192 // Avoid exceeding the target's limit. If signed PSetID is negative, it is
2193 // invalid; convert it to INT_MAX to give it lowest priority.
2194 if (tryPressure(TryCand.RPDelta.Excess, Cand.RPDelta.Excess, TryCand, Cand,
2198 // For loops that are acyclic path limited, aggressively schedule for latency.
2199 if (Rem.IsAcyclicLatencyLimited && tryLatency(TryCand, Cand, Zone))
2202 // Avoid increasing the max critical pressure in the scheduled region.
2203 if (tryPressure(TryCand.RPDelta.CriticalMax, Cand.RPDelta.CriticalMax,
2204 TryCand, Cand, RegCritical))
2207 // Keep clustered nodes together to encourage downstream peephole
2208 // optimizations which may reduce resource requirements.
2210 // This is a best effort to set things up for a post-RA pass. Optimizations
2211 // like generating loads of multiple registers should ideally be done within
2212 // the scheduler pass by combining the loads during DAG postprocessing.
2213 const SUnit *NextClusterSU =
2214 Zone.isTop() ? DAG->getNextClusterSucc() : DAG->getNextClusterPred();
2215 if (tryGreater(TryCand.SU == NextClusterSU, Cand.SU == NextClusterSU,
2216 TryCand, Cand, Cluster))
2219 // Weak edges are for clustering and other constraints.
2220 if (tryLess(getWeakLeft(TryCand.SU, Zone.isTop()),
2221 getWeakLeft(Cand.SU, Zone.isTop()),
2222 TryCand, Cand, Weak)) {
2225 // Avoid increasing the max pressure of the entire region.
2226 if (tryPressure(TryCand.RPDelta.CurrentMax, Cand.RPDelta.CurrentMax,
2227 TryCand, Cand, RegMax))
2230 // Avoid critical resource consumption and balance the schedule.
2231 TryCand.initResourceDelta(DAG, SchedModel);
2232 if (tryLess(TryCand.ResDelta.CritResources, Cand.ResDelta.CritResources,
2233 TryCand, Cand, ResourceReduce))
2235 if (tryGreater(TryCand.ResDelta.DemandedResources,
2236 Cand.ResDelta.DemandedResources,
2237 TryCand, Cand, ResourceDemand))
2240 // Avoid serializing long latency dependence chains.
2241 // For acyclic path limited loops, latency was already checked above.
2242 if (Cand.Policy.ReduceLatency && !Rem.IsAcyclicLatencyLimited
2243 && tryLatency(TryCand, Cand, Zone)) {
2247 // Prefer immediate defs/users of the last scheduled instruction. This is a
2248 // local pressure avoidance strategy that also makes the machine code
2250 if (tryGreater(Zone.NextSUs.count(TryCand.SU), Zone.NextSUs.count(Cand.SU),
2251 TryCand, Cand, NextDefUse))
2254 // Fall through to original instruction order.
2255 if ((Zone.isTop() && TryCand.SU->NodeNum < Cand.SU->NodeNum)
2256 || (!Zone.isTop() && TryCand.SU->NodeNum > Cand.SU->NodeNum)) {
2257 TryCand.Reason = NodeOrder;
2262 const char *ConvergingScheduler::getReasonStr(
2263 ConvergingScheduler::CandReason Reason) {
2265 case NoCand: return "NOCAND ";
2266 case PhysRegCopy: return "PREG-COPY";
2267 case RegExcess: return "REG-EXCESS";
2268 case RegCritical: return "REG-CRIT ";
2269 case Cluster: return "CLUSTER ";
2270 case Weak: return "WEAK ";
2271 case RegMax: return "REG-MAX ";
2272 case ResourceReduce: return "RES-REDUCE";
2273 case ResourceDemand: return "RES-DEMAND";
2274 case TopDepthReduce: return "TOP-DEPTH ";
2275 case TopPathReduce: return "TOP-PATH ";
2276 case BotHeightReduce:return "BOT-HEIGHT";
2277 case BotPathReduce: return "BOT-PATH ";
2278 case NextDefUse: return "DEF-USE ";
2279 case NodeOrder: return "ORDER ";
2281 llvm_unreachable("Unknown reason!");
2284 void ConvergingScheduler::traceCandidate(const SchedCandidate &Cand) {
2286 unsigned ResIdx = 0;
2287 unsigned Latency = 0;
2288 switch (Cand.Reason) {
2292 P = Cand.RPDelta.Excess;
2295 P = Cand.RPDelta.CriticalMax;
2298 P = Cand.RPDelta.CurrentMax;
2300 case ResourceReduce:
2301 ResIdx = Cand.Policy.ReduceResIdx;
2303 case ResourceDemand:
2304 ResIdx = Cand.Policy.DemandResIdx;
2306 case TopDepthReduce:
2307 Latency = Cand.SU->getDepth();
2310 Latency = Cand.SU->getHeight();
2312 case BotHeightReduce:
2313 Latency = Cand.SU->getHeight();
2316 Latency = Cand.SU->getDepth();
2319 dbgs() << " SU(" << Cand.SU->NodeNum << ") " << getReasonStr(Cand.Reason);
2321 dbgs() << " " << TRI->getRegPressureSetName(P.PSetID)
2322 << ":" << P.UnitIncrease << " ";
2326 dbgs() << " " << SchedModel->getProcResource(ResIdx)->Name << " ";
2330 dbgs() << " " << Latency << " cycles ";
2337 /// Pick the best candidate from the top queue.
2339 /// TODO: getMaxPressureDelta results can be mostly cached for each SUnit during
2340 /// DAG building. To adjust for the current scheduling location we need to
2341 /// maintain the number of vreg uses remaining to be top-scheduled.
2342 void ConvergingScheduler::pickNodeFromQueue(SchedBoundary &Zone,
2343 const RegPressureTracker &RPTracker,
2344 SchedCandidate &Cand) {
2345 ReadyQueue &Q = Zone.Available;
2349 // getMaxPressureDelta temporarily modifies the tracker.
2350 RegPressureTracker &TempTracker = const_cast<RegPressureTracker&>(RPTracker);
2352 for (ReadyQueue::iterator I = Q.begin(), E = Q.end(); I != E; ++I) {
2354 SchedCandidate TryCand(Cand.Policy);
2356 tryCandidate(Cand, TryCand, Zone, RPTracker, TempTracker);
2357 if (TryCand.Reason != NoCand) {
2358 // Initialize resource delta if needed in case future heuristics query it.
2359 if (TryCand.ResDelta == SchedResourceDelta())
2360 TryCand.initResourceDelta(DAG, SchedModel);
2361 Cand.setBest(TryCand);
2362 DEBUG(traceCandidate(Cand));
2367 static void tracePick(const ConvergingScheduler::SchedCandidate &Cand,
2369 DEBUG(dbgs() << "Pick " << (IsTop ? "Top " : "Bot ")
2370 << ConvergingScheduler::getReasonStr(Cand.Reason) << '\n');
2373 /// Pick the best candidate node from either the top or bottom queue.
2374 SUnit *ConvergingScheduler::pickNodeBidirectional(bool &IsTopNode) {
2375 // Schedule as far as possible in the direction of no choice. This is most
2376 // efficient, but also provides the best heuristics for CriticalPSets.
2377 if (SUnit *SU = Bot.pickOnlyChoice()) {
2379 DEBUG(dbgs() << "Pick Bot NOCAND\n");
2382 if (SUnit *SU = Top.pickOnlyChoice()) {
2384 DEBUG(dbgs() << "Pick Top NOCAND\n");
2387 CandPolicy NoPolicy;
2388 SchedCandidate BotCand(NoPolicy);
2389 SchedCandidate TopCand(NoPolicy);
2390 Bot.setPolicy(BotCand.Policy, Top);
2391 Top.setPolicy(TopCand.Policy, Bot);
2393 // Prefer bottom scheduling when heuristics are silent.
2394 pickNodeFromQueue(Bot, DAG->getBotRPTracker(), BotCand);
2395 assert(BotCand.Reason != NoCand && "failed to find the first candidate");
2397 // If either Q has a single candidate that provides the least increase in
2398 // Excess pressure, we can immediately schedule from that Q.
2400 // RegionCriticalPSets summarizes the pressure within the scheduled region and
2401 // affects picking from either Q. If scheduling in one direction must
2402 // increase pressure for one of the excess PSets, then schedule in that
2403 // direction first to provide more freedom in the other direction.
2404 if ((BotCand.Reason == RegExcess && !BotCand.isRepeat(RegExcess))
2405 || (BotCand.Reason == RegCritical
2406 && !BotCand.isRepeat(RegCritical)))
2409 tracePick(BotCand, IsTopNode);
2412 // Check if the top Q has a better candidate.
2413 pickNodeFromQueue(Top, DAG->getTopRPTracker(), TopCand);
2414 assert(TopCand.Reason != NoCand && "failed to find the first candidate");
2416 // Choose the queue with the most important (lowest enum) reason.
2417 if (TopCand.Reason < BotCand.Reason) {
2419 tracePick(TopCand, IsTopNode);
2422 // Otherwise prefer the bottom candidate, in node order if all else failed.
2424 tracePick(BotCand, IsTopNode);
2428 /// Pick the best node to balance the schedule. Implements MachineSchedStrategy.
2429 SUnit *ConvergingScheduler::pickNode(bool &IsTopNode) {
2430 if (DAG->top() == DAG->bottom()) {
2431 assert(Top.Available.empty() && Top.Pending.empty() &&
2432 Bot.Available.empty() && Bot.Pending.empty() && "ReadyQ garbage");
2438 SU = Top.pickOnlyChoice();
2440 CandPolicy NoPolicy;
2441 SchedCandidate TopCand(NoPolicy);
2442 pickNodeFromQueue(Top, DAG->getTopRPTracker(), TopCand);
2443 assert(TopCand.Reason != NoCand && "failed to find the first candidate");
2448 else if (ForceBottomUp) {
2449 SU = Bot.pickOnlyChoice();
2451 CandPolicy NoPolicy;
2452 SchedCandidate BotCand(NoPolicy);
2453 pickNodeFromQueue(Bot, DAG->getBotRPTracker(), BotCand);
2454 assert(BotCand.Reason != NoCand && "failed to find the first candidate");
2460 SU = pickNodeBidirectional(IsTopNode);
2462 } while (SU->isScheduled);
2464 if (SU->isTopReady())
2465 Top.removeReady(SU);
2466 if (SU->isBottomReady())
2467 Bot.removeReady(SU);
2469 DEBUG(dbgs() << "Scheduling SU(" << SU->NodeNum << ") " << *SU->getInstr());
2473 void ConvergingScheduler::reschedulePhysRegCopies(SUnit *SU, bool isTop) {
2475 MachineBasicBlock::iterator InsertPos = SU->getInstr();
2478 SmallVectorImpl<SDep> &Deps = isTop ? SU->Preds : SU->Succs;
2480 // Find already scheduled copies with a single physreg dependence and move
2481 // them just above the scheduled instruction.
2482 for (SmallVectorImpl<SDep>::iterator I = Deps.begin(), E = Deps.end();
2484 if (I->getKind() != SDep::Data || !TRI->isPhysicalRegister(I->getReg()))
2486 SUnit *DepSU = I->getSUnit();
2487 if (isTop ? DepSU->Succs.size() > 1 : DepSU->Preds.size() > 1)
2489 MachineInstr *Copy = DepSU->getInstr();
2490 if (!Copy->isCopy())
2492 DEBUG(dbgs() << " Rescheduling physreg copy ";
2493 I->getSUnit()->dump(DAG));
2494 DAG->moveInstruction(Copy, InsertPos);
2498 /// Update the scheduler's state after scheduling a node. This is the same node
2499 /// that was just returned by pickNode(). However, ScheduleDAGMI needs to update
2500 /// it's state based on the current cycle before MachineSchedStrategy does.
2502 /// FIXME: Eventually, we may bundle physreg copies rather than rescheduling
2503 /// them here. See comments in biasPhysRegCopy.
2504 void ConvergingScheduler::schedNode(SUnit *SU, bool IsTopNode) {
2506 SU->TopReadyCycle = std::max(SU->TopReadyCycle, Top.CurrCycle);
2508 if (SU->hasPhysRegUses)
2509 reschedulePhysRegCopies(SU, true);
2512 SU->BotReadyCycle = std::max(SU->BotReadyCycle, Bot.CurrCycle);
2514 if (SU->hasPhysRegDefs)
2515 reschedulePhysRegCopies(SU, false);
2519 /// Create the standard converging machine scheduler. This will be used as the
2520 /// default scheduler if the target does not set a default.
2521 static ScheduleDAGInstrs *createConvergingSched(MachineSchedContext *C) {
2522 assert((!ForceTopDown || !ForceBottomUp) &&
2523 "-misched-topdown incompatible with -misched-bottomup");
2524 ScheduleDAGMI *DAG = new ScheduleDAGMI(C, new ConvergingScheduler());
2525 // Register DAG post-processors.
2527 // FIXME: extend the mutation API to allow earlier mutations to instantiate
2528 // data and pass it to later mutations. Have a single mutation that gathers
2529 // the interesting nodes in one pass.
2530 DAG->addMutation(new CopyConstrain(DAG->TII, DAG->TRI));
2531 if (EnableLoadCluster)
2532 DAG->addMutation(new LoadClusterMutation(DAG->TII, DAG->TRI));
2533 if (EnableMacroFusion)
2534 DAG->addMutation(new MacroFusion(DAG->TII));
2537 static MachineSchedRegistry
2538 ConvergingSchedRegistry("converge", "Standard converging scheduler.",
2539 createConvergingSched);
2541 //===----------------------------------------------------------------------===//
2542 // ILP Scheduler. Currently for experimental analysis of heuristics.
2543 //===----------------------------------------------------------------------===//
2546 /// \brief Order nodes by the ILP metric.
2548 const SchedDFSResult *DFSResult;
2549 const BitVector *ScheduledTrees;
2552 ILPOrder(bool MaxILP): DFSResult(0), ScheduledTrees(0), MaximizeILP(MaxILP) {}
2554 /// \brief Apply a less-than relation on node priority.
2556 /// (Return true if A comes after B in the Q.)
2557 bool operator()(const SUnit *A, const SUnit *B) const {
2558 unsigned SchedTreeA = DFSResult->getSubtreeID(A);
2559 unsigned SchedTreeB = DFSResult->getSubtreeID(B);
2560 if (SchedTreeA != SchedTreeB) {
2561 // Unscheduled trees have lower priority.
2562 if (ScheduledTrees->test(SchedTreeA) != ScheduledTrees->test(SchedTreeB))
2563 return ScheduledTrees->test(SchedTreeB);
2565 // Trees with shallower connections have have lower priority.
2566 if (DFSResult->getSubtreeLevel(SchedTreeA)
2567 != DFSResult->getSubtreeLevel(SchedTreeB)) {
2568 return DFSResult->getSubtreeLevel(SchedTreeA)
2569 < DFSResult->getSubtreeLevel(SchedTreeB);
2573 return DFSResult->getILP(A) < DFSResult->getILP(B);
2575 return DFSResult->getILP(A) > DFSResult->getILP(B);
2579 /// \brief Schedule based on the ILP metric.
2580 class ILPScheduler : public MachineSchedStrategy {
2581 /// In case all subtrees are eventually connected to a common root through
2582 /// data dependence (e.g. reduction), place an upper limit on their size.
2584 /// FIXME: A subtree limit is generally good, but in the situation commented
2585 /// above, where multiple similar subtrees feed a common root, we should
2586 /// only split at a point where the resulting subtrees will be balanced.
2587 /// (a motivating test case must be found).
2588 static const unsigned SubtreeLimit = 16;
2593 std::vector<SUnit*> ReadyQ;
2595 ILPScheduler(bool MaximizeILP): DAG(0), Cmp(MaximizeILP) {}
2597 virtual void initialize(ScheduleDAGMI *dag) {
2599 DAG->computeDFSResult();
2600 Cmp.DFSResult = DAG->getDFSResult();
2601 Cmp.ScheduledTrees = &DAG->getScheduledTrees();
2605 virtual void registerRoots() {
2606 // Restore the heap in ReadyQ with the updated DFS results.
2607 std::make_heap(ReadyQ.begin(), ReadyQ.end(), Cmp);
2610 /// Implement MachineSchedStrategy interface.
2611 /// -----------------------------------------
2613 /// Callback to select the highest priority node from the ready Q.
2614 virtual SUnit *pickNode(bool &IsTopNode) {
2615 if (ReadyQ.empty()) return NULL;
2616 std::pop_heap(ReadyQ.begin(), ReadyQ.end(), Cmp);
2617 SUnit *SU = ReadyQ.back();
2620 DEBUG(dbgs() << "Pick node " << "SU(" << SU->NodeNum << ") "
2621 << " ILP: " << DAG->getDFSResult()->getILP(SU)
2622 << " Tree: " << DAG->getDFSResult()->getSubtreeID(SU) << " @"
2623 << DAG->getDFSResult()->getSubtreeLevel(
2624 DAG->getDFSResult()->getSubtreeID(SU)) << '\n'
2625 << "Scheduling " << *SU->getInstr());
2629 /// \brief Scheduler callback to notify that a new subtree is scheduled.
2630 virtual void scheduleTree(unsigned SubtreeID) {
2631 std::make_heap(ReadyQ.begin(), ReadyQ.end(), Cmp);
2634 /// Callback after a node is scheduled. Mark a newly scheduled tree, notify
2635 /// DFSResults, and resort the priority Q.
2636 virtual void schedNode(SUnit *SU, bool IsTopNode) {
2637 assert(!IsTopNode && "SchedDFSResult needs bottom-up");
2640 virtual void releaseTopNode(SUnit *) { /*only called for top roots*/ }
2642 virtual void releaseBottomNode(SUnit *SU) {
2643 ReadyQ.push_back(SU);
2644 std::push_heap(ReadyQ.begin(), ReadyQ.end(), Cmp);
2649 static ScheduleDAGInstrs *createILPMaxScheduler(MachineSchedContext *C) {
2650 return new ScheduleDAGMI(C, new ILPScheduler(true));
2652 static ScheduleDAGInstrs *createILPMinScheduler(MachineSchedContext *C) {
2653 return new ScheduleDAGMI(C, new ILPScheduler(false));
2655 static MachineSchedRegistry ILPMaxRegistry(
2656 "ilpmax", "Schedule bottom-up for max ILP", createILPMaxScheduler);
2657 static MachineSchedRegistry ILPMinRegistry(
2658 "ilpmin", "Schedule bottom-up for min ILP", createILPMinScheduler);
2660 //===----------------------------------------------------------------------===//
2661 // Machine Instruction Shuffler for Correctness Testing
2662 //===----------------------------------------------------------------------===//
2666 /// Apply a less-than relation on the node order, which corresponds to the
2667 /// instruction order prior to scheduling. IsReverse implements greater-than.
2668 template<bool IsReverse>
2670 bool operator()(SUnit *A, SUnit *B) const {
2672 return A->NodeNum > B->NodeNum;
2674 return A->NodeNum < B->NodeNum;
2678 /// Reorder instructions as much as possible.
2679 class InstructionShuffler : public MachineSchedStrategy {
2683 // Using a less-than relation (SUnitOrder<false>) for the TopQ priority
2684 // gives nodes with a higher number higher priority causing the latest
2685 // instructions to be scheduled first.
2686 PriorityQueue<SUnit*, std::vector<SUnit*>, SUnitOrder<false> >
2688 // When scheduling bottom-up, use greater-than as the queue priority.
2689 PriorityQueue<SUnit*, std::vector<SUnit*>, SUnitOrder<true> >
2692 InstructionShuffler(bool alternate, bool topdown)
2693 : IsAlternating(alternate), IsTopDown(topdown) {}
2695 virtual void initialize(ScheduleDAGMI *) {
2700 /// Implement MachineSchedStrategy interface.
2701 /// -----------------------------------------
2703 virtual SUnit *pickNode(bool &IsTopNode) {
2707 if (TopQ.empty()) return NULL;
2710 } while (SU->isScheduled);
2715 if (BottomQ.empty()) return NULL;
2718 } while (SU->isScheduled);
2722 IsTopDown = !IsTopDown;
2726 virtual void schedNode(SUnit *SU, bool IsTopNode) {}
2728 virtual void releaseTopNode(SUnit *SU) {
2731 virtual void releaseBottomNode(SUnit *SU) {
2737 static ScheduleDAGInstrs *createInstructionShuffler(MachineSchedContext *C) {
2738 bool Alternate = !ForceTopDown && !ForceBottomUp;
2739 bool TopDown = !ForceBottomUp;
2740 assert((TopDown || !ForceTopDown) &&
2741 "-misched-topdown incompatible with -misched-bottomup");
2742 return new ScheduleDAGMI(C, new InstructionShuffler(Alternate, TopDown));
2744 static MachineSchedRegistry ShufflerRegistry(
2745 "shuffle", "Shuffle machine instructions alternating directions",
2746 createInstructionShuffler);
2749 //===----------------------------------------------------------------------===//
2750 // GraphWriter support for ScheduleDAGMI.
2751 //===----------------------------------------------------------------------===//
2756 template<> struct GraphTraits<
2757 ScheduleDAGMI*> : public GraphTraits<ScheduleDAG*> {};
2760 struct DOTGraphTraits<ScheduleDAGMI*> : public DefaultDOTGraphTraits {
2762 DOTGraphTraits (bool isSimple=false) : DefaultDOTGraphTraits(isSimple) {}
2764 static std::string getGraphName(const ScheduleDAG *G) {
2765 return G->MF.getName();
2768 static bool renderGraphFromBottomUp() {
2772 static bool isNodeHidden(const SUnit *Node) {
2773 return (Node->NumPreds > 10 || Node->NumSuccs > 10);
2776 static bool hasNodeAddressLabel(const SUnit *Node,
2777 const ScheduleDAG *Graph) {
2781 /// If you want to override the dot attributes printed for a particular
2782 /// edge, override this method.
2783 static std::string getEdgeAttributes(const SUnit *Node,
2785 const ScheduleDAG *Graph) {
2786 if (EI.isArtificialDep())
2787 return "color=cyan,style=dashed";
2789 return "color=blue,style=dashed";
2793 static std::string getNodeLabel(const SUnit *SU, const ScheduleDAG *G) {
2795 raw_string_ostream SS(Str);
2796 SS << "SU(" << SU->NodeNum << ')';
2799 static std::string getNodeDescription(const SUnit *SU, const ScheduleDAG *G) {
2800 return G->getGraphNodeLabel(SU);
2803 static std::string getNodeAttributes(const SUnit *N,
2804 const ScheduleDAG *Graph) {
2805 std::string Str("shape=Mrecord");
2806 const SchedDFSResult *DFS =
2807 static_cast<const ScheduleDAGMI*>(Graph)->getDFSResult();
2809 Str += ",style=filled,fillcolor=\"#";
2810 Str += DOT::getColorString(DFS->getSubtreeID(N));
2819 /// viewGraph - Pop up a ghostview window with the reachable parts of the DAG
2820 /// rendered using 'dot'.
2822 void ScheduleDAGMI::viewGraph(const Twine &Name, const Twine &Title) {
2824 ViewGraph(this, Name, false, Title);
2826 errs() << "ScheduleDAGMI::viewGraph is only available in debug builds on "
2827 << "systems with Graphviz or gv!\n";
2831 /// Out-of-line implementation with no arguments is handy for gdb.
2832 void ScheduleDAGMI::viewGraph() {
2833 viewGraph(getDAGName(), "Scheduling-Units Graph for " + getDAGName());