1 //===-- lib/Codegen/MachineRegisterInfo.cpp -------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Implementation of the MachineRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/MachineRegisterInfo.h"
15 #include "llvm/CodeGen/MachineInstrBuilder.h"
16 #include "llvm/Support/raw_os_ostream.h"
17 #include "llvm/Target/TargetInstrInfo.h"
18 #include "llvm/Target/TargetMachine.h"
19 #include "llvm/Target/TargetSubtargetInfo.h"
23 // Pin the vtable to this file.
24 void MachineRegisterInfo::Delegate::anchor() {}
26 MachineRegisterInfo::MachineRegisterInfo(const MachineFunction *MF)
27 : MF(MF), TheDelegate(nullptr), IsSSA(true), TracksLiveness(true),
28 TracksSubRegLiveness(false) {
29 VRegInfo.reserve(256);
30 RegAllocHints.reserve(256);
31 UsedRegUnits.resize(getTargetRegisterInfo()->getNumRegUnits());
32 UsedPhysRegMask.resize(getTargetRegisterInfo()->getNumRegs());
34 // Create the physreg use/def lists.
35 PhysRegUseDefLists.resize(getTargetRegisterInfo()->getNumRegs(), nullptr);
38 /// setRegClass - Set the register class of the specified virtual register.
41 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) {
42 assert(RC && RC->isAllocatable() && "Invalid RC for virtual register");
43 VRegInfo[Reg].first = RC;
46 const TargetRegisterClass *
47 MachineRegisterInfo::constrainRegClass(unsigned Reg,
48 const TargetRegisterClass *RC,
49 unsigned MinNumRegs) {
50 const TargetRegisterClass *OldRC = getRegClass(Reg);
53 const TargetRegisterClass *NewRC =
54 getTargetRegisterInfo()->getCommonSubClass(OldRC, RC);
55 if (!NewRC || NewRC == OldRC)
57 if (NewRC->getNumRegs() < MinNumRegs)
59 setRegClass(Reg, NewRC);
64 MachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) {
65 const TargetInstrInfo *TII = TM.getSubtargetImpl()->getInstrInfo();
66 const TargetRegisterClass *OldRC = getRegClass(Reg);
67 const TargetRegisterClass *NewRC =
68 getTargetRegisterInfo()->getLargestLegalSuperClass(OldRC);
70 // Stop early if there is no room to grow.
74 // Accumulate constraints from all uses.
75 for (MachineOperand &MO : reg_nodbg_operands(Reg)) {
76 // Apply the effect of the given operand to NewRC.
77 MachineInstr *MI = MO.getParent();
78 unsigned OpNo = &MO - &MI->getOperand(0);
79 NewRC = MI->getRegClassConstraintEffect(OpNo, NewRC, TII,
80 getTargetRegisterInfo());
81 if (!NewRC || NewRC == OldRC)
84 setRegClass(Reg, NewRC);
88 /// createVirtualRegister - Create and return a new virtual register in the
89 /// function with the specified register class.
92 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){
93 assert(RegClass && "Cannot create register without RegClass!");
94 assert(RegClass->isAllocatable() &&
95 "Virtual register RegClass must be allocatable.");
97 // New virtual register number.
98 unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs());
100 VRegInfo[Reg].first = RegClass;
101 RegAllocHints.grow(Reg);
103 TheDelegate->MRI_NoteNewVirtualRegister(Reg);
107 /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
108 void MachineRegisterInfo::clearVirtRegs() {
110 for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) {
111 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
112 if (!VRegInfo[Reg].second)
115 llvm_unreachable("Remaining virtual register operands");
121 void MachineRegisterInfo::verifyUseList(unsigned Reg) const {
124 for (MachineOperand &M : reg_operands(Reg)) {
125 MachineOperand *MO = &M;
126 MachineInstr *MI = MO->getParent();
128 errs() << PrintReg(Reg, getTargetRegisterInfo())
129 << " use list MachineOperand " << MO
130 << " has no parent instruction.\n";
133 MachineOperand *MO0 = &MI->getOperand(0);
134 unsigned NumOps = MI->getNumOperands();
135 if (!(MO >= MO0 && MO < MO0+NumOps)) {
136 errs() << PrintReg(Reg, getTargetRegisterInfo())
137 << " use list MachineOperand " << MO
138 << " doesn't belong to parent MI: " << *MI;
142 errs() << PrintReg(Reg, getTargetRegisterInfo())
143 << " MachineOperand " << MO << ": " << *MO
144 << " is not a register\n";
147 if (MO->getReg() != Reg) {
148 errs() << PrintReg(Reg, getTargetRegisterInfo())
149 << " use-list MachineOperand " << MO << ": "
150 << *MO << " is the wrong register\n";
154 assert(Valid && "Invalid use list");
158 void MachineRegisterInfo::verifyUseLists() const {
160 for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i)
161 verifyUseList(TargetRegisterInfo::index2VirtReg(i));
162 for (unsigned i = 1, e = getTargetRegisterInfo()->getNumRegs(); i != e; ++i)
167 /// Add MO to the linked list of operands for its register.
168 void MachineRegisterInfo::addRegOperandToUseList(MachineOperand *MO) {
169 assert(!MO->isOnRegUseList() && "Already on list");
170 MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());
171 MachineOperand *const Head = HeadRef;
173 // Head points to the first list element.
174 // Next is NULL on the last list element.
175 // Prev pointers are circular, so Head->Prev == Last.
177 // Head is NULL for an empty list.
179 MO->Contents.Reg.Prev = MO;
180 MO->Contents.Reg.Next = nullptr;
184 assert(MO->getReg() == Head->getReg() && "Different regs on the same list!");
186 // Insert MO between Last and Head in the circular Prev chain.
187 MachineOperand *Last = Head->Contents.Reg.Prev;
188 assert(Last && "Inconsistent use list");
189 assert(MO->getReg() == Last->getReg() && "Different regs on the same list!");
190 Head->Contents.Reg.Prev = MO;
191 MO->Contents.Reg.Prev = Last;
193 // Def operands always precede uses. This allows def_iterator to stop early.
194 // Insert def operands at the front, and use operands at the back.
196 // Insert def at the front.
197 MO->Contents.Reg.Next = Head;
200 // Insert use at the end.
201 MO->Contents.Reg.Next = nullptr;
202 Last->Contents.Reg.Next = MO;
206 /// Remove MO from its use-def list.
207 void MachineRegisterInfo::removeRegOperandFromUseList(MachineOperand *MO) {
208 assert(MO->isOnRegUseList() && "Operand not on use list");
209 MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());
210 MachineOperand *const Head = HeadRef;
211 assert(Head && "List already empty");
213 // Unlink this from the doubly linked list of operands.
214 MachineOperand *Next = MO->Contents.Reg.Next;
215 MachineOperand *Prev = MO->Contents.Reg.Prev;
217 // Prev links are circular, next link is NULL instead of looping back to Head.
221 Prev->Contents.Reg.Next = Next;
223 (Next ? Next : Head)->Contents.Reg.Prev = Prev;
225 MO->Contents.Reg.Prev = nullptr;
226 MO->Contents.Reg.Next = nullptr;
229 /// Move NumOps operands from Src to Dst, updating use-def lists as needed.
231 /// The Dst range is assumed to be uninitialized memory. (Or it may contain
232 /// operands that won't be destroyed, which is OK because the MO destructor is
235 /// The Src and Dst ranges may overlap.
236 void MachineRegisterInfo::moveOperands(MachineOperand *Dst,
239 assert(Src != Dst && NumOps && "Noop moveOperands");
241 // Copy backwards if Dst is within the Src range.
243 if (Dst >= Src && Dst < Src + NumOps) {
249 // Copy one operand at a time.
251 new (Dst) MachineOperand(*Src);
253 // Dst takes Src's place in the use-def chain.
255 MachineOperand *&Head = getRegUseDefListHead(Src->getReg());
256 MachineOperand *Prev = Src->Contents.Reg.Prev;
257 MachineOperand *Next = Src->Contents.Reg.Next;
258 assert(Head && "List empty, but operand is chained");
259 assert(Prev && "Operand was not on use-def list");
261 // Prev links are circular, next link is NULL instead of looping back to
266 Prev->Contents.Reg.Next = Dst;
268 // Update Prev pointer. This also works when Src was pointing to itself
269 // in a 1-element list. In that case Head == Dst.
270 (Next ? Next : Head)->Contents.Reg.Prev = Dst;
278 /// replaceRegWith - Replace all instances of FromReg with ToReg in the
279 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
280 /// except that it also changes any definitions of the register as well.
281 /// If ToReg is a physical register we apply the sub register to obtain the
282 /// final/proper physical register.
283 void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) {
284 assert(FromReg != ToReg && "Cannot replace a reg with itself");
286 const TargetRegisterInfo *TRI = getTargetRegisterInfo();
288 // TODO: This could be more efficient by bulk changing the operands.
289 for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) {
290 MachineOperand &O = *I;
292 if (TargetRegisterInfo::isPhysicalRegister(ToReg)) {
293 O.substPhysReg(ToReg, *TRI);
300 /// getVRegDef - Return the machine instr that defines the specified virtual
301 /// register or null if none is found. This assumes that the code is in SSA
302 /// form, so there should only be one definition.
303 MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const {
304 // Since we are in SSA form, we can use the first definition.
305 def_instr_iterator I = def_instr_begin(Reg);
306 assert((I.atEnd() || std::next(I) == def_instr_end()) &&
307 "getVRegDef assumes a single definition or no definition");
308 return !I.atEnd() ? &*I : nullptr;
311 /// getUniqueVRegDef - Return the unique machine instr that defines the
312 /// specified virtual register or null if none is found. If there are
313 /// multiple definitions or no definition, return null.
314 MachineInstr *MachineRegisterInfo::getUniqueVRegDef(unsigned Reg) const {
315 if (def_empty(Reg)) return nullptr;
316 def_instr_iterator I = def_instr_begin(Reg);
317 if (std::next(I) != def_instr_end())
322 bool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const {
323 use_nodbg_iterator UI = use_nodbg_begin(RegNo);
324 if (UI == use_nodbg_end())
326 return ++UI == use_nodbg_end();
329 /// clearKillFlags - Iterate over all the uses of the given register and
330 /// clear the kill flag from the MachineOperand. This function is used by
331 /// optimization passes which extend register lifetimes and need only
332 /// preserve conservative kill flag information.
333 void MachineRegisterInfo::clearKillFlags(unsigned Reg) const {
334 for (MachineOperand &MO : use_operands(Reg))
338 bool MachineRegisterInfo::isLiveIn(unsigned Reg) const {
339 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
340 if (I->first == Reg || I->second == Reg)
345 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
346 /// corresponding live-in physical register.
347 unsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const {
348 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
349 if (I->second == VReg)
354 /// getLiveInVirtReg - If PReg is a live-in physical register, return the
355 /// corresponding live-in physical register.
356 unsigned MachineRegisterInfo::getLiveInVirtReg(unsigned PReg) const {
357 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
358 if (I->first == PReg)
363 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
364 /// into the given entry block.
366 MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB,
367 const TargetRegisterInfo &TRI,
368 const TargetInstrInfo &TII) {
369 // Emit the copies into the top of the block.
370 for (unsigned i = 0, e = LiveIns.size(); i != e; ++i)
371 if (LiveIns[i].second) {
372 if (use_empty(LiveIns[i].second)) {
373 // The livein has no uses. Drop it.
375 // It would be preferable to have isel avoid creating live-in
376 // records for unused arguments in the first place, but it's
377 // complicated by the debug info code for arguments.
378 LiveIns.erase(LiveIns.begin() + i);
382 BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(),
383 TII.get(TargetOpcode::COPY), LiveIns[i].second)
384 .addReg(LiveIns[i].first);
386 // Add the register to the entry block live-in set.
387 EntryMBB->addLiveIn(LiveIns[i].first);
390 // Add the register to the entry block live-in set.
391 EntryMBB->addLiveIn(LiveIns[i].first);
395 unsigned MachineRegisterInfo::getMaxLaneMaskForVReg(unsigned Reg) const
397 // Lane masks are only defined for vregs.
398 assert(TargetRegisterInfo::isVirtualRegister(Reg));
399 const TargetRegisterClass &TRC = *getRegClass(Reg);
400 return TRC.getLaneMask();
404 void MachineRegisterInfo::dumpUses(unsigned Reg) const {
405 for (MachineInstr &I : use_instructions(Reg))
410 void MachineRegisterInfo::freezeReservedRegs(const MachineFunction &MF) {
411 ReservedRegs = getTargetRegisterInfo()->getReservedRegs(MF);
412 assert(ReservedRegs.size() == getTargetRegisterInfo()->getNumRegs() &&
413 "Invalid ReservedRegs vector from target");
416 bool MachineRegisterInfo::isConstantPhysReg(unsigned PhysReg,
417 const MachineFunction &MF) const {
418 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg));
420 // Check if any overlapping register is modified, or allocatable so it may be
422 for (MCRegAliasIterator AI(PhysReg, getTargetRegisterInfo(), true);
424 if (!def_empty(*AI) || isAllocatable(*AI))
429 /// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the
430 /// specified register as undefined which causes the DBG_VALUE to be
431 /// deleted during LiveDebugVariables analysis.
432 void MachineRegisterInfo::markUsesInDebugValueAsUndef(unsigned Reg) const {
433 // Mark any DBG_VALUE that uses Reg as undef (but don't delete it.)
434 MachineRegisterInfo::use_instr_iterator nextI;
435 for (use_instr_iterator I = use_instr_begin(Reg), E = use_instr_end();
437 nextI = std::next(I); // I is invalidated by the setReg
438 MachineInstr *UseMI = &*I;
439 if (UseMI->isDebugValue())
440 UseMI->getOperand(0).setReg(0U);