1 //===-- lib/Codegen/MachineRegisterInfo.cpp -------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Implementation of the MachineRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/MachineRegisterInfo.h"
15 #include "llvm/CodeGen/MachineInstrBuilder.h"
16 #include "llvm/Target/TargetInstrInfo.h"
17 #include "llvm/Target/TargetMachine.h"
20 MachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI)
21 : TRI(&TRI), IsSSA(true), TracksLiveness(true) {
22 VRegInfo.reserve(256);
23 RegAllocHints.reserve(256);
24 UsedRegUnits.resize(TRI.getNumRegUnits());
25 UsedPhysRegMask.resize(TRI.getNumRegs());
27 // Create the physreg use/def lists.
28 PhysRegUseDefLists = new MachineOperand*[TRI.getNumRegs()];
29 memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*TRI.getNumRegs());
32 MachineRegisterInfo::~MachineRegisterInfo() {
33 delete [] PhysRegUseDefLists;
36 /// setRegClass - Set the register class of the specified virtual register.
39 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) {
40 VRegInfo[Reg].first = RC;
43 const TargetRegisterClass *
44 MachineRegisterInfo::constrainRegClass(unsigned Reg,
45 const TargetRegisterClass *RC,
46 unsigned MinNumRegs) {
47 const TargetRegisterClass *OldRC = getRegClass(Reg);
50 const TargetRegisterClass *NewRC = TRI->getCommonSubClass(OldRC, RC);
51 if (!NewRC || NewRC == OldRC)
53 if (NewRC->getNumRegs() < MinNumRegs)
55 setRegClass(Reg, NewRC);
60 MachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) {
61 const TargetInstrInfo *TII = TM.getInstrInfo();
62 const TargetRegisterClass *OldRC = getRegClass(Reg);
63 const TargetRegisterClass *NewRC = TRI->getLargestLegalSuperClass(OldRC);
65 // Stop early if there is no room to grow.
69 // Accumulate constraints from all uses.
70 for (reg_nodbg_iterator I = reg_nodbg_begin(Reg), E = reg_nodbg_end(); I != E;
72 const TargetRegisterClass *OpRC =
73 I->getRegClassConstraint(I.getOperandNo(), TII, TRI);
74 if (unsigned SubIdx = I.getOperand().getSubReg()) {
76 NewRC = TRI->getMatchingSuperRegClass(NewRC, OpRC, SubIdx);
78 NewRC = TRI->getSubClassWithSubReg(NewRC, SubIdx);
80 NewRC = TRI->getCommonSubClass(NewRC, OpRC);
81 if (!NewRC || NewRC == OldRC)
84 setRegClass(Reg, NewRC);
88 /// createVirtualRegister - Create and return a new virtual register in the
89 /// function with the specified register class.
92 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){
93 assert(RegClass && "Cannot create register without RegClass!");
94 assert(RegClass->isAllocatable() &&
95 "Virtual register RegClass must be allocatable.");
97 // New virtual register number.
98 unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs());
100 VRegInfo[Reg].first = RegClass;
101 RegAllocHints.grow(Reg);
105 /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
106 void MachineRegisterInfo::clearVirtRegs() {
108 for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i)
109 assert(VRegInfo[TargetRegisterInfo::index2VirtReg(i)].second == 0 &&
110 "Vreg use list non-empty still?");
115 /// Add MO to the linked list of operands for its register.
116 void MachineRegisterInfo::addRegOperandToUseList(MachineOperand *MO) {
117 assert(!MO->isOnRegUseList() && "Already on list");
118 MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());
119 MachineOperand *const Head = HeadRef;
121 // Head points to the first list element.
122 // Next is NULL on the last list element.
123 // Prev pointers are circular, so Head->Prev == Last.
125 // Head is NULL for an empty list.
127 MO->Contents.Reg.Prev = MO;
128 MO->Contents.Reg.Next = 0;
132 assert(MO->getReg() == Head->getReg() && "Different regs on the same list!");
134 // Insert MO between Last and Head in the circular Prev chain.
135 MachineOperand *Last = Head->Contents.Reg.Prev;
136 assert(Last && "Inconsistent use list");
137 assert(MO->getReg() == Last->getReg() && "Different regs on the same list!");
138 Head->Contents.Reg.Prev = MO;
139 MO->Contents.Reg.Prev = Last;
141 // Def operands always precede uses. This allows def_iterator to stop early.
142 // Insert def operands at the front, and use operands at the back.
144 // Insert def at the front.
145 MO->Contents.Reg.Next = Head;
148 // Insert use at the end.
149 MO->Contents.Reg.Next = 0;
150 Last->Contents.Reg.Next = MO;
154 /// Remove MO from its use-def list.
155 void MachineRegisterInfo::removeRegOperandFromUseList(MachineOperand *MO) {
156 assert(MO->isOnRegUseList() && "Operand not on use list");
157 MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());
158 MachineOperand *const Head = HeadRef;
159 assert(Head && "List already empty");
161 // Unlink this from the doubly linked list of operands.
162 MachineOperand *Next = MO->Contents.Reg.Next;
163 MachineOperand *Prev = MO->Contents.Reg.Prev;
165 // Prev links are circular, next link is NULL instead of looping back to Head.
169 Prev->Contents.Reg.Next = Next;
171 (Next ? Next : Head)->Contents.Reg.Prev = Prev;
173 MO->Contents.Reg.Prev = 0;
174 MO->Contents.Reg.Next = 0;
177 /// Move NumOps operands from Src to Dst, updating use-def lists as needed.
179 /// The Dst range is assumed to be uninitialized memory. (Or it may contain
180 /// operands that won't be destroyed, which is OK because the MO destructor is
183 /// The Src and Dst ranges may overlap.
184 void MachineRegisterInfo::moveOperands(MachineOperand *Dst,
187 assert(Src != Dst && NumOps && "Noop moveOperands");
189 // Copy backwards if Dst is within the Src range.
191 if (Dst >= Src && Dst < Src + NumOps) {
197 // Copy one operand at a time.
199 new (Dst) MachineOperand(*Src);
201 // Dst takes Src's place in the use-def chain.
203 MachineOperand *&Head = getRegUseDefListHead(Src->getReg());
204 MachineOperand *Prev = Src->Contents.Reg.Prev;
205 MachineOperand *Next = Src->Contents.Reg.Next;
206 assert(Head && "List empty, but operand is chained");
207 assert(Prev && "Operand was not on use-def list");
209 // Prev links are circular, next link is NULL instead of looping back to
214 Prev->Contents.Reg.Next = Dst;
216 // Update Prev pointer. This also works when Src was pointing to itself
217 // in a 1-element list. In that case Head == Dst.
218 (Next ? Next : Head)->Contents.Reg.Prev = Dst;
226 /// replaceRegWith - Replace all instances of FromReg with ToReg in the
227 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
228 /// except that it also changes any definitions of the register as well.
229 void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) {
230 assert(FromReg != ToReg && "Cannot replace a reg with itself");
232 // TODO: This could be more efficient by bulk changing the operands.
233 for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) {
234 MachineOperand &O = I.getOperand();
241 /// getVRegDef - Return the machine instr that defines the specified virtual
242 /// register or null if none is found. This assumes that the code is in SSA
243 /// form, so there should only be one definition.
244 MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const {
245 // Since we are in SSA form, we can use the first definition.
246 def_iterator I = def_begin(Reg);
247 assert((I.atEnd() || llvm::next(I) == def_end()) &&
248 "getVRegDef assumes a single definition or no definition");
249 return !I.atEnd() ? &*I : 0;
252 /// getUniqueVRegDef - Return the unique machine instr that defines the
253 /// specified virtual register or null if none is found. If there are
254 /// multiple definitions or no definition, return null.
255 MachineInstr *MachineRegisterInfo::getUniqueVRegDef(unsigned Reg) const {
256 if (def_empty(Reg)) return 0;
257 def_iterator I = def_begin(Reg);
258 if (llvm::next(I) != def_end())
263 bool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const {
264 use_nodbg_iterator UI = use_nodbg_begin(RegNo);
265 if (UI == use_nodbg_end())
267 return ++UI == use_nodbg_end();
270 /// clearKillFlags - Iterate over all the uses of the given register and
271 /// clear the kill flag from the MachineOperand. This function is used by
272 /// optimization passes which extend register lifetimes and need only
273 /// preserve conservative kill flag information.
274 void MachineRegisterInfo::clearKillFlags(unsigned Reg) const {
275 for (use_iterator UI = use_begin(Reg), UE = use_end(); UI != UE; ++UI)
276 UI.getOperand().setIsKill(false);
279 bool MachineRegisterInfo::isLiveIn(unsigned Reg) const {
280 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
281 if (I->first == Reg || I->second == Reg)
286 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
287 /// corresponding live-in physical register.
288 unsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const {
289 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
290 if (I->second == VReg)
295 /// getLiveInVirtReg - If PReg is a live-in physical register, return the
296 /// corresponding live-in physical register.
297 unsigned MachineRegisterInfo::getLiveInVirtReg(unsigned PReg) const {
298 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
299 if (I->first == PReg)
304 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
305 /// into the given entry block.
307 MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB,
308 const TargetRegisterInfo &TRI,
309 const TargetInstrInfo &TII) {
310 // Emit the copies into the top of the block.
311 for (unsigned i = 0, e = LiveIns.size(); i != e; ++i)
312 if (LiveIns[i].second) {
313 if (use_empty(LiveIns[i].second)) {
314 // The livein has no uses. Drop it.
316 // It would be preferable to have isel avoid creating live-in
317 // records for unused arguments in the first place, but it's
318 // complicated by the debug info code for arguments.
319 LiveIns.erase(LiveIns.begin() + i);
323 BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(),
324 TII.get(TargetOpcode::COPY), LiveIns[i].second)
325 .addReg(LiveIns[i].first);
327 // Add the register to the entry block live-in set.
328 EntryMBB->addLiveIn(LiveIns[i].first);
331 // Add the register to the entry block live-in set.
332 EntryMBB->addLiveIn(LiveIns[i].first);
337 void MachineRegisterInfo::dumpUses(unsigned Reg) const {
338 for (use_iterator I = use_begin(Reg), E = use_end(); I != E; ++I)
339 I.getOperand().getParent()->dump();
343 void MachineRegisterInfo::freezeReservedRegs(const MachineFunction &MF) {
344 ReservedRegs = TRI->getReservedRegs(MF);
345 assert(ReservedRegs.size() == TRI->getNumRegs() &&
346 "Invalid ReservedRegs vector from target");
349 bool MachineRegisterInfo::isConstantPhysReg(unsigned PhysReg,
350 const MachineFunction &MF) const {
351 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg));
353 // Check if any overlapping register is modified, or allocatable so it may be
355 for (MCRegAliasIterator AI(PhysReg, TRI, true); AI.isValid(); ++AI)
356 if (!def_empty(*AI) || isAllocatable(*AI))