1 //===-- lib/Codegen/MachineRegisterInfo.cpp -------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Implementation of the MachineRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/MachineRegisterInfo.h"
15 #include "llvm/CodeGen/MachineInstrBuilder.h"
16 #include "llvm/Target/TargetInstrInfo.h"
17 #include "llvm/Target/TargetMachine.h"
20 MachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI)
21 : TRI(&TRI), IsSSA(true), TracksLiveness(true) {
22 VRegInfo.reserve(256);
23 RegAllocHints.reserve(256);
24 UsedRegUnits.resize(TRI.getNumRegUnits());
25 UsedPhysRegMask.resize(TRI.getNumRegs());
27 // Create the physreg use/def lists.
28 PhysRegUseDefLists = new MachineOperand*[TRI.getNumRegs()];
29 memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*TRI.getNumRegs());
32 MachineRegisterInfo::~MachineRegisterInfo() {
35 for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i)
36 assert(!PhysRegUseDefLists[i] &&
37 "PhysRegUseDefLists has entries after all instructions are deleted");
39 delete [] PhysRegUseDefLists;
42 /// setRegClass - Set the register class of the specified virtual register.
45 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) {
46 VRegInfo[Reg].first = RC;
49 const TargetRegisterClass *
50 MachineRegisterInfo::constrainRegClass(unsigned Reg,
51 const TargetRegisterClass *RC,
52 unsigned MinNumRegs) {
53 const TargetRegisterClass *OldRC = getRegClass(Reg);
56 const TargetRegisterClass *NewRC = TRI->getCommonSubClass(OldRC, RC);
57 if (!NewRC || NewRC == OldRC)
59 if (NewRC->getNumRegs() < MinNumRegs)
61 setRegClass(Reg, NewRC);
66 MachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) {
67 const TargetInstrInfo *TII = TM.getInstrInfo();
68 const TargetRegisterClass *OldRC = getRegClass(Reg);
69 const TargetRegisterClass *NewRC = TRI->getLargestLegalSuperClass(OldRC);
71 // Stop early if there is no room to grow.
75 // Accumulate constraints from all uses.
76 for (reg_nodbg_iterator I = reg_nodbg_begin(Reg), E = reg_nodbg_end(); I != E;
78 const TargetRegisterClass *OpRC =
79 I->getRegClassConstraint(I.getOperandNo(), TII, TRI);
80 if (unsigned SubIdx = I.getOperand().getSubReg()) {
82 NewRC = TRI->getMatchingSuperRegClass(NewRC, OpRC, SubIdx);
84 NewRC = TRI->getSubClassWithSubReg(NewRC, SubIdx);
86 NewRC = TRI->getCommonSubClass(NewRC, OpRC);
87 if (!NewRC || NewRC == OldRC)
90 setRegClass(Reg, NewRC);
94 /// createVirtualRegister - Create and return a new virtual register in the
95 /// function with the specified register class.
98 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){
99 assert(RegClass && "Cannot create register without RegClass!");
100 assert(RegClass->isAllocatable() &&
101 "Virtual register RegClass must be allocatable.");
103 // New virtual register number.
104 unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs());
106 VRegInfo[Reg].first = RegClass;
107 RegAllocHints.grow(Reg);
111 /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
112 void MachineRegisterInfo::clearVirtRegs() {
114 for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i)
115 assert(VRegInfo[TargetRegisterInfo::index2VirtReg(i)].second == 0 &&
116 "Vreg use list non-empty still?");
121 /// Add MO to the linked list of operands for its register.
122 void MachineRegisterInfo::addRegOperandToUseList(MachineOperand *MO) {
123 assert(!MO->isOnRegUseList() && "Already on list");
124 MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());
125 MachineOperand *const Head = HeadRef;
127 // Head points to the first list element.
128 // Next is NULL on the last list element.
129 // Prev pointers are circular, so Head->Prev == Last.
131 // Head is NULL for an empty list.
133 MO->Contents.Reg.Prev = MO;
134 MO->Contents.Reg.Next = 0;
138 assert(MO->getReg() == Head->getReg() && "Different regs on the same list!");
140 // Insert MO between Last and Head in the circular Prev chain.
141 MachineOperand *Last = Head->Contents.Reg.Prev;
142 assert(Last && "Inconsistent use list");
143 assert(MO->getReg() == Last->getReg() && "Different regs on the same list!");
144 Head->Contents.Reg.Prev = MO;
145 MO->Contents.Reg.Prev = Last;
147 // Def operands always precede uses. This allows def_iterator to stop early.
148 // Insert def operands at the front, and use operands at the back.
150 // Insert def at the front.
151 MO->Contents.Reg.Next = Head;
154 // Insert use at the end.
155 MO->Contents.Reg.Next = 0;
156 Last->Contents.Reg.Next = MO;
160 /// Remove MO from its use-def list.
161 void MachineRegisterInfo::removeRegOperandFromUseList(MachineOperand *MO) {
162 assert(MO->isOnRegUseList() && "Operand not on use list");
163 MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());
164 MachineOperand *const Head = HeadRef;
165 assert(Head && "List already empty");
167 // Unlink this from the doubly linked list of operands.
168 MachineOperand *Next = MO->Contents.Reg.Next;
169 MachineOperand *Prev = MO->Contents.Reg.Prev;
171 // Prev links are circular, next link is NULL instead of looping back to Head.
175 Prev->Contents.Reg.Next = Next;
177 (Next ? Next : Head)->Contents.Reg.Prev = Prev;
179 MO->Contents.Reg.Prev = 0;
180 MO->Contents.Reg.Next = 0;
183 /// Move NumOps operands from Src to Dst, updating use-def lists as needed.
185 /// The Dst range is assumed to be uninitialized memory. (Or it may contain
186 /// operands that won't be destroyed, which is OK because the MO destructor is
189 /// The Src and Dst ranges may overlap.
190 void MachineRegisterInfo::moveOperands(MachineOperand *Dst,
193 assert(Src != Dst && NumOps && "Noop moveOperands");
195 // Copy backwards if Dst is within the Src range.
197 if (Dst >= Src && Dst < Src + NumOps) {
203 // Copy one operand at a time.
205 new (Dst) MachineOperand(*Src);
207 // Dst takes Src's place in the use-def chain.
209 MachineOperand *&Head = getRegUseDefListHead(Src->getReg());
210 MachineOperand *Prev = Src->Contents.Reg.Prev;
211 MachineOperand *Next = Src->Contents.Reg.Next;
212 assert(Head && "List empty, but operand is chained");
213 assert(Prev && "Operand was not on use-def list");
215 // Prev links are circular, next link is NULL instead of looping back to
220 Prev->Contents.Reg.Next = Dst;
222 // Update Prev pointer. This also works when Src was pointing to itself
223 // in a 1-element list. In that case Head == Dst.
224 (Next ? Next : Head)->Contents.Reg.Prev = Dst;
232 /// replaceRegWith - Replace all instances of FromReg with ToReg in the
233 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
234 /// except that it also changes any definitions of the register as well.
235 void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) {
236 assert(FromReg != ToReg && "Cannot replace a reg with itself");
238 // TODO: This could be more efficient by bulk changing the operands.
239 for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) {
240 MachineOperand &O = I.getOperand();
247 /// getVRegDef - Return the machine instr that defines the specified virtual
248 /// register or null if none is found. This assumes that the code is in SSA
249 /// form, so there should only be one definition.
250 MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const {
251 // Since we are in SSA form, we can use the first definition.
252 def_iterator I = def_begin(Reg);
253 assert((I.atEnd() || llvm::next(I) == def_end()) &&
254 "getVRegDef assumes a single definition or no definition");
255 return !I.atEnd() ? &*I : 0;
258 /// getUniqueVRegDef - Return the unique machine instr that defines the
259 /// specified virtual register or null if none is found. If there are
260 /// multiple definitions or no definition, return null.
261 MachineInstr *MachineRegisterInfo::getUniqueVRegDef(unsigned Reg) const {
262 if (def_empty(Reg)) return 0;
263 def_iterator I = def_begin(Reg);
264 if (llvm::next(I) != def_end())
269 bool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const {
270 use_nodbg_iterator UI = use_nodbg_begin(RegNo);
271 if (UI == use_nodbg_end())
273 return ++UI == use_nodbg_end();
276 /// clearKillFlags - Iterate over all the uses of the given register and
277 /// clear the kill flag from the MachineOperand. This function is used by
278 /// optimization passes which extend register lifetimes and need only
279 /// preserve conservative kill flag information.
280 void MachineRegisterInfo::clearKillFlags(unsigned Reg) const {
281 for (use_iterator UI = use_begin(Reg), UE = use_end(); UI != UE; ++UI)
282 UI.getOperand().setIsKill(false);
285 bool MachineRegisterInfo::isLiveIn(unsigned Reg) const {
286 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
287 if (I->first == Reg || I->second == Reg)
292 bool MachineRegisterInfo::isLiveOut(unsigned Reg) const {
293 for (liveout_iterator I = liveout_begin(), E = liveout_end(); I != E; ++I)
299 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
300 /// corresponding live-in physical register.
301 unsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const {
302 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
303 if (I->second == VReg)
308 /// getLiveInVirtReg - If PReg is a live-in physical register, return the
309 /// corresponding live-in physical register.
310 unsigned MachineRegisterInfo::getLiveInVirtReg(unsigned PReg) const {
311 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
312 if (I->first == PReg)
317 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
318 /// into the given entry block.
320 MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB,
321 const TargetRegisterInfo &TRI,
322 const TargetInstrInfo &TII) {
323 // Emit the copies into the top of the block.
324 for (unsigned i = 0, e = LiveIns.size(); i != e; ++i)
325 if (LiveIns[i].second) {
326 if (use_empty(LiveIns[i].second)) {
327 // The livein has no uses. Drop it.
329 // It would be preferable to have isel avoid creating live-in
330 // records for unused arguments in the first place, but it's
331 // complicated by the debug info code for arguments.
332 LiveIns.erase(LiveIns.begin() + i);
336 BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(),
337 TII.get(TargetOpcode::COPY), LiveIns[i].second)
338 .addReg(LiveIns[i].first);
340 // Add the register to the entry block live-in set.
341 EntryMBB->addLiveIn(LiveIns[i].first);
344 // Add the register to the entry block live-in set.
345 EntryMBB->addLiveIn(LiveIns[i].first);
350 void MachineRegisterInfo::dumpUses(unsigned Reg) const {
351 for (use_iterator I = use_begin(Reg), E = use_end(); I != E; ++I)
352 I.getOperand().getParent()->dump();
356 void MachineRegisterInfo::freezeReservedRegs(const MachineFunction &MF) {
357 ReservedRegs = TRI->getReservedRegs(MF);
358 assert(ReservedRegs.size() == TRI->getNumRegs() &&
359 "Invalid ReservedRegs vector from target");
362 bool MachineRegisterInfo::isConstantPhysReg(unsigned PhysReg,
363 const MachineFunction &MF) const {
364 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg));
366 // Check if any overlapping register is modified, or allocatable so it may be
368 for (MCRegAliasIterator AI(PhysReg, TRI, true); AI.isValid(); ++AI)
369 if (!def_empty(*AI) || isAllocatable(*AI))