1 //===-- lib/Codegen/MachineRegisterInfo.cpp -------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Implementation of the MachineRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/MachineRegisterInfo.h"
15 #include "llvm/CodeGen/MachineInstrBuilder.h"
16 #include "llvm/Target/TargetInstrInfo.h"
17 #include "llvm/Support/CommandLine.h"
20 MachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI)
22 VRegInfo.reserve(256);
23 RegAllocHints.reserve(256);
24 UsedPhysRegs.resize(TRI.getNumRegs());
26 // Create the physreg use/def lists.
27 PhysRegUseDefLists = new MachineOperand*[TRI.getNumRegs()];
28 memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*TRI.getNumRegs());
31 MachineRegisterInfo::~MachineRegisterInfo() {
33 for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i)
34 assert(VRegInfo[TargetRegisterInfo::index2VirtReg(i)].second == 0 &&
35 "Vreg use list non-empty still?");
36 for (unsigned i = 0, e = UsedPhysRegs.size(); i != e; ++i)
37 assert(!PhysRegUseDefLists[i] &&
38 "PhysRegUseDefLists has entries after all instructions are deleted");
40 delete [] PhysRegUseDefLists;
43 /// setRegClass - Set the register class of the specified virtual register.
46 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) {
47 VRegInfo[Reg].first = RC;
50 const TargetRegisterClass *
51 MachineRegisterInfo::constrainRegClass(unsigned Reg,
52 const TargetRegisterClass *RC) {
53 const TargetRegisterClass *OldRC = getRegClass(Reg);
56 const TargetRegisterClass *NewRC = getCommonSubClass(OldRC, RC);
60 setRegClass(Reg, NewRC);
64 /// createVirtualRegister - Create and return a new virtual register in the
65 /// function with the specified register class.
68 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){
69 assert(RegClass && "Cannot create register without RegClass!");
70 assert(RegClass->isAllocatable() &&
71 "Virtual register RegClass must be allocatable.");
73 // New virtual register number.
74 unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs());
76 // Add a reg, but keep track of whether the vector reallocated or not.
77 const unsigned FirstVirtReg = TargetRegisterInfo::index2VirtReg(0);
78 void *ArrayBase = getNumVirtRegs() == 0 ? 0 : &VRegInfo[FirstVirtReg];
80 VRegInfo[Reg].first = RegClass;
81 RegAllocHints.grow(Reg);
83 if (ArrayBase && &VRegInfo[FirstVirtReg] != ArrayBase)
84 // The vector reallocated, handle this now.
85 HandleVRegListReallocation();
89 /// HandleVRegListReallocation - We just added a virtual register to the
90 /// VRegInfo info list and it reallocated. Update the use/def lists info
92 void MachineRegisterInfo::HandleVRegListReallocation() {
93 // The back pointers for the vreg lists point into the previous vector.
94 // Update them to point to their correct slots.
95 for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) {
96 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
97 MachineOperand *List = VRegInfo[Reg].second;
99 // Update the back-pointer to be accurate once more.
100 List->Contents.Reg.Prev = &VRegInfo[Reg].second;
104 /// replaceRegWith - Replace all instances of FromReg with ToReg in the
105 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
106 /// except that it also changes any definitions of the register as well.
107 void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) {
108 assert(FromReg != ToReg && "Cannot replace a reg with itself");
110 // TODO: This could be more efficient by bulk changing the operands.
111 for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) {
112 MachineOperand &O = I.getOperand();
119 /// getVRegDef - Return the machine instr that defines the specified virtual
120 /// register or null if none is found. This assumes that the code is in SSA
121 /// form, so there should only be one definition.
122 MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const {
123 // Since we are in SSA form, we can use the first definition.
125 return &*def_begin(Reg);
129 bool MachineRegisterInfo::hasOneUse(unsigned RegNo) const {
130 use_iterator UI = use_begin(RegNo);
133 return ++UI == use_end();
136 bool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const {
137 use_nodbg_iterator UI = use_nodbg_begin(RegNo);
138 if (UI == use_nodbg_end())
140 return ++UI == use_nodbg_end();
143 /// clearKillFlags - Iterate over all the uses of the given register and
144 /// clear the kill flag from the MachineOperand. This function is used by
145 /// optimization passes which extend register lifetimes and need only
146 /// preserve conservative kill flag information.
147 void MachineRegisterInfo::clearKillFlags(unsigned Reg) const {
148 for (use_iterator UI = use_begin(Reg), UE = use_end(); UI != UE; ++UI)
149 UI.getOperand().setIsKill(false);
152 bool MachineRegisterInfo::isLiveIn(unsigned Reg) const {
153 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
154 if (I->first == Reg || I->second == Reg)
159 bool MachineRegisterInfo::isLiveOut(unsigned Reg) const {
160 for (liveout_iterator I = liveout_begin(), E = liveout_end(); I != E; ++I)
166 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
167 /// corresponding live-in physical register.
168 unsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const {
169 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
170 if (I->second == VReg)
175 /// getLiveInVirtReg - If PReg is a live-in physical register, return the
176 /// corresponding live-in physical register.
177 unsigned MachineRegisterInfo::getLiveInVirtReg(unsigned PReg) const {
178 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
179 if (I->first == PReg)
184 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
185 /// into the given entry block.
187 MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB,
188 const TargetRegisterInfo &TRI,
189 const TargetInstrInfo &TII) {
190 // Emit the copies into the top of the block.
191 for (unsigned i = 0, e = LiveIns.size(); i != e; ++i)
192 if (LiveIns[i].second) {
193 if (use_empty(LiveIns[i].second)) {
194 // The livein has no uses. Drop it.
196 // It would be preferable to have isel avoid creating live-in
197 // records for unused arguments in the first place, but it's
198 // complicated by the debug info code for arguments.
199 LiveIns.erase(LiveIns.begin() + i);
203 BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(),
204 TII.get(TargetOpcode::COPY), LiveIns[i].second)
205 .addReg(LiveIns[i].first);
207 // Add the register to the entry block live-in set.
208 EntryMBB->addLiveIn(LiveIns[i].first);
211 // Add the register to the entry block live-in set.
212 EntryMBB->addLiveIn(LiveIns[i].first);
216 void MachineRegisterInfo::closePhysRegsUsed(const TargetRegisterInfo &TRI) {
217 for (int i = UsedPhysRegs.find_first(); i >= 0;
218 i = UsedPhysRegs.find_next(i))
219 for (const unsigned *SS = TRI.getSubRegisters(i);
220 unsigned SubReg = *SS; ++SS)
221 if (SubReg > unsigned(i))
222 UsedPhysRegs.set(SubReg);
226 void MachineRegisterInfo::dumpUses(unsigned Reg) const {
227 for (use_iterator I = use_begin(Reg), E = use_end(); I != E; ++I)
228 I.getOperand().getParent()->dump();