1 //===-- MachineLICM.cpp - Machine Loop Invariant Code Motion Pass ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass performs loop invariant code motion on machine instructions. We
11 // attempt to remove as much code from the body of a loop as possible.
13 // This pass does not attempt to throttle itself to limit register pressure.
14 // The register allocation phases are expected to perform rematerialization
15 // to recover when register pressure is high.
17 // This pass is not intended to be a replacement or a complete alternative
18 // for the LLVM-IR-level LICM pass. It is only designed to hoist simple
19 // constructs that are not exposed before lowering and instruction selection.
21 //===----------------------------------------------------------------------===//
23 #define DEBUG_TYPE "machine-licm"
24 #include "llvm/CodeGen/Passes.h"
25 #include "llvm/CodeGen/MachineDominators.h"
26 #include "llvm/CodeGen/MachineLoopInfo.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/Target/TargetRegisterInfo.h"
29 #include "llvm/Target/TargetInstrInfo.h"
30 #include "llvm/Target/TargetMachine.h"
31 #include "llvm/ADT/DenseMap.h"
32 #include "llvm/ADT/Statistic.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/Compiler.h"
35 #include "llvm/Support/Debug.h"
39 STATISTIC(NumHoisted, "Number of machine instructions hoisted out of loops");
40 STATISTIC(NumCSEed, "Number of hoisted machine instructions CSEed");
43 class VISIBILITY_HIDDEN MachineLICM : public MachineFunctionPass {
44 const TargetMachine *TM;
45 const TargetInstrInfo *TII;
47 // Various analyses that we use...
48 MachineLoopInfo *LI; // Current MachineLoopInfo
49 MachineDominatorTree *DT; // Machine dominator tree for the cur loop
50 MachineRegisterInfo *RegInfo; // Machine register information
52 // State that is updated as we process loops
53 bool Changed; // True if a loop is changed.
54 MachineLoop *CurLoop; // The current loop we are working on.
55 MachineBasicBlock *CurPreheader; // The preheader for CurLoop.
57 // For each BB and opcode pair, keep a list of hoisted instructions.
58 DenseMap<std::pair<unsigned, unsigned>,
59 std::vector<const MachineInstr*> > CSEMap;
61 static char ID; // Pass identification, replacement for typeid
62 MachineLICM() : MachineFunctionPass(&ID) {}
64 virtual bool runOnMachineFunction(MachineFunction &MF);
66 const char *getPassName() const { return "Machine Instruction LICM"; }
68 // FIXME: Loop preheaders?
69 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
71 AU.addRequired<MachineLoopInfo>();
72 AU.addRequired<MachineDominatorTree>();
73 AU.addPreserved<MachineLoopInfo>();
74 AU.addPreserved<MachineDominatorTree>();
75 MachineFunctionPass::getAnalysisUsage(AU);
78 virtual void releaseMemory() {
83 /// IsLoopInvariantInst - Returns true if the instruction is loop
84 /// invariant. I.e., all virtual register operands are defined outside of
85 /// the loop, physical registers aren't accessed (explicitly or implicitly),
86 /// and the instruction is hoistable.
88 bool IsLoopInvariantInst(MachineInstr &I);
90 /// IsProfitableToHoist - Return true if it is potentially profitable to
91 /// hoist the given loop invariant.
92 bool IsProfitableToHoist(MachineInstr &MI);
94 /// HoistRegion - Walk the specified region of the CFG (defined by all
95 /// blocks dominated by the specified block, and that are in the current
96 /// loop) in depth first order w.r.t the DominatorTree. This allows us to
97 /// visit definitions before uses, allowing us to hoist a loop body in one
98 /// pass without iteration.
100 void HoistRegion(MachineDomTreeNode *N);
102 /// Hoist - When an instruction is found to only use loop invariant operands
103 /// that is safe to hoist, this instruction is called to do the dirty work.
105 void Hoist(MachineInstr &MI);
107 } // end anonymous namespace
109 char MachineLICM::ID = 0;
110 static RegisterPass<MachineLICM>
111 X("machinelicm", "Machine Loop Invariant Code Motion");
113 FunctionPass *llvm::createMachineLICMPass() { return new MachineLICM(); }
115 /// LoopIsOuterMostWithPreheader - Test if the given loop is the outer-most
116 /// loop that has a preheader.
117 static bool LoopIsOuterMostWithPreheader(MachineLoop *CurLoop) {
118 for (MachineLoop *L = CurLoop->getParentLoop(); L; L = L->getParentLoop())
119 if (L->getLoopPreheader())
124 /// Hoist expressions out of the specified loop. Note, alias info for inner loop
125 /// is not preserved so it is not a good idea to run LICM multiple times on one
128 bool MachineLICM::runOnMachineFunction(MachineFunction &MF) {
129 const Function *F = MF.getFunction();
130 if (F->hasFnAttr(Attribute::OptimizeForSize))
133 DOUT << "******** Machine LICM ********\n";
136 TM = &MF.getTarget();
137 TII = TM->getInstrInfo();
138 RegInfo = &MF.getRegInfo();
140 // Get our Loop information...
141 LI = &getAnalysis<MachineLoopInfo>();
142 DT = &getAnalysis<MachineDominatorTree>();
144 for (MachineLoopInfo::iterator
145 I = LI->begin(), E = LI->end(); I != E; ++I) {
148 // Only visit outer-most preheader-sporting loops.
149 if (!LoopIsOuterMostWithPreheader(CurLoop))
152 // Determine the block to which to hoist instructions. If we can't find a
153 // suitable loop preheader, we can't do any hoisting.
155 // FIXME: We are only hoisting if the basic block coming into this loop
156 // has only one successor. This isn't the case in general because we haven't
157 // broken critical edges or added preheaders.
158 CurPreheader = CurLoop->getLoopPreheader();
162 HoistRegion(DT->getNode(CurLoop->getHeader()));
168 /// HoistRegion - Walk the specified region of the CFG (defined by all blocks
169 /// dominated by the specified block, and that are in the current loop) in depth
170 /// first order w.r.t the DominatorTree. This allows us to visit definitions
171 /// before uses, allowing us to hoist a loop body in one pass without iteration.
173 void MachineLICM::HoistRegion(MachineDomTreeNode *N) {
174 assert(N != 0 && "Null dominator tree node?");
175 MachineBasicBlock *BB = N->getBlock();
177 // If this subregion is not in the top level loop at all, exit.
178 if (!CurLoop->contains(BB)) return;
180 for (MachineBasicBlock::iterator
181 MII = BB->begin(), E = BB->end(); MII != E; ) {
182 MachineBasicBlock::iterator NextMII = MII; ++NextMII;
183 MachineInstr &MI = *MII;
190 const std::vector<MachineDomTreeNode*> &Children = N->getChildren();
192 for (unsigned I = 0, E = Children.size(); I != E; ++I)
193 HoistRegion(Children[I]);
196 /// IsLoopInvariantInst - Returns true if the instruction is loop
197 /// invariant. I.e., all virtual register operands are defined outside of the
198 /// loop, physical registers aren't accessed explicitly, and there are no side
199 /// effects that aren't captured by the operands or other flags.
201 bool MachineLICM::IsLoopInvariantInst(MachineInstr &I) {
202 const TargetInstrDesc &TID = I.getDesc();
204 // Ignore stuff that we obviously can't hoist.
205 if (TID.mayStore() || TID.isCall() || TID.isTerminator() ||
206 TID.hasUnmodeledSideEffects())
210 // Okay, this instruction does a load. As a refinement, we allow the target
211 // to decide whether the loaded value is actually a constant. If so, we can
212 // actually use it as a load.
213 if (!TII->isInvariantLoad(&I))
214 // FIXME: we should be able to sink loads with no other side effects if
215 // there is nothing that can change memory from here until the end of
216 // block. This is a trivial form of alias analysis.
221 DOUT << "--- Checking if we can hoist " << I;
222 if (I.getDesc().getImplicitUses()) {
223 DOUT << " * Instruction has implicit uses:\n";
225 const TargetRegisterInfo *TRI = TM->getRegisterInfo();
226 for (const unsigned *ImpUses = I.getDesc().getImplicitUses();
228 DOUT << " -> " << TRI->getName(*ImpUses) << "\n";
231 if (I.getDesc().getImplicitDefs()) {
232 DOUT << " * Instruction has implicit defines:\n";
234 const TargetRegisterInfo *TRI = TM->getRegisterInfo();
235 for (const unsigned *ImpDefs = I.getDesc().getImplicitDefs();
237 DOUT << " -> " << TRI->getName(*ImpDefs) << "\n";
241 if (I.getDesc().getImplicitDefs() || I.getDesc().getImplicitUses()) {
242 DOUT << "Cannot hoist with implicit defines or uses\n";
246 // The instruction is loop invariant if all of its operands are.
247 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
248 const MachineOperand &MO = I.getOperand(i);
253 unsigned Reg = MO.getReg();
254 if (Reg == 0) continue;
256 // Don't hoist an instruction that uses or defines a physical register.
257 if (TargetRegisterInfo::isPhysicalRegister(Reg))
263 assert(RegInfo->getVRegDef(Reg) &&
264 "Machine instr not mapped for this vreg?!");
266 // If the loop contains the definition of an operand, then the instruction
267 // isn't loop invariant.
268 if (CurLoop->contains(RegInfo->getVRegDef(Reg)->getParent()))
272 // If we got this far, the instruction is loop invariant!
277 /// HasPHIUses - Return true if the specified register has any PHI use.
278 static bool HasPHIUses(unsigned Reg, MachineRegisterInfo *RegInfo) {
279 for (MachineRegisterInfo::use_iterator UI = RegInfo->use_begin(Reg),
280 UE = RegInfo->use_end(); UI != UE; ++UI) {
281 MachineInstr *UseMI = &*UI;
282 if (UseMI->getOpcode() == TargetInstrInfo::PHI)
288 /// IsProfitableToHoist - Return true if it is potentially profitable to hoist
289 /// the given loop invariant.
290 bool MachineLICM::IsProfitableToHoist(MachineInstr &MI) {
291 const TargetInstrDesc &TID = MI.getDesc();
293 // FIXME: For now, only hoist re-materilizable instructions. LICM will
294 // increase register pressure. We want to make sure it doesn't increase
296 if (!TID.mayLoad() && (!TID.isRematerializable() ||
297 !TII->isTriviallyReMaterializable(&MI)))
300 // If result(s) of this instruction is used by PHIs, then don't hoist it.
301 // The presence of joins makes it difficult for current register allocator
302 // implementation to perform remat.
303 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
304 const MachineOperand &MO = MI.getOperand(i);
305 if (!MO.isReg() || !MO.isDef())
307 if (HasPHIUses(MO.getReg(), RegInfo))
314 static const MachineInstr *LookForDuplicate(const MachineInstr *MI,
315 std::vector<const MachineInstr*> &PrevMIs) {
316 unsigned NumOps = MI->getNumOperands();
317 for (unsigned i = 0, e = PrevMIs.size(); i != e; ++i) {
318 const MachineInstr *PrevMI = PrevMIs[i];
319 unsigned NumOps2 = PrevMI->getNumOperands();
320 if (NumOps != NumOps2)
323 for (unsigned j = 0; j != NumOps; ++j) {
324 const MachineOperand &MO = MI->getOperand(j);
325 if (MO.isReg() && MO.isDef())
327 if (!MO.isIdenticalTo(PrevMI->getOperand(j))) {
338 /// Hoist - When an instruction is found to use only loop invariant operands
339 /// that are safe to hoist, this instruction is called to do the dirty work.
341 void MachineLICM::Hoist(MachineInstr &MI) {
342 if (!IsLoopInvariantInst(MI)) return;
343 if (!IsProfitableToHoist(MI)) return;
345 // Now move the instructions to the predecessor, inserting it before any
346 // terminator instructions.
348 DOUT << "Hoisting " << MI;
349 if (CurPreheader->getBasicBlock())
350 DOUT << " to MachineBasicBlock "
351 << CurPreheader->getBasicBlock()->getName();
352 if (MI.getParent()->getBasicBlock())
353 DOUT << " from MachineBasicBlock "
354 << MI.getParent()->getBasicBlock()->getName();
358 // Look for opportunity to CSE the hoisted instruction.
359 std::pair<unsigned, unsigned> BBOpcPair =
360 std::make_pair(CurPreheader->getNumber(), MI.getOpcode());
361 DenseMap<std::pair<unsigned, unsigned>,
362 std::vector<const MachineInstr*> >::iterator CI = CSEMap.find(BBOpcPair);
363 bool DoneCSE = false;
364 if (CI != CSEMap.end()) {
365 const MachineInstr *Dup = LookForDuplicate(&MI, CI->second);
367 DOUT << "CSEing " << MI;
368 DOUT << " with " << *Dup;
369 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
370 const MachineOperand &MO = MI.getOperand(i);
371 if (MO.isReg() && MO.isDef())
372 RegInfo->replaceRegWith(MO.getReg(), Dup->getOperand(i).getReg());
374 MI.eraseFromParent();
380 // Otherwise, splice the instruction to the preheader.
382 CurPreheader->splice(CurPreheader->getFirstTerminator(),
383 MI.getParent(), &MI);
384 // Add to the CSE map.
385 if (CI != CSEMap.end())
386 CI->second.push_back(&MI);
388 std::vector<const MachineInstr*> CSEMIs;
389 CSEMIs.push_back(&MI);
390 CSEMap.insert(std::make_pair(BBOpcPair, CSEMIs));