1 //===-- MachineLICM.cpp - Machine Loop Invariant Code Motion Pass ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Bill Wendling and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass performs loop invariant code motion on machine instructions. We
11 // attempt to remove as much code from the body of a loop as possible.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "machine-licm"
16 #include "llvm/ADT/IndexedMap.h"
17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/ADT/Statistic.h"
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/MachineDominators.h"
21 #include "llvm/CodeGen/MachineInstr.h"
22 #include "llvm/CodeGen/MachineLoopInfo.h"
23 #include "llvm/CodeGen/Passes.h"
24 #include "llvm/Target/TargetInstrInfo.h"
25 #include "llvm/Support/CFG.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Support/Compiler.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Target/MRegisterInfo.h"
30 #include "llvm/Target/TargetMachine.h"
35 // Hidden options to help debugging
37 PerformLICM("machine-licm",
38 cl::init(false), cl::Hidden,
39 cl::desc("Perform loop-invariant code motion on machine code"));
42 STATISTIC(NumHoisted, "Number of machine instructions hoisted out of loops");
45 class VISIBILITY_HIDDEN MachineLICM : public MachineFunctionPass {
46 MachineFunction *CurMF;// Current MachineFunction
48 // Various analyses that we use...
49 MachineLoopInfo *LI; // Current MachineLoopInfo
50 MachineDominatorTree *DT; // Machine dominator tree for the current Loop
52 const TargetInstrInfo *TII;
54 // State that is updated as we process loops
55 bool Changed; // True if a loop is changed.
56 MachineLoop *CurLoop; // The current loop we are working on.
58 // Map the def of a virtual register to the machine instruction.
59 IndexedMap<const MachineInstr*, VirtReg2IndexFunctor> VRegDefs;
61 static char ID; // Pass identification, replacement for typeid
62 MachineLICM() : MachineFunctionPass((intptr_t)&ID) {}
64 virtual bool runOnMachineFunction(MachineFunction &MF);
66 /// FIXME: Loop preheaders?
68 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
70 AU.addRequired<MachineLoopInfo>();
71 AU.addRequired<MachineDominatorTree>();
74 /// VisitAllLoops - Visit all of the loops in depth first order and try to
75 /// hoist invariant instructions from them.
77 void VisitAllLoops(MachineLoop *L) {
78 const std::vector<MachineLoop*> &SubLoops = L->getSubLoops();
80 for (MachineLoop::iterator
81 I = SubLoops.begin(), E = SubLoops.end(); I != E; ++I) {
84 // Traverse the body of the loop in depth first order on the dominator
85 // tree so that we are guaranteed to see definitions before we see uses.
87 HoistRegion(DT->getNode(ML->getHeader()));
90 HoistRegion(DT->getNode(L->getHeader()));
93 /// MapVirtualRegisterDefs - Create a map of which machine instruction
94 /// defines a virtual register.
96 void MapVirtualRegisterDefs();
98 /// IsInSubLoop - A little predicate that returns true if the specified
99 /// basic block is in a subloop of the current one, not the current one
102 bool IsInSubLoop(MachineBasicBlock *BB) {
103 assert(CurLoop->contains(BB) && "Only valid if BB is IN the loop");
104 return LI->getLoopFor(BB) != CurLoop;
107 /// CanHoistInst - Checks that this instructions is one that can be hoisted
108 /// out of the loop. I.e., it has no side effects, isn't a control flow
111 bool CanHoistInst(MachineInstr &I) const {
112 const TargetInstrDescriptor *TID = I.getInstrDescriptor();
114 // Don't hoist if this instruction implicitly reads physical registers.
115 if (TID->ImplicitUses) return false;
117 MachineOpCode Opcode = TID->Opcode;
118 return TII->isTriviallyReMaterializable(&I) &&
119 // FIXME: Below necessary?
120 !(TII->isReturn(Opcode) ||
121 TII->isTerminatorInstr(Opcode) ||
122 TII->isBranch(Opcode) ||
123 TII->isIndirectBranch(Opcode) ||
124 TII->isBarrier(Opcode) ||
125 TII->isCall(Opcode) ||
126 TII->isLoad(Opcode) || // TODO: Do loads and stores.
127 TII->isStore(Opcode));
130 /// IsLoopInvariantInst - Returns true if the instruction is loop
131 /// invariant. I.e., all virtual register operands are defined outside of
132 /// the loop, physical registers aren't accessed (explicitly or implicitly),
133 /// and the instruction is hoistable.
135 bool IsLoopInvariantInst(MachineInstr &I);
137 /// FindPredecessors - Get all of the predecessors of the loop that are not
140 void FindPredecessors(std::vector<MachineBasicBlock*> &Preds) {
141 const MachineBasicBlock *Header = CurLoop->getHeader();
143 for (MachineBasicBlock::const_pred_iterator
144 I = Header->pred_begin(), E = Header->pred_end(); I != E; ++I)
145 if (!CurLoop->contains(*I))
149 /// MoveInstToEndOfBlock - Moves the machine instruction to the bottom of
150 /// the predecessor basic block (but before the terminator instructions).
152 void MoveInstToEndOfBlock(MachineBasicBlock *MBB, MachineInstr *MI) {
153 MachineBasicBlock::iterator Iter = MBB->getFirstTerminator();
154 MBB->insert(Iter, MI);
158 /// HoistRegion - Walk the specified region of the CFG (defined by all
159 /// blocks dominated by the specified block, and that are in the current
160 /// loop) in depth first order w.r.t the DominatorTree. This allows us to
161 /// visit definitions before uses, allowing us to hoist a loop body in one
162 /// pass without iteration.
164 void HoistRegion(MachineDomTreeNode *N);
166 /// Hoist - When an instruction is found to only use loop invariant operands
167 /// that is safe to hoist, this instruction is called to do the dirty work.
169 void Hoist(MachineInstr &MI);
172 char MachineLICM::ID = 0;
173 RegisterPass<MachineLICM> X("machine-licm",
174 "Machine Loop Invariant Code Motion");
175 } // end anonymous namespace
177 FunctionPass *llvm::createMachineLICMPass() { return new MachineLICM(); }
179 /// Hoist expressions out of the specified loop. Note, alias info for inner loop
180 /// is not preserved so it is not a good idea to run LICM multiple times on one
183 bool MachineLICM::runOnMachineFunction(MachineFunction &MF) {
184 if (!PerformLICM) return false; // For debugging.
188 TII = CurMF->getTarget().getInstrInfo();
190 // Get our Loop information...
191 LI = &getAnalysis<MachineLoopInfo>();
192 DT = &getAnalysis<MachineDominatorTree>();
194 MapVirtualRegisterDefs();
196 for (MachineLoopInfo::iterator
197 I = LI->begin(), E = LI->end(); I != E; ++I) {
201 // Visit all of the instructions of the loop. We want to visit the subloops
202 // first, though, so that we can hoist their invariants first into their
203 // containing loop before we process that loop.
210 /// MapVirtualRegisterDefs - Create a map of which machine instruction defines a
211 /// virtual register.
213 void MachineLICM::MapVirtualRegisterDefs() {
214 for (MachineFunction::const_iterator
215 I = CurMF->begin(), E = CurMF->end(); I != E; ++I) {
216 const MachineBasicBlock &MBB = *I;
218 for (MachineBasicBlock::const_iterator
219 II = MBB.begin(), IE = MBB.end(); II != IE; ++II) {
220 const MachineInstr &MI = *II;
222 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
223 const MachineOperand &MO = MI.getOperand(i);
225 if (MO.isRegister() && MO.isDef() &&
226 MRegisterInfo::isVirtualRegister(MO.getReg()))
227 VRegDefs[MO.getReg()] = &MI;
233 /// HoistRegion - Walk the specified region of the CFG (defined by all blocks
234 /// dominated by the specified block, and that are in the current loop) in depth
235 /// first order w.r.t the DominatorTree. This allows us to visit definitions
236 /// before uses, allowing us to hoist a loop body in one pass without iteration.
238 void MachineLICM::HoistRegion(MachineDomTreeNode *N) {
239 assert(N != 0 && "Null dominator tree node?");
240 MachineBasicBlock *BB = N->getBlock();
242 // If this subregion is not in the top level loop at all, exit.
243 if (!CurLoop->contains(BB)) return;
245 // Only need to process the contents of this block if it is not part of a
246 // subloop (which would already have been processed).
247 if (!IsInSubLoop(BB))
248 for (MachineBasicBlock::iterator
249 I = BB->begin(), E = BB->end(); I != E; ) {
250 MachineInstr &MI = *I++;
252 // Try hoisting the instruction out of the loop. We can only do this if
253 // all of the operands of the instruction are loop invariant and if it is
254 // safe to hoist the instruction.
258 const std::vector<MachineDomTreeNode*> &Children = N->getChildren();
260 for (unsigned I = 0, E = Children.size(); I != E; ++I)
261 HoistRegion(Children[I]);
264 /// IsLoopInvariantInst - Returns true if the instruction is loop
265 /// invariant. I.e., all virtual register operands are defined outside of the
266 /// loop, physical registers aren't accessed (explicitly or implicitly), and the
267 /// instruction is hoistable.
269 bool MachineLICM::IsLoopInvariantInst(MachineInstr &I) {
270 if (!CanHoistInst(I)) return false;
272 // The instruction is loop invariant if all of its operands are loop-invariant
273 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
274 const MachineOperand &MO = I.getOperand(i);
276 if (!MO.isRegister() || !MO.isUse())
279 unsigned Reg = MO.getReg();
281 // Don't hoist instructions that access physical registers.
282 if (!MRegisterInfo::isVirtualRegister(Reg))
285 assert(VRegDefs[Reg] && "Machine instr not mapped for this vreg?");
287 // If the loop contains the definition of an operand, then the instruction
288 // isn't loop invariant.
289 if (CurLoop->contains(VRegDefs[Reg]->getParent()))
293 // If we got this far, the instruction is loop invariant!
297 /// Hoist - When an instruction is found to only use loop invariant operands
298 /// that is safe to hoist, this instruction is called to do the dirty work.
300 void MachineLICM::Hoist(MachineInstr &MI) {
301 if (!IsLoopInvariantInst(MI)) return;
303 std::vector<MachineBasicBlock*> Preds;
305 // Non-back-edge predecessors.
306 FindPredecessors(Preds);
308 // Either we don't have any predecessors(?!) or we have more than one, which
310 if (Preds.empty() || Preds.size() != 1) return;
312 // Check that the predecessor is qualified to take the hoisted
313 // instruction. I.e., there is only one edge from the predecessor, and it's to
315 MachineBasicBlock *MBB = Preds.front();
317 // FIXME: We are assuming at first that the basic block coming into this loop
318 // has only one successor. This isn't the case in general because we haven't
319 // broken critical edges or added preheaders.
320 if (MBB->succ_size() != 1) return;
321 assert(*MBB->succ_begin() == CurLoop->getHeader() &&
322 "The predecessor doesn't feed directly into the loop header!");
324 // Now move the instructions to the predecessor.
325 MachineInstr *NewMI = MI.clone();
326 MoveInstToEndOfBlock(MBB, NewMI);
329 for (unsigned i = 0, e = NewMI->getNumOperands(); i != e; ++i) {
330 const MachineOperand &MO = NewMI->getOperand(i);
332 if (MO.isRegister() && MO.isDef() &&
333 MRegisterInfo::isVirtualRegister(MO.getReg()))
334 VRegDefs[MO.getReg()] = NewMI;
337 // Hoisting was successful! Remove bothersome instruction now.
338 MI.getParent()->remove(&MI);