1 //===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Methods common to all machine instructions.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "llvm/Constants.h"
16 #include "llvm/Function.h"
17 #include "llvm/InlineAsm.h"
18 #include "llvm/Metadata.h"
19 #include "llvm/Type.h"
20 #include "llvm/Value.h"
21 #include "llvm/Assembly/Writer.h"
22 #include "llvm/CodeGen/MachineConstantPool.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineMemOperand.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/PseudoSourceValue.h"
27 #include "llvm/MC/MCSymbol.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include "llvm/Target/TargetInstrInfo.h"
30 #include "llvm/Target/TargetInstrDesc.h"
31 #include "llvm/Target/TargetRegisterInfo.h"
32 #include "llvm/Analysis/AliasAnalysis.h"
33 #include "llvm/Analysis/DebugInfo.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/LeakDetector.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/raw_ostream.h"
39 #include "llvm/ADT/FoldingSet.h"
42 //===----------------------------------------------------------------------===//
43 // MachineOperand Implementation
44 //===----------------------------------------------------------------------===//
46 /// AddRegOperandToRegInfo - Add this register operand to the specified
47 /// MachineRegisterInfo. If it is null, then the next/prev fields should be
48 /// explicitly nulled out.
49 void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) {
50 assert(isReg() && "Can only add reg operand to use lists");
52 // If the reginfo pointer is null, just explicitly null out or next/prev
53 // pointers, to ensure they are not garbage.
55 Contents.Reg.Prev = 0;
56 Contents.Reg.Next = 0;
60 // Otherwise, add this operand to the head of the registers use/def list.
61 MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg());
63 // For SSA values, we prefer to keep the definition at the start of the list.
64 // we do this by skipping over the definition if it is at the head of the
66 if (*Head && (*Head)->isDef())
67 Head = &(*Head)->Contents.Reg.Next;
69 Contents.Reg.Next = *Head;
70 if (Contents.Reg.Next) {
71 assert(getReg() == Contents.Reg.Next->getReg() &&
72 "Different regs on the same list!");
73 Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next;
76 Contents.Reg.Prev = Head;
80 /// RemoveRegOperandFromRegInfo - Remove this register operand from the
81 /// MachineRegisterInfo it is linked with.
82 void MachineOperand::RemoveRegOperandFromRegInfo() {
83 assert(isOnRegUseList() && "Reg operand is not on a use list");
84 // Unlink this from the doubly linked list of operands.
85 MachineOperand *NextOp = Contents.Reg.Next;
86 *Contents.Reg.Prev = NextOp;
88 assert(NextOp->getReg() == getReg() && "Corrupt reg use/def chain!");
89 NextOp->Contents.Reg.Prev = Contents.Reg.Prev;
91 Contents.Reg.Prev = 0;
92 Contents.Reg.Next = 0;
95 void MachineOperand::setReg(unsigned Reg) {
96 if (getReg() == Reg) return; // No change.
98 // Otherwise, we have to change the register. If this operand is embedded
99 // into a machine function, we need to update the old and new register's
101 if (MachineInstr *MI = getParent())
102 if (MachineBasicBlock *MBB = MI->getParent())
103 if (MachineFunction *MF = MBB->getParent()) {
104 RemoveRegOperandFromRegInfo();
105 Contents.Reg.RegNo = Reg;
106 AddRegOperandToRegInfo(&MF->getRegInfo());
110 // Otherwise, just change the register, no problem. :)
111 Contents.Reg.RegNo = Reg;
114 void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx,
115 const TargetRegisterInfo &TRI) {
116 assert(TargetRegisterInfo::isVirtualRegister(Reg));
117 if (SubIdx && getSubReg())
118 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
124 void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) {
125 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
127 Reg = TRI.getSubReg(Reg, getSubReg());
128 assert(Reg && "Invalid SubReg for physical register");
134 /// ChangeToImmediate - Replace this operand with a new immediate operand of
135 /// the specified value. If an operand is known to be an immediate already,
136 /// the setImm method should be used.
137 void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
138 // If this operand is currently a register operand, and if this is in a
139 // function, deregister the operand from the register's use/def list.
140 if (isReg() && getParent() && getParent()->getParent() &&
141 getParent()->getParent()->getParent())
142 RemoveRegOperandFromRegInfo();
144 OpKind = MO_Immediate;
145 Contents.ImmVal = ImmVal;
148 /// ChangeToRegister - Replace this operand with a new register operand of
149 /// the specified value. If an operand is known to be an register already,
150 /// the setReg method should be used.
151 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
152 bool isKill, bool isDead, bool isUndef,
154 // If this operand is already a register operand, use setReg to update the
155 // register's use/def lists.
157 assert(!isEarlyClobber());
160 // Otherwise, change this to a register and set the reg#.
161 OpKind = MO_Register;
162 Contents.Reg.RegNo = Reg;
164 // If this operand is embedded in a function, add the operand to the
165 // register's use/def list.
166 if (MachineInstr *MI = getParent())
167 if (MachineBasicBlock *MBB = MI->getParent())
168 if (MachineFunction *MF = MBB->getParent())
169 AddRegOperandToRegInfo(&MF->getRegInfo());
177 IsEarlyClobber = false;
182 /// isIdenticalTo - Return true if this operand is identical to the specified
184 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
185 if (getType() != Other.getType() ||
186 getTargetFlags() != Other.getTargetFlags())
190 default: llvm_unreachable("Unrecognized operand type");
191 case MachineOperand::MO_Register:
192 return getReg() == Other.getReg() && isDef() == Other.isDef() &&
193 getSubReg() == Other.getSubReg();
194 case MachineOperand::MO_Immediate:
195 return getImm() == Other.getImm();
196 case MachineOperand::MO_FPImmediate:
197 return getFPImm() == Other.getFPImm();
198 case MachineOperand::MO_MachineBasicBlock:
199 return getMBB() == Other.getMBB();
200 case MachineOperand::MO_FrameIndex:
201 return getIndex() == Other.getIndex();
202 case MachineOperand::MO_ConstantPoolIndex:
203 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
204 case MachineOperand::MO_JumpTableIndex:
205 return getIndex() == Other.getIndex();
206 case MachineOperand::MO_GlobalAddress:
207 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
208 case MachineOperand::MO_ExternalSymbol:
209 return !strcmp(getSymbolName(), Other.getSymbolName()) &&
210 getOffset() == Other.getOffset();
211 case MachineOperand::MO_BlockAddress:
212 return getBlockAddress() == Other.getBlockAddress();
213 case MachineOperand::MO_MCSymbol:
214 return getMCSymbol() == Other.getMCSymbol();
215 case MachineOperand::MO_Metadata:
216 return getMetadata() == Other.getMetadata();
220 /// print - Print the specified machine operand.
222 void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
223 // If the instruction is embedded into a basic block, we can find the
224 // target info for the instruction.
226 if (const MachineInstr *MI = getParent())
227 if (const MachineBasicBlock *MBB = MI->getParent())
228 if (const MachineFunction *MF = MBB->getParent())
229 TM = &MF->getTarget();
232 case MachineOperand::MO_Register:
233 if (getReg() == 0 || TargetRegisterInfo::isVirtualRegister(getReg())) {
234 OS << "%reg" << getReg();
237 OS << "%" << TM->getRegisterInfo()->get(getReg()).Name;
239 OS << "%physreg" << getReg();
242 if (getSubReg() != 0) {
244 OS << ':' << TM->getRegisterInfo()->getSubRegIndexName(getSubReg());
246 OS << ':' << getSubReg();
249 if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
252 bool NeedComma = false;
254 if (NeedComma) OS << ',';
255 if (isEarlyClobber())
256 OS << "earlyclobber,";
261 } else if (isImplicit()) {
266 if (isKill() || isDead() || isUndef()) {
267 if (NeedComma) OS << ',';
268 if (isKill()) OS << "kill";
269 if (isDead()) OS << "dead";
271 if (isKill() || isDead())
279 case MachineOperand::MO_Immediate:
282 case MachineOperand::MO_FPImmediate:
283 if (getFPImm()->getType()->isFloatTy())
284 OS << getFPImm()->getValueAPF().convertToFloat();
286 OS << getFPImm()->getValueAPF().convertToDouble();
288 case MachineOperand::MO_MachineBasicBlock:
289 OS << "<BB#" << getMBB()->getNumber() << ">";
291 case MachineOperand::MO_FrameIndex:
292 OS << "<fi#" << getIndex() << '>';
294 case MachineOperand::MO_ConstantPoolIndex:
295 OS << "<cp#" << getIndex();
296 if (getOffset()) OS << "+" << getOffset();
299 case MachineOperand::MO_JumpTableIndex:
300 OS << "<jt#" << getIndex() << '>';
302 case MachineOperand::MO_GlobalAddress:
304 WriteAsOperand(OS, getGlobal(), /*PrintType=*/false);
305 if (getOffset()) OS << "+" << getOffset();
308 case MachineOperand::MO_ExternalSymbol:
309 OS << "<es:" << getSymbolName();
310 if (getOffset()) OS << "+" << getOffset();
313 case MachineOperand::MO_BlockAddress:
315 WriteAsOperand(OS, getBlockAddress(), /*PrintType=*/false);
318 case MachineOperand::MO_Metadata:
320 WriteAsOperand(OS, getMetadata(), /*PrintType=*/false);
323 case MachineOperand::MO_MCSymbol:
324 OS << "<MCSym=" << *getMCSymbol() << '>';
327 llvm_unreachable("Unrecognized operand type");
330 if (unsigned TF = getTargetFlags())
331 OS << "[TF=" << TF << ']';
334 //===----------------------------------------------------------------------===//
335 // MachineMemOperand Implementation
336 //===----------------------------------------------------------------------===//
338 MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, unsigned f,
339 uint64_t s, unsigned int a)
340 : PtrInfo(ptrinfo), Size(s),
341 Flags((f & ((1 << MOMaxBits) - 1)) | ((Log2_32(a) + 1) << MOMaxBits)) {
342 assert((PtrInfo.V == 0 || isa<PointerType>(PtrInfo.V->getType())) &&
343 "invalid pointer value");
344 assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
345 assert((isLoad() || isStore()) && "Not a load/store!");
348 /// Profile - Gather unique data for the object.
350 void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
351 ID.AddInteger(getOffset());
353 ID.AddPointer(getValue());
354 ID.AddInteger(Flags);
357 void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
358 // The Value and Offset may differ due to CSE. But the flags and size
359 // should be the same.
360 assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
361 assert(MMO->getSize() == getSize() && "Size mismatch!");
363 if (MMO->getBaseAlignment() >= getBaseAlignment()) {
364 // Update the alignment value.
365 Flags = (Flags & ((1 << MOMaxBits) - 1)) |
366 ((Log2_32(MMO->getBaseAlignment()) + 1) << MOMaxBits);
367 // Also update the base and offset, because the new alignment may
368 // not be applicable with the old ones.
369 PtrInfo = MMO->PtrInfo;
373 /// getAlignment - Return the minimum known alignment in bytes of the
374 /// actual memory reference.
375 uint64_t MachineMemOperand::getAlignment() const {
376 return MinAlign(getBaseAlignment(), getOffset());
379 raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineMemOperand &MMO) {
380 assert((MMO.isLoad() || MMO.isStore()) &&
381 "SV has to be a load, store or both.");
383 if (MMO.isVolatile())
392 // Print the address information.
397 WriteAsOperand(OS, MMO.getValue(), /*PrintType=*/false);
399 // If the alignment of the memory reference itself differs from the alignment
400 // of the base pointer, print the base alignment explicitly, next to the base
402 if (MMO.getBaseAlignment() != MMO.getAlignment())
403 OS << "(align=" << MMO.getBaseAlignment() << ")";
405 if (MMO.getOffset() != 0)
406 OS << "+" << MMO.getOffset();
409 // Print the alignment of the reference.
410 if (MMO.getBaseAlignment() != MMO.getAlignment() ||
411 MMO.getBaseAlignment() != MMO.getSize())
412 OS << "(align=" << MMO.getAlignment() << ")";
417 //===----------------------------------------------------------------------===//
418 // MachineInstr Implementation
419 //===----------------------------------------------------------------------===//
421 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
422 /// TID NULL and no operands.
423 MachineInstr::MachineInstr()
424 : TID(0), NumImplicitOps(0), AsmPrinterFlags(0), MemRefs(0), MemRefsEnd(0),
426 // Make sure that we get added to a machine basicblock
427 LeakDetector::addGarbageObject(this);
430 void MachineInstr::addImplicitDefUseOperands() {
431 if (TID->ImplicitDefs)
432 for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
433 addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
434 if (TID->ImplicitUses)
435 for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
436 addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
439 /// MachineInstr ctor - This constructor creates a MachineInstr and adds the
440 /// implicit operands. It reserves space for the number of operands specified by
441 /// the TargetInstrDesc.
442 MachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp)
443 : TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0),
444 MemRefs(0), MemRefsEnd(0), Parent(0) {
446 NumImplicitOps = TID->getNumImplicitDefs() + TID->getNumImplicitUses();
447 Operands.reserve(NumImplicitOps + TID->getNumOperands());
449 addImplicitDefUseOperands();
450 // Make sure that we get added to a machine basicblock
451 LeakDetector::addGarbageObject(this);
454 /// MachineInstr ctor - As above, but with a DebugLoc.
455 MachineInstr::MachineInstr(const TargetInstrDesc &tid, const DebugLoc dl,
457 : TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0), MemRefs(0), MemRefsEnd(0),
458 Parent(0), debugLoc(dl) {
460 NumImplicitOps = TID->getNumImplicitDefs() + TID->getNumImplicitUses();
461 Operands.reserve(NumImplicitOps + TID->getNumOperands());
463 addImplicitDefUseOperands();
464 // Make sure that we get added to a machine basicblock
465 LeakDetector::addGarbageObject(this);
468 /// MachineInstr ctor - Work exactly the same as the ctor two above, except
469 /// that the MachineInstr is created and added to the end of the specified
471 MachineInstr::MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &tid)
472 : TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0),
473 MemRefs(0), MemRefsEnd(0), Parent(0) {
474 assert(MBB && "Cannot use inserting ctor with null basic block!");
475 NumImplicitOps = TID->getNumImplicitDefs() + TID->getNumImplicitUses();
476 Operands.reserve(NumImplicitOps + TID->getNumOperands());
477 addImplicitDefUseOperands();
478 // Make sure that we get added to a machine basicblock
479 LeakDetector::addGarbageObject(this);
480 MBB->push_back(this); // Add instruction to end of basic block!
483 /// MachineInstr ctor - As above, but with a DebugLoc.
485 MachineInstr::MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
486 const TargetInstrDesc &tid)
487 : TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0), MemRefs(0), MemRefsEnd(0),
488 Parent(0), debugLoc(dl) {
489 assert(MBB && "Cannot use inserting ctor with null basic block!");
490 NumImplicitOps = TID->getNumImplicitDefs() + TID->getNumImplicitUses();
491 Operands.reserve(NumImplicitOps + TID->getNumOperands());
492 addImplicitDefUseOperands();
493 // Make sure that we get added to a machine basicblock
494 LeakDetector::addGarbageObject(this);
495 MBB->push_back(this); // Add instruction to end of basic block!
498 /// MachineInstr ctor - Copies MachineInstr arg exactly
500 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
501 : TID(&MI.getDesc()), NumImplicitOps(0), AsmPrinterFlags(0),
502 MemRefs(MI.MemRefs), MemRefsEnd(MI.MemRefsEnd),
503 Parent(0), debugLoc(MI.getDebugLoc()) {
504 Operands.reserve(MI.getNumOperands());
507 for (unsigned i = 0; i != MI.getNumOperands(); ++i)
508 addOperand(MI.getOperand(i));
509 NumImplicitOps = MI.NumImplicitOps;
511 // Set parent to null.
514 LeakDetector::addGarbageObject(this);
517 MachineInstr::~MachineInstr() {
518 LeakDetector::removeGarbageObject(this);
520 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
521 assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
522 assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
523 "Reg operand def/use list corrupted");
528 /// getRegInfo - If this instruction is embedded into a MachineFunction,
529 /// return the MachineRegisterInfo object for the current function, otherwise
531 MachineRegisterInfo *MachineInstr::getRegInfo() {
532 if (MachineBasicBlock *MBB = getParent())
533 return &MBB->getParent()->getRegInfo();
537 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
538 /// this instruction from their respective use lists. This requires that the
539 /// operands already be on their use lists.
540 void MachineInstr::RemoveRegOperandsFromUseLists() {
541 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
542 if (Operands[i].isReg())
543 Operands[i].RemoveRegOperandFromRegInfo();
547 /// AddRegOperandsToUseLists - Add all of the register operands in
548 /// this instruction from their respective use lists. This requires that the
549 /// operands not be on their use lists yet.
550 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) {
551 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
552 if (Operands[i].isReg())
553 Operands[i].AddRegOperandToRegInfo(&RegInfo);
558 /// addOperand - Add the specified operand to the instruction. If it is an
559 /// implicit operand, it is added to the end of the operand list. If it is
560 /// an explicit operand it is added at the end of the explicit operand list
561 /// (before the first implicit operand).
562 void MachineInstr::addOperand(const MachineOperand &Op) {
563 bool isImpReg = Op.isReg() && Op.isImplicit();
564 assert((isImpReg || !OperandsComplete()) &&
565 "Trying to add an operand to a machine instr that is already done!");
567 MachineRegisterInfo *RegInfo = getRegInfo();
569 // If we are adding the operand to the end of the list, our job is simpler.
570 // This is true most of the time, so this is a reasonable optimization.
571 if (isImpReg || NumImplicitOps == 0) {
572 // We can only do this optimization if we know that the operand list won't
574 if (Operands.empty() || Operands.size()+1 <= Operands.capacity()) {
575 Operands.push_back(Op);
577 // Set the parent of the operand.
578 Operands.back().ParentMI = this;
580 // If the operand is a register, update the operand's use list.
582 Operands.back().AddRegOperandToRegInfo(RegInfo);
583 // If the register operand is flagged as early, mark the operand as such
584 unsigned OpNo = Operands.size() - 1;
585 if (TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1)
586 Operands[OpNo].setIsEarlyClobber(true);
592 // Otherwise, we have to insert a real operand before any implicit ones.
593 unsigned OpNo = Operands.size()-NumImplicitOps;
595 // If this instruction isn't embedded into a function, then we don't need to
596 // update any operand lists.
598 // Simple insertion, no reginfo update needed for other register operands.
599 Operands.insert(Operands.begin()+OpNo, Op);
600 Operands[OpNo].ParentMI = this;
602 // Do explicitly set the reginfo for this operand though, to ensure the
603 // next/prev fields are properly nulled out.
604 if (Operands[OpNo].isReg()) {
605 Operands[OpNo].AddRegOperandToRegInfo(0);
606 // If the register operand is flagged as early, mark the operand as such
607 if (TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1)
608 Operands[OpNo].setIsEarlyClobber(true);
611 } else if (Operands.size()+1 <= Operands.capacity()) {
612 // Otherwise, we have to remove register operands from their register use
613 // list, add the operand, then add the register operands back to their use
614 // list. This also must handle the case when the operand list reallocates
615 // to somewhere else.
617 // If insertion of this operand won't cause reallocation of the operand
618 // list, just remove the implicit operands, add the operand, then re-add all
619 // the rest of the operands.
620 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
621 assert(Operands[i].isReg() && "Should only be an implicit reg!");
622 Operands[i].RemoveRegOperandFromRegInfo();
625 // Add the operand. If it is a register, add it to the reg list.
626 Operands.insert(Operands.begin()+OpNo, Op);
627 Operands[OpNo].ParentMI = this;
629 if (Operands[OpNo].isReg()) {
630 Operands[OpNo].AddRegOperandToRegInfo(RegInfo);
631 // If the register operand is flagged as early, mark the operand as such
632 if (TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1)
633 Operands[OpNo].setIsEarlyClobber(true);
636 // Re-add all the implicit ops.
637 for (unsigned i = OpNo+1, e = Operands.size(); i != e; ++i) {
638 assert(Operands[i].isReg() && "Should only be an implicit reg!");
639 Operands[i].AddRegOperandToRegInfo(RegInfo);
642 // Otherwise, we will be reallocating the operand list. Remove all reg
643 // operands from their list, then readd them after the operand list is
645 RemoveRegOperandsFromUseLists();
647 Operands.insert(Operands.begin()+OpNo, Op);
648 Operands[OpNo].ParentMI = this;
650 // Re-add all the operands.
651 AddRegOperandsToUseLists(*RegInfo);
653 // If the register operand is flagged as early, mark the operand as such
654 if (Operands[OpNo].isReg()
655 && TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1)
656 Operands[OpNo].setIsEarlyClobber(true);
660 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
661 /// fewer operand than it started with.
663 void MachineInstr::RemoveOperand(unsigned OpNo) {
664 assert(OpNo < Operands.size() && "Invalid operand number");
666 // Special case removing the last one.
667 if (OpNo == Operands.size()-1) {
668 // If needed, remove from the reg def/use list.
669 if (Operands.back().isReg() && Operands.back().isOnRegUseList())
670 Operands.back().RemoveRegOperandFromRegInfo();
676 // Otherwise, we are removing an interior operand. If we have reginfo to
677 // update, remove all operands that will be shifted down from their reg lists,
678 // move everything down, then re-add them.
679 MachineRegisterInfo *RegInfo = getRegInfo();
681 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
682 if (Operands[i].isReg())
683 Operands[i].RemoveRegOperandFromRegInfo();
687 Operands.erase(Operands.begin()+OpNo);
690 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
691 if (Operands[i].isReg())
692 Operands[i].AddRegOperandToRegInfo(RegInfo);
697 /// addMemOperand - Add a MachineMemOperand to the machine instruction.
698 /// This function should be used only occasionally. The setMemRefs function
699 /// is the primary method for setting up a MachineInstr's MemRefs list.
700 void MachineInstr::addMemOperand(MachineFunction &MF,
701 MachineMemOperand *MO) {
702 mmo_iterator OldMemRefs = MemRefs;
703 mmo_iterator OldMemRefsEnd = MemRefsEnd;
705 size_t NewNum = (MemRefsEnd - MemRefs) + 1;
706 mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum);
707 mmo_iterator NewMemRefsEnd = NewMemRefs + NewNum;
709 std::copy(OldMemRefs, OldMemRefsEnd, NewMemRefs);
710 NewMemRefs[NewNum - 1] = MO;
712 MemRefs = NewMemRefs;
713 MemRefsEnd = NewMemRefsEnd;
716 bool MachineInstr::isIdenticalTo(const MachineInstr *Other,
717 MICheckType Check) const {
718 // If opcodes or number of operands are not the same then the two
719 // instructions are obviously not identical.
720 if (Other->getOpcode() != getOpcode() ||
721 Other->getNumOperands() != getNumOperands())
724 // Check operands to make sure they match.
725 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
726 const MachineOperand &MO = getOperand(i);
727 const MachineOperand &OMO = Other->getOperand(i);
728 // Clients may or may not want to ignore defs when testing for equality.
729 // For example, machine CSE pass only cares about finding common
730 // subexpressions, so it's safe to ignore virtual register defs.
731 if (Check != CheckDefs && MO.isReg() && MO.isDef()) {
732 if (Check == IgnoreDefs)
734 // Check == IgnoreVRegDefs
735 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) ||
736 TargetRegisterInfo::isPhysicalRegister(OMO.getReg()))
737 if (MO.getReg() != OMO.getReg())
739 } else if (!MO.isIdenticalTo(OMO))
745 /// removeFromParent - This method unlinks 'this' from the containing basic
746 /// block, and returns it, but does not delete it.
747 MachineInstr *MachineInstr::removeFromParent() {
748 assert(getParent() && "Not embedded in a basic block!");
749 getParent()->remove(this);
754 /// eraseFromParent - This method unlinks 'this' from the containing basic
755 /// block, and deletes it.
756 void MachineInstr::eraseFromParent() {
757 assert(getParent() && "Not embedded in a basic block!");
758 getParent()->erase(this);
762 /// OperandComplete - Return true if it's illegal to add a new operand
764 bool MachineInstr::OperandsComplete() const {
765 unsigned short NumOperands = TID->getNumOperands();
766 if (!TID->isVariadic() && getNumOperands()-NumImplicitOps >= NumOperands)
767 return true; // Broken: we have all the operands of this instruction!
771 /// getNumExplicitOperands - Returns the number of non-implicit operands.
773 unsigned MachineInstr::getNumExplicitOperands() const {
774 unsigned NumOperands = TID->getNumOperands();
775 if (!TID->isVariadic())
778 for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) {
779 const MachineOperand &MO = getOperand(i);
780 if (!MO.isReg() || !MO.isImplicit())
787 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
788 /// the specific register or -1 if it is not found. It further tightens
789 /// the search criteria to a use that kills the register if isKill is true.
790 int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
791 const TargetRegisterInfo *TRI) const {
792 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
793 const MachineOperand &MO = getOperand(i);
794 if (!MO.isReg() || !MO.isUse())
796 unsigned MOReg = MO.getReg();
801 TargetRegisterInfo::isPhysicalRegister(MOReg) &&
802 TargetRegisterInfo::isPhysicalRegister(Reg) &&
803 TRI->isSubRegister(MOReg, Reg)))
804 if (!isKill || MO.isKill())
810 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
811 /// indicating if this instruction reads or writes Reg. This also considers
814 MachineInstr::readsWritesVirtualRegister(unsigned Reg,
815 SmallVectorImpl<unsigned> *Ops) const {
816 bool PartDef = false; // Partial redefine.
817 bool FullDef = false; // Full define.
820 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
821 const MachineOperand &MO = getOperand(i);
822 if (!MO.isReg() || MO.getReg() != Reg)
827 Use |= !MO.isUndef();
828 else if (MO.getSubReg())
833 // A partial redefine uses Reg unless there is also a full define.
834 return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
837 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
838 /// the specified register or -1 if it is not found. If isDead is true, defs
839 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
840 /// also checks if there is a def of a super-register.
842 MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap,
843 const TargetRegisterInfo *TRI) const {
844 bool isPhys = TargetRegisterInfo::isPhysicalRegister(Reg);
845 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
846 const MachineOperand &MO = getOperand(i);
847 if (!MO.isReg() || !MO.isDef())
849 unsigned MOReg = MO.getReg();
850 bool Found = (MOReg == Reg);
851 if (!Found && TRI && isPhys &&
852 TargetRegisterInfo::isPhysicalRegister(MOReg)) {
854 Found = TRI->regsOverlap(MOReg, Reg);
856 Found = TRI->isSubRegister(MOReg, Reg);
858 if (Found && (!isDead || MO.isDead()))
864 /// findFirstPredOperandIdx() - Find the index of the first operand in the
865 /// operand list that is used to represent the predicate. It returns -1 if
867 int MachineInstr::findFirstPredOperandIdx() const {
868 const TargetInstrDesc &TID = getDesc();
869 if (TID.isPredicable()) {
870 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
871 if (TID.OpInfo[i].isPredicate())
878 /// isRegTiedToUseOperand - Given the index of a register def operand,
879 /// check if the register def is tied to a source operand, due to either
880 /// two-address elimination or inline assembly constraints. Returns the
881 /// first tied use operand index by reference is UseOpIdx is not null.
883 isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx) const {
885 assert(DefOpIdx >= 3);
886 const MachineOperand &MO = getOperand(DefOpIdx);
887 if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
889 // Determine the actual operand index that corresponds to this index.
891 unsigned DefPart = 0;
892 for (unsigned i = 2, e = getNumOperands(); i < e; ) {
893 const MachineOperand &FMO = getOperand(i);
894 // After the normal asm operands there may be additional imp-def regs.
897 // Skip over this def.
898 unsigned NumOps = InlineAsm::getNumOperandRegisters(FMO.getImm());
899 unsigned PrevDef = i + 1;
900 i = PrevDef + NumOps;
902 DefPart = DefOpIdx - PrevDef;
907 for (unsigned i = 2, e = getNumOperands(); i != e; ++i) {
908 const MachineOperand &FMO = getOperand(i);
911 if (i+1 >= e || !getOperand(i+1).isReg() || !getOperand(i+1).isUse())
914 if (InlineAsm::isUseOperandTiedToDef(FMO.getImm(), Idx) &&
917 *UseOpIdx = (unsigned)i + 1 + DefPart;
924 assert(getOperand(DefOpIdx).isDef() && "DefOpIdx is not a def!");
925 const TargetInstrDesc &TID = getDesc();
926 for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
927 const MachineOperand &MO = getOperand(i);
928 if (MO.isReg() && MO.isUse() &&
929 TID.getOperandConstraint(i, TOI::TIED_TO) == (int)DefOpIdx) {
931 *UseOpIdx = (unsigned)i;
938 /// isRegTiedToDefOperand - Return true if the operand of the specified index
939 /// is a register use and it is tied to an def operand. It also returns the def
940 /// operand index by reference.
942 isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx) const {
944 const MachineOperand &MO = getOperand(UseOpIdx);
945 if (!MO.isReg() || !MO.isUse() || MO.getReg() == 0)
948 // Find the flag operand corresponding to UseOpIdx
949 unsigned FlagIdx, NumOps=0;
950 for (FlagIdx = 2; FlagIdx < UseOpIdx; FlagIdx += NumOps+1) {
951 const MachineOperand &UFMO = getOperand(FlagIdx);
952 // After the normal asm operands there may be additional imp-def regs.
955 NumOps = InlineAsm::getNumOperandRegisters(UFMO.getImm());
956 assert(NumOps < getNumOperands() && "Invalid inline asm flag");
957 if (UseOpIdx < FlagIdx+NumOps+1)
960 if (FlagIdx >= UseOpIdx)
962 const MachineOperand &UFMO = getOperand(FlagIdx);
964 if (InlineAsm::isUseOperandTiedToDef(UFMO.getImm(), DefNo)) {
969 // Remember to adjust the index. First operand is asm string, second is
970 // the AlignStack bit, then there is a flag for each.
972 const MachineOperand &FMO = getOperand(DefIdx);
974 // Skip over this def.
975 DefIdx += InlineAsm::getNumOperandRegisters(FMO.getImm()) + 1;
978 *DefOpIdx = DefIdx + UseOpIdx - FlagIdx;
984 const TargetInstrDesc &TID = getDesc();
985 if (UseOpIdx >= TID.getNumOperands())
987 const MachineOperand &MO = getOperand(UseOpIdx);
988 if (!MO.isReg() || !MO.isUse())
990 int DefIdx = TID.getOperandConstraint(UseOpIdx, TOI::TIED_TO);
994 *DefOpIdx = (unsigned)DefIdx;
998 /// clearKillInfo - Clears kill flags on all operands.
1000 void MachineInstr::clearKillInfo() {
1001 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1002 MachineOperand &MO = getOperand(i);
1003 if (MO.isReg() && MO.isUse())
1004 MO.setIsKill(false);
1008 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
1010 void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
1011 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1012 const MachineOperand &MO = MI->getOperand(i);
1013 if (!MO.isReg() || (!MO.isKill() && !MO.isDead()))
1015 for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
1016 MachineOperand &MOp = getOperand(j);
1017 if (!MOp.isIdenticalTo(MO))
1028 /// copyPredicates - Copies predicate operand(s) from MI.
1029 void MachineInstr::copyPredicates(const MachineInstr *MI) {
1030 const TargetInstrDesc &TID = MI->getDesc();
1031 if (!TID.isPredicable())
1033 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1034 if (TID.OpInfo[i].isPredicate()) {
1035 // Predicated operands must be last operands.
1036 addOperand(MI->getOperand(i));
1041 void MachineInstr::substituteRegister(unsigned FromReg,
1044 const TargetRegisterInfo &RegInfo) {
1045 if (TargetRegisterInfo::isPhysicalRegister(ToReg)) {
1047 ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1048 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1049 MachineOperand &MO = getOperand(i);
1050 if (!MO.isReg() || MO.getReg() != FromReg)
1052 MO.substPhysReg(ToReg, RegInfo);
1055 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1056 MachineOperand &MO = getOperand(i);
1057 if (!MO.isReg() || MO.getReg() != FromReg)
1059 MO.substVirtReg(ToReg, SubIdx, RegInfo);
1064 /// isSafeToMove - Return true if it is safe to move this instruction. If
1065 /// SawStore is set to true, it means that there is a store (or call) between
1066 /// the instruction's location and its intended destination.
1067 bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII,
1069 bool &SawStore) const {
1070 // Ignore stuff that we obviously can't move.
1071 if (TID->mayStore() || TID->isCall()) {
1075 if (TID->isTerminator() || TID->hasUnmodeledSideEffects())
1078 // See if this instruction does a load. If so, we have to guarantee that the
1079 // loaded value doesn't change between the load and the its intended
1080 // destination. The check for isInvariantLoad gives the targe the chance to
1081 // classify the load as always returning a constant, e.g. a constant pool
1083 if (TID->mayLoad() && !isInvariantLoad(AA))
1084 // Otherwise, this is a real load. If there is a store between the load and
1085 // end of block, or if the load is volatile, we can't move it.
1086 return !SawStore && !hasVolatileMemoryRef();
1091 /// isSafeToReMat - Return true if it's safe to rematerialize the specified
1092 /// instruction which defined the specified register instead of copying it.
1093 bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII,
1095 unsigned DstReg) const {
1096 bool SawStore = false;
1097 if (!TII->isTriviallyReMaterializable(this, AA) ||
1098 !isSafeToMove(TII, AA, SawStore))
1100 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1101 const MachineOperand &MO = getOperand(i);
1104 // FIXME: For now, do not remat any instruction with register operands.
1105 // Later on, we can loosen the restriction is the register operands have
1106 // not been modified between the def and use. Note, this is different from
1107 // MachineSink because the code is no longer in two-address form (at least
1111 else if (!MO.isDead() && MO.getReg() != DstReg)
1117 /// hasVolatileMemoryRef - Return true if this instruction may have a
1118 /// volatile memory reference, or if the information describing the
1119 /// memory reference is not available. Return false if it is known to
1120 /// have no volatile memory references.
1121 bool MachineInstr::hasVolatileMemoryRef() const {
1122 // An instruction known never to access memory won't have a volatile access.
1123 if (!TID->mayStore() &&
1126 !TID->hasUnmodeledSideEffects())
1129 // Otherwise, if the instruction has no memory reference information,
1130 // conservatively assume it wasn't preserved.
1131 if (memoperands_empty())
1134 // Check the memory reference information for volatile references.
1135 for (mmo_iterator I = memoperands_begin(), E = memoperands_end(); I != E; ++I)
1136 if ((*I)->isVolatile())
1142 /// isInvariantLoad - Return true if this instruction is loading from a
1143 /// location whose value is invariant across the function. For example,
1144 /// loading a value from the constant pool or from the argument area
1145 /// of a function if it does not change. This should only return true of
1146 /// *all* loads the instruction does are invariant (if it does multiple loads).
1147 bool MachineInstr::isInvariantLoad(AliasAnalysis *AA) const {
1148 // If the instruction doesn't load at all, it isn't an invariant load.
1149 if (!TID->mayLoad())
1152 // If the instruction has lost its memoperands, conservatively assume that
1153 // it may not be an invariant load.
1154 if (memoperands_empty())
1157 const MachineFrameInfo *MFI = getParent()->getParent()->getFrameInfo();
1159 for (mmo_iterator I = memoperands_begin(),
1160 E = memoperands_end(); I != E; ++I) {
1161 if ((*I)->isVolatile()) return false;
1162 if ((*I)->isStore()) return false;
1164 if (const Value *V = (*I)->getValue()) {
1165 // A load from a constant PseudoSourceValue is invariant.
1166 if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V))
1167 if (PSV->isConstant(MFI))
1169 // If we have an AliasAnalysis, ask it whether the memory is constant.
1170 if (AA && AA->pointsToConstantMemory(V))
1174 // Otherwise assume conservatively.
1178 // Everything checks out.
1182 /// isConstantValuePHI - If the specified instruction is a PHI that always
1183 /// merges together the same virtual register, return the register, otherwise
1185 unsigned MachineInstr::isConstantValuePHI() const {
1188 assert(getNumOperands() >= 3 &&
1189 "It's illegal to have a PHI without source operands");
1191 unsigned Reg = getOperand(1).getReg();
1192 for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1193 if (getOperand(i).getReg() != Reg)
1198 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
1200 bool MachineInstr::allDefsAreDead() const {
1201 for (unsigned i = 0, e = getNumOperands(); i < e; ++i) {
1202 const MachineOperand &MO = getOperand(i);
1203 if (!MO.isReg() || MO.isUse())
1211 void MachineInstr::dump() const {
1212 dbgs() << " " << *this;
1215 static void printDebugLoc(DebugLoc DL, const MachineFunction *MF,
1216 raw_ostream &CommentOS) {
1217 const LLVMContext &Ctx = MF->getFunction()->getContext();
1218 if (!DL.isUnknown()) { // Print source line info.
1219 DIScope Scope(DL.getScope(Ctx));
1220 // Omit the directory, because it's likely to be long and uninteresting.
1222 CommentOS << Scope.getFilename();
1224 CommentOS << "<unknown>";
1225 CommentOS << ':' << DL.getLine();
1226 if (DL.getCol() != 0)
1227 CommentOS << ':' << DL.getCol();
1228 DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(DL.getInlinedAt(Ctx));
1229 if (!InlinedAtDL.isUnknown()) {
1230 CommentOS << " @[ ";
1231 printDebugLoc(InlinedAtDL, MF, CommentOS);
1237 void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const {
1238 // We can be a bit tidier if we know the TargetMachine and/or MachineFunction.
1239 const MachineFunction *MF = 0;
1240 const MachineRegisterInfo *MRI = 0;
1241 if (const MachineBasicBlock *MBB = getParent()) {
1242 MF = MBB->getParent();
1244 TM = &MF->getTarget();
1246 MRI = &MF->getRegInfo();
1249 // Save a list of virtual registers.
1250 SmallVector<unsigned, 8> VirtRegs;
1252 // Print explicitly defined operands on the left of an assignment syntax.
1253 unsigned StartOp = 0, e = getNumOperands();
1254 for (; StartOp < e && getOperand(StartOp).isReg() &&
1255 getOperand(StartOp).isDef() &&
1256 !getOperand(StartOp).isImplicit();
1258 if (StartOp != 0) OS << ", ";
1259 getOperand(StartOp).print(OS, TM);
1260 unsigned Reg = getOperand(StartOp).getReg();
1261 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg))
1262 VirtRegs.push_back(Reg);
1268 // Print the opcode name.
1269 OS << getDesc().getName();
1271 // Print the rest of the operands.
1272 bool OmittedAnyCallClobbers = false;
1273 bool FirstOp = true;
1274 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1275 const MachineOperand &MO = getOperand(i);
1277 if (MO.isReg() && MO.getReg() &&
1278 TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1279 VirtRegs.push_back(MO.getReg());
1281 // Omit call-clobbered registers which aren't used anywhere. This makes
1282 // call instructions much less noisy on targets where calls clobber lots
1283 // of registers. Don't rely on MO.isDead() because we may be called before
1284 // LiveVariables is run, or we may be looking at a non-allocatable reg.
1285 if (MF && getDesc().isCall() &&
1286 MO.isReg() && MO.isImplicit() && MO.isDef()) {
1287 unsigned Reg = MO.getReg();
1288 if (Reg != 0 && TargetRegisterInfo::isPhysicalRegister(Reg)) {
1289 const MachineRegisterInfo &MRI = MF->getRegInfo();
1290 if (MRI.use_empty(Reg) && !MRI.isLiveOut(Reg)) {
1291 bool HasAliasLive = false;
1292 for (const unsigned *Alias = TM->getRegisterInfo()->getAliasSet(Reg);
1293 unsigned AliasReg = *Alias; ++Alias)
1294 if (!MRI.use_empty(AliasReg) || MRI.isLiveOut(AliasReg)) {
1295 HasAliasLive = true;
1298 if (!HasAliasLive) {
1299 OmittedAnyCallClobbers = true;
1306 if (FirstOp) FirstOp = false; else OS << ",";
1308 if (i < getDesc().NumOperands) {
1309 const TargetOperandInfo &TOI = getDesc().OpInfo[i];
1310 if (TOI.isPredicate())
1312 if (TOI.isOptionalDef())
1315 if (isDebugValue() && MO.isMetadata()) {
1316 // Pretty print DBG_VALUE instructions.
1317 const MDNode *MD = MO.getMetadata();
1318 if (const MDString *MDS = dyn_cast<MDString>(MD->getOperand(2)))
1319 OS << "!\"" << MDS->getString() << '\"';
1322 } else if (TM && (isInsertSubreg() || isRegSequence()) && MO.isImm()) {
1323 OS << TM->getRegisterInfo()->getSubRegIndexName(MO.getImm());
1328 // Briefly indicate whether any call clobbers were omitted.
1329 if (OmittedAnyCallClobbers) {
1330 if (!FirstOp) OS << ",";
1334 bool HaveSemi = false;
1335 if (!memoperands_empty()) {
1336 if (!HaveSemi) OS << ";"; HaveSemi = true;
1339 for (mmo_iterator i = memoperands_begin(), e = memoperands_end();
1342 if (llvm::next(i) != e)
1347 // Print the regclass of any virtual registers encountered.
1348 if (MRI && !VirtRegs.empty()) {
1349 if (!HaveSemi) OS << ";"; HaveSemi = true;
1350 for (unsigned i = 0; i != VirtRegs.size(); ++i) {
1351 const TargetRegisterClass *RC = MRI->getRegClass(VirtRegs[i]);
1352 OS << " " << RC->getName() << ":%reg" << VirtRegs[i];
1353 for (unsigned j = i+1; j != VirtRegs.size();) {
1354 if (MRI->getRegClass(VirtRegs[j]) != RC) {
1358 if (VirtRegs[i] != VirtRegs[j])
1359 OS << "," << VirtRegs[j];
1360 VirtRegs.erase(VirtRegs.begin()+j);
1365 if (!debugLoc.isUnknown() && MF) {
1366 if (!HaveSemi) OS << ";";
1368 printDebugLoc(debugLoc, MF, OS);
1374 bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
1375 const TargetRegisterInfo *RegInfo,
1376 bool AddIfNotFound) {
1377 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1378 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
1380 SmallVector<unsigned,4> DeadOps;
1381 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1382 MachineOperand &MO = getOperand(i);
1383 if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1385 unsigned Reg = MO.getReg();
1389 if (Reg == IncomingReg) {
1392 // The register is already marked kill.
1394 if (isPhysReg && isRegTiedToDefOperand(i))
1395 // Two-address uses of physregs must not be marked kill.
1400 } else if (hasAliases && MO.isKill() &&
1401 TargetRegisterInfo::isPhysicalRegister(Reg)) {
1402 // A super-register kill already exists.
1403 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1405 if (RegInfo->isSubRegister(IncomingReg, Reg))
1406 DeadOps.push_back(i);
1410 // Trim unneeded kill operands.
1411 while (!DeadOps.empty()) {
1412 unsigned OpIdx = DeadOps.back();
1413 if (getOperand(OpIdx).isImplicit())
1414 RemoveOperand(OpIdx);
1416 getOperand(OpIdx).setIsKill(false);
1420 // If not found, this means an alias of one of the operands is killed. Add a
1421 // new implicit operand if required.
1422 if (!Found && AddIfNotFound) {
1423 addOperand(MachineOperand::CreateReg(IncomingReg,
1432 bool MachineInstr::addRegisterDead(unsigned IncomingReg,
1433 const TargetRegisterInfo *RegInfo,
1434 bool AddIfNotFound) {
1435 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1436 bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
1438 SmallVector<unsigned,4> DeadOps;
1439 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1440 MachineOperand &MO = getOperand(i);
1441 if (!MO.isReg() || !MO.isDef())
1443 unsigned Reg = MO.getReg();
1447 if (Reg == IncomingReg) {
1450 // The register is already marked dead.
1455 } else if (hasAliases && MO.isDead() &&
1456 TargetRegisterInfo::isPhysicalRegister(Reg)) {
1457 // There exists a super-register that's marked dead.
1458 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1460 if (RegInfo->getSubRegisters(IncomingReg) &&
1461 RegInfo->getSuperRegisters(Reg) &&
1462 RegInfo->isSubRegister(IncomingReg, Reg))
1463 DeadOps.push_back(i);
1467 // Trim unneeded dead operands.
1468 while (!DeadOps.empty()) {
1469 unsigned OpIdx = DeadOps.back();
1470 if (getOperand(OpIdx).isImplicit())
1471 RemoveOperand(OpIdx);
1473 getOperand(OpIdx).setIsDead(false);
1477 // If not found, this means an alias of one of the operands is dead. Add a
1478 // new implicit operand if required.
1479 if (Found || !AddIfNotFound)
1482 addOperand(MachineOperand::CreateReg(IncomingReg,
1490 void MachineInstr::addRegisterDefined(unsigned IncomingReg,
1491 const TargetRegisterInfo *RegInfo) {
1492 if (TargetRegisterInfo::isPhysicalRegister(IncomingReg)) {
1493 MachineOperand *MO = findRegisterDefOperand(IncomingReg, false, RegInfo);
1497 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1498 const MachineOperand &MO = getOperand(i);
1499 if (MO.isReg() && MO.getReg() == IncomingReg && MO.isDef() &&
1500 MO.getSubReg() == 0)
1504 addOperand(MachineOperand::CreateReg(IncomingReg,
1509 void MachineInstr::setPhysRegsDeadExcept(const SmallVectorImpl<unsigned> &UsedRegs,
1510 const TargetRegisterInfo &TRI) {
1511 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1512 MachineOperand &MO = getOperand(i);
1513 if (!MO.isReg() || !MO.isDef()) continue;
1514 unsigned Reg = MO.getReg();
1515 if (Reg == 0) continue;
1517 for (SmallVectorImpl<unsigned>::const_iterator I = UsedRegs.begin(),
1518 E = UsedRegs.end(); I != E; ++I)
1519 if (TRI.regsOverlap(*I, Reg)) {
1523 // If there are no uses, including partial uses, the def is dead.
1524 if (Dead) MO.setIsDead();
1529 MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
1530 unsigned Hash = MI->getOpcode() * 37;
1531 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1532 const MachineOperand &MO = MI->getOperand(i);
1533 uint64_t Key = (uint64_t)MO.getType() << 32;
1534 switch (MO.getType()) {
1536 case MachineOperand::MO_Register:
1537 if (MO.isDef() && MO.getReg() &&
1538 TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1539 continue; // Skip virtual register defs.
1542 case MachineOperand::MO_Immediate:
1545 case MachineOperand::MO_FrameIndex:
1546 case MachineOperand::MO_ConstantPoolIndex:
1547 case MachineOperand::MO_JumpTableIndex:
1548 Key |= MO.getIndex();
1550 case MachineOperand::MO_MachineBasicBlock:
1551 Key |= DenseMapInfo<void*>::getHashValue(MO.getMBB());
1553 case MachineOperand::MO_GlobalAddress:
1554 Key |= DenseMapInfo<void*>::getHashValue(MO.getGlobal());
1556 case MachineOperand::MO_BlockAddress:
1557 Key |= DenseMapInfo<void*>::getHashValue(MO.getBlockAddress());
1559 case MachineOperand::MO_MCSymbol:
1560 Key |= DenseMapInfo<void*>::getHashValue(MO.getMCSymbol());
1563 Key += ~(Key << 32);
1565 Key += ~(Key << 13);
1569 Key += ~(Key << 27);
1571 Hash = (unsigned)Key + Hash * 37;