2 //***************************************************************************
12 // 7/2/01 - Vikram Adve - Created
13 //**************************************************************************/
16 #include "llvm/CodeGen/MachineInstr.h"
17 #include "llvm/Method.h"
18 #include "llvm/ConstPoolVals.h"
19 #include "llvm/Instruction.h"
22 //************************ Class Implementations **************************/
24 // Constructor for instructions with fixed #operands (nearly all)
25 MachineInstr::MachineInstr(MachineOpCode _opCode,
26 OpCodeMask _opCodeMask)
28 opCodeMask(_opCodeMask),
29 operands(TargetInstrDescriptors[_opCode].numOperands)
31 assert(TargetInstrDescriptors[_opCode].numOperands >= 0);
34 // Constructor for instructions with variable #operands
35 MachineInstr::MachineInstr(MachineOpCode _opCode,
37 OpCodeMask _opCodeMask)
39 opCodeMask(_opCodeMask),
45 MachineInstr::SetMachineOperand(unsigned int i,
46 MachineOperand::MachineOperandType operandType,
47 Value* _val, bool isdef=false)
49 assert(i < operands.size());
50 operands[i].Initialize(operandType, _val);
51 operands[i].isDef = isdef ||
52 TargetInstrDescriptors[opCode].resultPos == (int) i;
56 MachineInstr::SetMachineOperand(unsigned int i,
57 MachineOperand::MachineOperandType operandType,
58 int64_t intValue, bool isdef=false)
60 assert(i < operands.size());
61 operands[i].InitializeConst(operandType, intValue);
62 operands[i].isDef = isdef ||
63 TargetInstrDescriptors[opCode].resultPos == (int) i;
67 MachineInstr::SetMachineOperand(unsigned int i,
68 unsigned int regNum, bool isdef=false)
70 assert(i < operands.size());
71 operands[i].InitializeReg(regNum);
72 operands[i].isDef = isdef ||
73 TargetInstrDescriptors[opCode].resultPos == (int) i;
77 MachineInstr::dump(unsigned int indent) const
79 for (unsigned i=0; i < indent; i++)
86 operator<< (ostream& os, const MachineInstr& minstr)
88 os << TargetInstrDescriptors[minstr.opCode].opCodeString;
90 for (unsigned i=0, N=minstr.getNumOperands(); i < N; i++)
91 os << "\t" << minstr.getOperand(i);
93 #undef DEBUG_VAL_OP_ITERATOR
94 #ifdef DEBUG_VAL_OP_ITERATOR
95 os << endl << "\tValue operands are: ";
96 for (MachineInstr::val_op_const_iterator vo(&minstr); ! vo.done(); ++vo)
98 const Value* val = *vo;
99 os << val << (vo.isDef()? "(def), " : ", ");
107 static inline ostream &OutputOperand(ostream &os, const MachineOperand &mop) {
108 switch (mop.getOperandType()) {
109 case MachineOperand::MO_CCRegister:
110 case MachineOperand::MO_VirtualRegister:
111 return os << "(val " << mop.getVRegValue() << ")";
112 case MachineOperand::MO_MachineRegister:
113 return os << "(" << mop.getMachineRegNum() << ")";
115 assert(0 && "Unknown operand type");
121 ostream &operator<<(ostream &os, const MachineOperand &mop) {
123 case MachineOperand::MO_VirtualRegister:
124 case MachineOperand::MO_MachineRegister:
126 return OutputOperand(os, mop);
127 case MachineOperand::MO_CCRegister:
129 return OutputOperand(os, mop);
131 case MachineOperand::MO_SignExtendedImmed:
132 return os << mop.immedVal;
134 case MachineOperand::MO_UnextendedImmed:
135 return os << mop.immedVal;
137 case MachineOperand::MO_PCRelativeDisp:
138 os << "%disp(label ";
139 return OutputOperand(os, mop) << ")";
142 assert(0 && "Unrecognized operand type");
150 //---------------------------------------------------------------------------
151 // Target-independent utility routines for creating machine instructions
152 //---------------------------------------------------------------------------
155 //------------------------------------------------------------------------
156 // Function Set2OperandsFromInstr
157 // Function Set3OperandsFromInstr
159 // For the common case of 2- and 3-operand arithmetic/logical instructions,
160 // set the m/c instr. operands directly from the VM instruction's operands.
161 // Check whether the first or second operand is 0 and can use a dedicated "0" register.
162 // Check whether the second operand should use an immediate field or register.
163 // (First and third operands are never immediates for such instructions.)
166 // canDiscardResult: Specifies that the result operand can be discarded
167 // by using the dedicated "0"
169 // op1position, op2position and resultPosition: Specify in which position
170 // in the machine instruction the 3 operands (arg1, arg2
171 // and result) should go.
173 // RETURN VALUE: unsigned int flags, where
174 // flags & 0x01 => operand 1 is constant and needs a register
175 // flags & 0x02 => operand 2 is constant and needs a register
176 //------------------------------------------------------------------------
179 Set2OperandsFromInstr(MachineInstr* minstr,
180 InstructionNode* vmInstrNode,
181 const TargetMachine& target,
182 bool canDiscardResult,
186 Set3OperandsFromInstr(minstr, vmInstrNode, target,
187 canDiscardResult, op1Position,
188 /*op2Position*/ -1, resultPosition);
191 #undef REVERT_TO_EXPLICIT_CONSTANT_CHECKS
192 #ifdef REVERT_TO_EXPLICIT_CONSTANT_CHECKS
194 Set3OperandsFromInstrJUNK(MachineInstr* minstr,
195 InstructionNode* vmInstrNode,
196 const TargetMachine& target,
197 bool canDiscardResult,
202 assert(op1Position >= 0);
203 assert(resultPosition >= 0);
205 unsigned returnFlags = 0x0;
207 // Check if operand 1 is 0. If so, try to use a hardwired 0 register.
208 Value* op1Value = vmInstrNode->leftChild()->getValue();
209 bool isValidConstant;
210 int64_t intValue = GetConstantValueAsSignedInt(op1Value, isValidConstant);
211 if (isValidConstant && intValue == 0 && target.zeroRegNum >= 0)
212 minstr->SetMachineOperand(op1Position, /*regNum*/ target.zeroRegNum);
215 if (op1Value->getValueType() == Value::ConstantVal)
216 {// value is constant and must be loaded from constant pool
217 returnFlags = returnFlags | (1 << op1Position);
219 minstr->SetMachineOperand(op1Position,MachineOperand::MO_VirtualRegister,
223 // Check if operand 2 (if any) fits in the immed. field of the instruction,
224 // or if it is 0 and can use a dedicated machine register
225 if (op2Position >= 0)
227 Value* op2Value = vmInstrNode->rightChild()->getValue();
229 unsigned int machineRegNum;
231 MachineOperand::MachineOperandType
232 op2type = ChooseRegOrImmed(op2Value, minstr->getOpCode(), target,
233 /*canUseImmed*/ true,
234 machineRegNum, immedValue);
236 if (op2type == MachineOperand::MO_MachineRegister)
237 minstr->SetMachineOperand(op2Position, machineRegNum);
238 else if (op2type == MachineOperand::MO_VirtualRegister)
240 if (op2Value->getValueType() == Value::ConstantVal)
241 {// value is constant and must be loaded from constant pool
242 returnFlags = returnFlags | (1 << op2Position);
244 minstr->SetMachineOperand(op2Position, op2type, op2Value);
248 assert(op2type != MO_CCRegister);
249 minstr->SetMachineOperand(op2Position, op2type, immedValue);
253 // If operand 3 (result) can be discarded, use a dead register if one exists
254 if (canDiscardResult && target.zeroRegNum >= 0)
255 minstr->SetMachineOperand(resultPosition, target.zeroRegNum);
257 minstr->SetMachineOperand(resultPosition, MachineOperand::MO_VirtualRegister, vmInstrNode->getValue());
265 Set3OperandsFromInstr(MachineInstr* minstr,
266 InstructionNode* vmInstrNode,
267 const TargetMachine& target,
268 bool canDiscardResult,
273 assert(op1Position >= 0);
274 assert(resultPosition >= 0);
277 minstr->SetMachineOperand(op1Position, MachineOperand::MO_VirtualRegister,
278 vmInstrNode->leftChild()->getValue());
280 // operand 2 (if any)
281 if (op2Position >= 0)
282 minstr->SetMachineOperand(op2Position, MachineOperand::MO_VirtualRegister,
283 vmInstrNode->rightChild()->getValue());
285 // result operand: if it can be discarded, use a dead register if one exists
286 if (canDiscardResult && target.zeroRegNum >= 0)
287 minstr->SetMachineOperand(resultPosition, target.zeroRegNum);
289 minstr->SetMachineOperand(resultPosition, MachineOperand::MO_VirtualRegister, vmInstrNode->getValue());
293 MachineOperand::MachineOperandType
294 ChooseRegOrImmed(Value* val,
295 MachineOpCode opCode,
296 const TargetMachine& target,
298 unsigned int& getMachineRegNum,
299 int64_t& getImmedValue)
301 MachineOperand::MachineOperandType opType =
302 MachineOperand::MO_VirtualRegister;
303 getMachineRegNum = 0;
306 // Check for the common case first: argument is not constant
308 ConstPoolVal *CPV = val->castConstant();
309 if (!CPV) return opType;
311 if (CPV->getType() == Type::BoolTy) {
312 ConstPoolBool *CPB = (ConstPoolBool*)CPV;
313 if (!CPB->getValue() && target.zeroRegNum >= 0) {
314 getMachineRegNum = target.zeroRegNum;
315 return MachineOperand::MO_MachineRegister;
319 return MachineOperand::MO_SignExtendedImmed;
322 if (!CPV->getType()->isIntegral()) return opType;
324 // Now get the constant value and check if it fits in the IMMED field.
325 // Take advantage of the fact that the max unsigned value will rarely
326 // fit into any IMMED field and ignore that case (i.e., cast smaller
327 // unsigned constants to signed).
330 if (CPV->getType()->isSigned()) {
331 intValue = ((ConstPoolSInt*)CPV)->getValue();
333 uint64_t V = ((ConstPoolUInt*)CPV)->getValue();
334 if (V >= INT64_MAX) return opType;
335 intValue = (int64_t)V;
338 if (intValue == 0 && target.zeroRegNum >= 0){
339 opType = MachineOperand::MO_MachineRegister;
340 getMachineRegNum = target.zeroRegNum;
341 } else if (canUseImmed &&
342 target.getInstrInfo().constantFitsInImmedField(opCode, intValue)) {
343 opType = MachineOperand::MO_SignExtendedImmed;
344 getImmedValue = intValue;
352 PrintMachineInstructions(const Method* method)
354 cout << "\n" << method->getReturnType()
355 << " \"" << method->getName() << "\"" << endl;
357 for (Method::const_iterator BI = method->begin(); BI != method->end(); ++BI)
359 const BasicBlock* bb = *BI;
361 << (bb->hasName()? bb->getName() : "Label")
362 << " (" << bb << ")" << ":"
365 const MachineCodeForBasicBlock& mvec = bb->getMachineInstrVec();
366 for (unsigned i=0; i < mvec.size(); i++)
367 cout << "\t" << *mvec[i] << endl;
369 cout << endl << "End method \"" << method->getName() << "\""