1 //===-- MachineInstr.cpp --------------------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 #include "llvm/CodeGen/MachineInstr.h"
13 #include "llvm/CodeGen/MachineBasicBlock.h"
14 #include "llvm/Value.h"
15 #include "llvm/Target/TargetMachine.h"
16 #include "llvm/Target/TargetInstrInfo.h"
17 #include "llvm/Target/MRegisterInfo.h"
21 // Global variable holding an array of descriptors for machine instructions.
22 // The actual object needs to be created separately for each target machine.
23 // This variable is initialized and reset by class TargetInstrInfo.
25 // FIXME: This should be a property of the target so that more than one target
26 // at a time can be active...
28 extern const TargetInstrDescriptor *TargetInstrDescriptors;
30 bool MachineOperand::isEverUsed(const MachineInstr& mi) const
32 for (int i = 0, e = mi.getNumOperands(); i != e; ++i) {
33 if (*this == mi.getOperand(i) && mi.getOperand(i).isUse())
39 bool MachineOperand::isEverDefined(const MachineInstr& mi) const
41 for (int i = 0, e = mi.getNumOperands(); i != e; ++i) {
42 if (*this == mi.getOperand(i) && mi.getOperand(i).isDef())
48 // Constructor for instructions with variable #operands
49 MachineInstr::MachineInstr(MachineOpCode OpCode, unsigned numOperands)
52 operands(numOperands, MachineOperand()),
57 /// MachineInstr ctor - This constructor only does a _reserve_ of the operands,
58 /// not a resize for them. It is expected that if you use this that you call
59 /// add* methods below to fill up the operands, instead of the Set methods.
60 /// Eventually, the "resizing" ctors will be phased out.
62 MachineInstr::MachineInstr(MachineOpCode Opcode, unsigned numOperands,
68 operands.reserve(numOperands);
71 /// MachineInstr ctor - Work exactly the same as the ctor above, except that the
72 /// MachineInstr is created and added to the end of the specified basic block.
74 MachineInstr::MachineInstr(MachineBasicBlock *MBB, MachineOpCode Opcode,
80 assert(MBB && "Cannot use inserting ctor with null basic block!");
81 operands.reserve(numOperands);
82 MBB->push_back(this); // Add instruction to end of basic block!
86 // OperandComplete - Return true if it's illegal to add a new operand
87 bool MachineInstr::OperandsComplete() const
89 int NumOperands = TargetInstrDescriptors[opCode].numOperands;
90 if (NumOperands >= 0 && getNumOperands() >= (unsigned)NumOperands)
91 return true; // Broken: we have all the operands of this instruction!
97 // Support for replacing opcode and operands of a MachineInstr in place.
98 // This only resets the size of the operand vector and initializes it.
99 // The new operands must be set explicitly later.
101 void MachineInstr::replace(MachineOpCode Opcode, unsigned numOperands)
103 assert(getNumImplicitRefs() == 0 &&
104 "This is probably broken because implicit refs are going to be lost.");
107 operands.resize(numOperands, MachineOperand());
110 void MachineInstr::SetMachineOperandVal(unsigned i,
111 MachineOperand::MachineOperandType opTy,
113 assert(i < operands.size()); // may be explicit or implicit op
114 operands[i].opType = opTy;
115 operands[i].value = V;
116 operands[i].regNum = -1;
120 MachineInstr::SetMachineOperandConst(unsigned i,
121 MachineOperand::MachineOperandType operandType,
124 assert(i < getNumOperands()); // must be explicit op
125 assert(TargetInstrDescriptors[opCode].resultPos != (int) i &&
126 "immed. constant cannot be defined");
128 operands[i].opType = operandType;
129 operands[i].value = NULL;
130 operands[i].immedVal = intValue;
131 operands[i].regNum = -1;
132 operands[i].flags = 0;
135 void MachineInstr::SetMachineOperandReg(unsigned i, int regNum) {
136 assert(i < getNumOperands()); // must be explicit op
138 operands[i].opType = MachineOperand::MO_MachineRegister;
139 operands[i].value = NULL;
140 operands[i].regNum = regNum;
144 MachineInstr::SetRegForOperand(unsigned i, int regNum)
146 assert(i < getNumOperands()); // must be explicit op
147 operands[i].setRegForValue(regNum);
151 MachineInstr::SetRegForImplicitRef(unsigned i, int regNum)
153 getImplicitOp(i).setRegForValue(regNum);
157 // Substitute all occurrences of Value* oldVal with newVal in all operands
158 // and all implicit refs.
159 // If defsOnly == true, substitute defs only.
161 MachineInstr::substituteValue(const Value* oldVal, Value* newVal,
162 bool defsOnly, bool notDefsAndUses,
163 bool& someArgsWereIgnored)
165 assert((!defsOnly || !notDefsAndUses) &&
166 "notDefsAndUses is irrelevant if defsOnly == true.");
168 unsigned numSubst = 0;
170 // Substitute operands
171 for (MachineInstr::val_op_iterator O = begin(), E = end(); O != E; ++O)
174 notDefsAndUses && (O.isDef() && !O.isUse()) ||
175 !notDefsAndUses && O.isDef())
177 O.getMachineOperand().value = newVal;
181 someArgsWereIgnored = true;
183 // Substitute implicit refs
184 for (unsigned i=0, N=getNumImplicitRefs(); i < N; ++i)
185 if (getImplicitRef(i) == oldVal)
187 notDefsAndUses && (getImplicitOp(i).isDef() && !getImplicitOp(i).isUse()) ||
188 !notDefsAndUses && getImplicitOp(i).isDef())
190 getImplicitOp(i).value = newVal;
194 someArgsWereIgnored = true;
201 MachineInstr::dump() const
203 std::cerr << " " << *this;
206 static inline std::ostream&
207 OutputValue(std::ostream &os, const Value* val)
210 os << (void*) val; // print address always
211 if (val && val->hasName())
212 os << " " << val->getName() << ")"; // print name also, if available
216 static inline void OutputReg(std::ostream &os, unsigned RegNo,
217 const MRegisterInfo *MRI = 0) {
219 if (RegNo < MRegisterInfo::FirstVirtualRegister)
220 os << "%" << MRI->get(RegNo).Name;
222 os << "%reg" << RegNo;
224 os << "%mreg(" << RegNo << ")";
227 static void print(const MachineOperand &MO, std::ostream &OS,
228 const TargetMachine &TM) {
229 const MRegisterInfo *MRI = TM.getRegisterInfo();
230 bool CloseParen = true;
233 else if (MO.isLoBits32())
235 else if (MO.isHiBits64())
237 else if (MO.isLoBits64())
242 switch (MO.getType()) {
243 case MachineOperand::MO_VirtualRegister:
244 if (MO.getVRegValue()) {
246 OutputValue(OS, MO.getVRegValue());
247 if (MO.hasAllocatedReg())
250 if (MO.hasAllocatedReg())
251 OutputReg(OS, MO.getAllocatedRegNum(), MRI);
253 case MachineOperand::MO_CCRegister:
255 OutputValue(OS, MO.getVRegValue());
256 if (MO.hasAllocatedReg()) {
258 OutputReg(OS, MO.getAllocatedRegNum(), MRI);
261 case MachineOperand::MO_MachineRegister:
262 OutputReg(OS, MO.getMachineRegNum(), MRI);
264 case MachineOperand::MO_SignExtendedImmed:
265 OS << (long)MO.getImmedValue();
267 case MachineOperand::MO_UnextendedImmed:
268 OS << (long)MO.getImmedValue();
270 case MachineOperand::MO_PCRelativeDisp: {
271 const Value* opVal = MO.getVRegValue();
272 bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal);
273 OS << "%disp(" << (isLabel? "label " : "addr-of-val ");
274 if (opVal->hasName())
275 OS << opVal->getName();
277 OS << (const void*) opVal;
281 case MachineOperand::MO_MachineBasicBlock:
283 << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName()
284 << "," << (void*)MO.getMachineBasicBlock()->getBasicBlock() << ">";
286 case MachineOperand::MO_FrameIndex:
287 OS << "<fi#" << MO.getFrameIndex() << ">";
289 case MachineOperand::MO_ConstantPoolIndex:
290 OS << "<cp#" << MO.getConstantPoolIndex() << ">";
292 case MachineOperand::MO_GlobalAddress:
293 OS << "<ga:" << ((Value*)MO.getGlobal())->getName() << ">";
295 case MachineOperand::MO_ExternalSymbol:
296 OS << "<es:" << MO.getSymbolName() << ">";
299 assert(0 && "Unrecognized operand type");
306 void MachineInstr::print(std::ostream &OS, const TargetMachine &TM) const {
307 unsigned StartOp = 0;
309 // Specialize printing if op#0 is definition
310 if (getNumOperands() && getOperand(0).isDef() && !getOperand(0).isUse()) {
311 llvm::print(getOperand(0), OS, TM);
313 ++StartOp; // Don't print this operand again!
315 OS << TM.getInstrInfo().getName(getOpcode());
317 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
318 const MachineOperand& mop = getOperand(i);
322 llvm::print(mop, OS, TM);
331 // code for printing implicit references
332 if (getNumImplicitRefs()) {
333 OS << "\tImplicitRefs: ";
334 for(unsigned i = 0, e = getNumImplicitRefs(); i != e; ++i) {
336 OutputValue(OS, getImplicitRef(i));
337 if (getImplicitOp(i).isDef())
338 if (getImplicitOp(i).isUse())
349 std::ostream &operator<<(std::ostream& os, const MachineInstr& MI)
351 os << TargetInstrDescriptors[MI.opCode].Name;
353 for (unsigned i=0, N=MI.getNumOperands(); i < N; i++) {
354 os << "\t" << MI.getOperand(i);
355 if (MI.getOperand(i).isDef())
356 if (MI.getOperand(i).isUse())
362 // code for printing implicit references
363 unsigned NumOfImpRefs = MI.getNumImplicitRefs();
364 if (NumOfImpRefs > 0) {
365 os << "\tImplicit: ";
366 for (unsigned z=0; z < NumOfImpRefs; z++) {
367 OutputValue(os, MI.getImplicitRef(z));
368 if (MI.getImplicitOp(z).isDef())
369 if (MI.getImplicitOp(z).isUse())
380 std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO)
384 else if (MO.isLoBits32())
386 else if (MO.isHiBits64())
388 else if (MO.isLoBits64())
391 switch (MO.getType())
393 case MachineOperand::MO_VirtualRegister:
394 if (MO.hasAllocatedReg())
395 OutputReg(OS, MO.getAllocatedRegNum());
397 if (MO.getVRegValue()) {
398 if (MO.hasAllocatedReg()) OS << "==";
400 OutputValue(OS, MO.getVRegValue());
403 case MachineOperand::MO_CCRegister:
405 OutputValue(OS, MO.getVRegValue());
406 if (MO.hasAllocatedReg()) {
408 OutputReg(OS, MO.getAllocatedRegNum());
411 case MachineOperand::MO_MachineRegister:
412 OutputReg(OS, MO.getMachineRegNum());
414 case MachineOperand::MO_SignExtendedImmed:
415 OS << (long)MO.getImmedValue();
417 case MachineOperand::MO_UnextendedImmed:
418 OS << (long)MO.getImmedValue();
420 case MachineOperand::MO_PCRelativeDisp:
422 const Value* opVal = MO.getVRegValue();
423 bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal);
424 OS << "%disp(" << (isLabel? "label " : "addr-of-val ");
425 if (opVal->hasName())
426 OS << opVal->getName();
428 OS << (const void*) opVal;
432 case MachineOperand::MO_MachineBasicBlock:
434 << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName()
435 << "," << (void*)MO.getMachineBasicBlock()->getBasicBlock() << ">";
437 case MachineOperand::MO_FrameIndex:
438 OS << "<fi#" << MO.getFrameIndex() << ">";
440 case MachineOperand::MO_ConstantPoolIndex:
441 OS << "<cp#" << MO.getConstantPoolIndex() << ">";
443 case MachineOperand::MO_GlobalAddress:
444 OS << "<ga:" << ((Value*)MO.getGlobal())->getName() << ">";
446 case MachineOperand::MO_ExternalSymbol:
447 OS << "<es:" << MO.getSymbolName() << ">";
450 assert(0 && "Unrecognized operand type");
455 (MachineOperand::HIFLAG32 | MachineOperand::LOFLAG32 |
456 MachineOperand::HIFLAG64 | MachineOperand::LOFLAG64))
462 } // End llvm namespace