1 //===-- MachineInstr.cpp --------------------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Methods common to all machine instructions.
12 // FIXME: Now that MachineInstrs have parent pointers, they should always
13 // print themselves using their MachineFunction's TargetMachine.
15 //===----------------------------------------------------------------------===//
17 #include "llvm/CodeGen/MachineInstr.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/Value.h"
20 #include "llvm/Target/TargetMachine.h"
21 #include "llvm/Target/TargetInstrInfo.h"
22 #include "llvm/Target/MRegisterInfo.h"
23 #include "Support/LeakDetector.h"
26 // Global variable holding an array of descriptors for machine instructions.
27 // The actual object needs to be created separately for each target machine.
28 // This variable is initialized and reset by class TargetInstrInfo.
30 // FIXME: This should be a property of the target so that more than one target
31 // at a time can be active...
34 extern const TargetInstrDescriptor *TargetInstrDescriptors;
37 // Constructor for instructions with variable #operands
38 MachineInstr::MachineInstr(short opcode, unsigned numOperands)
41 operands(numOperands, MachineOperand()),
43 // Make sure that we get added to a machine basicblock
44 LeakDetector::addGarbageObject(this);
47 /// MachineInstr ctor - This constructor only does a _reserve_ of the operands,
48 /// not a resize for them. It is expected that if you use this that you call
49 /// add* methods below to fill up the operands, instead of the Set methods.
50 /// Eventually, the "resizing" ctors will be phased out.
52 MachineInstr::MachineInstr(short opcode, unsigned numOperands, bool XX, bool YY)
53 : Opcode(opcode), numImplicitRefs(0), parent(0) {
54 operands.reserve(numOperands);
55 // Make sure that we get added to a machine basicblock
56 LeakDetector::addGarbageObject(this);
59 /// MachineInstr ctor - Work exactly the same as the ctor above, except that the
60 /// MachineInstr is created and added to the end of the specified basic block.
62 MachineInstr::MachineInstr(MachineBasicBlock *MBB, short opcode,
64 : Opcode(opcode), numImplicitRefs(0), parent(0) {
65 assert(MBB && "Cannot use inserting ctor with null basic block!");
66 operands.reserve(numOperands);
67 // Make sure that we get added to a machine basicblock
68 LeakDetector::addGarbageObject(this);
69 MBB->push_back(this); // Add instruction to end of basic block!
72 ///MachineInstr ctor - Copies MachineInstr arg exactly
73 MachineInstr::MachineInstr(const MachineInstr &MI) {
74 Opcode = MI.getOpcode();
75 numImplicitRefs = MI.getNumImplicitRefs();
78 for(unsigned i=0; i < MI.getNumOperands(); ++i)
79 operands.push_back(MachineOperand(MI.getOperand(i)));
83 MachineInstr::~MachineInstr()
85 LeakDetector::removeGarbageObject(this);
88 ///clone - Create a copy of 'this' instruction that is identical in
89 ///all ways except the following: The instruction has no parent The
90 ///instruction has no name
91 MachineInstr* MachineInstr::clone() {
92 MachineInstr* newInst = new MachineInstr(*this);
95 /// OperandComplete - Return true if it's illegal to add a new operand
97 bool MachineInstr::OperandsComplete() const {
98 int NumOperands = TargetInstrDescriptors[Opcode].numOperands;
99 if (NumOperands >= 0 && getNumOperands() >= (unsigned)NumOperands)
100 return true; // Broken: we have all the operands of this instruction!
104 /// replace - Support for replacing opcode and operands of a MachineInstr in
105 /// place. This only resets the size of the operand vector and initializes it.
106 /// The new operands must be set explicitly later.
108 void MachineInstr::replace(short opcode, unsigned numOperands) {
109 assert(getNumImplicitRefs() == 0 &&
110 "This is probably broken because implicit refs are going to be lost.");
113 operands.resize(numOperands, MachineOperand());
117 void MachineInstr::SetMachineOperandVal(unsigned i,
118 MachineOperand::MachineOperandType opTy,
120 assert(i < operands.size()); // may be explicit or implicit op
121 operands[i].opType = opTy;
122 operands[i].contents.value = V;
123 operands[i].regNum = -1;
127 MachineInstr::SetMachineOperandConst(unsigned i,
128 MachineOperand::MachineOperandType opTy,
130 assert(i < getNumOperands()); // must be explicit op
131 assert(TargetInstrDescriptors[Opcode].resultPos != (int) i &&
132 "immed. constant cannot be defined");
134 operands[i].opType = opTy;
135 operands[i].contents.value = NULL;
136 operands[i].contents.immedVal = intValue;
137 operands[i].regNum = -1;
138 operands[i].flags = 0;
141 void MachineInstr::SetMachineOperandReg(unsigned i, int regNum) {
142 assert(i < getNumOperands()); // must be explicit op
144 operands[i].opType = MachineOperand::MO_MachineRegister;
145 operands[i].contents.value = NULL;
146 operands[i].regNum = regNum;
149 // Used only by the SPARC back-end.
150 void MachineInstr::SetRegForOperand(unsigned i, int regNum) {
151 assert(i < getNumOperands()); // must be explicit op
152 operands[i].setRegForValue(regNum);
155 // Used only by the SPARC back-end.
156 void MachineInstr::SetRegForImplicitRef(unsigned i, int regNum) {
157 getImplicitOp(i).setRegForValue(regNum);
160 /// substituteValue - Substitute all occurrences of Value* oldVal with newVal
161 /// in all operands and all implicit refs. If defsOnly == true, substitute defs
164 /// FIXME: Fold this into its single caller, at SparcInstrSelection.cpp:2865,
165 /// or make it a static function in that file.
168 MachineInstr::substituteValue(const Value* oldVal, Value* newVal,
169 bool defsOnly, bool notDefsAndUses,
170 bool& someArgsWereIgnored)
172 assert((!defsOnly || !notDefsAndUses) &&
173 "notDefsAndUses is irrelevant if defsOnly == true.");
175 unsigned numSubst = 0;
177 // Substitute operands
178 for (MachineInstr::val_op_iterator O = begin(), E = end(); O != E; ++O)
181 notDefsAndUses && (O.isDef() && !O.isUse()) ||
182 !notDefsAndUses && O.isDef())
184 O.getMachineOperand().contents.value = newVal;
188 someArgsWereIgnored = true;
190 // Substitute implicit refs
191 for (unsigned i=0, N=getNumImplicitRefs(); i < N; ++i)
192 if (getImplicitRef(i) == oldVal)
194 notDefsAndUses && (getImplicitOp(i).isDef() && !getImplicitOp(i).isUse()) ||
195 !notDefsAndUses && getImplicitOp(i).isDef())
197 getImplicitOp(i).contents.value = newVal;
201 someArgsWereIgnored = true;
206 void MachineInstr::dump() const {
207 std::cerr << " " << *this;
210 static inline std::ostream& OutputValue(std::ostream &os, const Value* val) {
212 os << (void*) val; // print address always
213 if (val && val->hasName())
214 os << " " << val->getName(); // print name also, if available
219 static inline void OutputReg(std::ostream &os, unsigned RegNo,
220 const MRegisterInfo *MRI = 0) {
221 if (!RegNo || MRegisterInfo::isPhysicalRegister(RegNo)) {
223 os << "%" << MRI->get(RegNo).Name;
225 os << "%mreg(" << RegNo << ")";
227 os << "%reg" << RegNo;
230 static void print(const MachineOperand &MO, std::ostream &OS,
231 const TargetMachine &TM) {
232 const MRegisterInfo *MRI = TM.getRegisterInfo();
233 bool CloseParen = true;
236 else if (MO.isLoBits32())
238 else if (MO.isHiBits64())
240 else if (MO.isLoBits64())
245 switch (MO.getType()) {
246 case MachineOperand::MO_VirtualRegister:
247 if (MO.getVRegValue()) {
249 OutputValue(OS, MO.getVRegValue());
250 if (MO.hasAllocatedReg())
253 if (MO.hasAllocatedReg())
254 OutputReg(OS, MO.getReg(), MRI);
256 case MachineOperand::MO_CCRegister:
258 OutputValue(OS, MO.getVRegValue());
259 if (MO.hasAllocatedReg()) {
261 OutputReg(OS, MO.getReg(), MRI);
264 case MachineOperand::MO_MachineRegister:
265 OutputReg(OS, MO.getMachineRegNum(), MRI);
267 case MachineOperand::MO_SignExtendedImmed:
268 OS << (long)MO.getImmedValue();
270 case MachineOperand::MO_UnextendedImmed:
271 OS << (long)MO.getImmedValue();
273 case MachineOperand::MO_PCRelativeDisp: {
274 const Value* opVal = MO.getVRegValue();
275 bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal);
276 OS << "%disp(" << (isLabel? "label " : "addr-of-val ");
277 if (opVal->hasName())
278 OS << opVal->getName();
280 OS << (const void*) opVal;
284 case MachineOperand::MO_MachineBasicBlock:
286 << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName()
287 << "," << (void*)MO.getMachineBasicBlock()->getBasicBlock() << ">";
289 case MachineOperand::MO_FrameIndex:
290 OS << "<fi#" << MO.getFrameIndex() << ">";
292 case MachineOperand::MO_ConstantPoolIndex:
293 OS << "<cp#" << MO.getConstantPoolIndex() << ">";
295 case MachineOperand::MO_GlobalAddress:
296 OS << "<ga:" << ((Value*)MO.getGlobal())->getName() << ">";
298 case MachineOperand::MO_ExternalSymbol:
299 OS << "<es:" << MO.getSymbolName() << ">";
302 assert(0 && "Unrecognized operand type");
309 void MachineInstr::print(std::ostream &OS, const TargetMachine &TM) const {
310 unsigned StartOp = 0;
312 // Specialize printing if op#0 is definition
313 if (getNumOperands() && getOperand(0).isDef() && !getOperand(0).isUse()) {
314 ::print(getOperand(0), OS, TM);
316 ++StartOp; // Don't print this operand again!
318 OS << TM.getInstrInfo().getName(getOpcode());
320 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
321 const MachineOperand& mop = getOperand(i);
325 ::print(mop, OS, TM);
334 // code for printing implicit references
335 if (getNumImplicitRefs()) {
336 OS << "\tImplicitRefs: ";
337 for(unsigned i = 0, e = getNumImplicitRefs(); i != e; ++i) {
339 OutputValue(OS, getImplicitRef(i));
340 if (getImplicitOp(i).isDef())
341 if (getImplicitOp(i).isUse())
352 std::ostream &operator<<(std::ostream &os, const MachineInstr &MI) {
353 // If the instruction is embedded into a basic block, we can find the target
354 // info for the instruction.
355 if (const MachineBasicBlock *MBB = MI.getParent()) {
356 const MachineFunction *MF = MBB->getParent();
357 MI.print(os, MF->getTarget());
361 // Otherwise, print it out in the "raw" format without symbolic register names
363 os << TargetInstrDescriptors[MI.getOpcode()].Name;
365 for (unsigned i=0, N=MI.getNumOperands(); i < N; i++) {
366 os << "\t" << MI.getOperand(i);
367 if (MI.getOperand(i).isDef())
368 if (MI.getOperand(i).isUse())
374 // code for printing implicit references
375 unsigned NumOfImpRefs = MI.getNumImplicitRefs();
376 if (NumOfImpRefs > 0) {
377 os << "\tImplicit: ";
378 for (unsigned z=0; z < NumOfImpRefs; z++) {
379 OutputValue(os, MI.getImplicitRef(z));
380 if (MI.getImplicitOp(z).isDef())
381 if (MI.getImplicitOp(z).isUse())
392 std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO) {
395 else if (MO.isLoBits32())
397 else if (MO.isHiBits64())
399 else if (MO.isLoBits64())
402 switch (MO.getType())
404 case MachineOperand::MO_VirtualRegister:
405 if (MO.hasAllocatedReg())
406 OutputReg(OS, MO.getReg());
408 if (MO.getVRegValue()) {
409 if (MO.hasAllocatedReg()) OS << "==";
411 OutputValue(OS, MO.getVRegValue());
414 case MachineOperand::MO_CCRegister:
416 OutputValue(OS, MO.getVRegValue());
417 if (MO.hasAllocatedReg()) {
419 OutputReg(OS, MO.getReg());
422 case MachineOperand::MO_MachineRegister:
423 OutputReg(OS, MO.getMachineRegNum());
425 case MachineOperand::MO_SignExtendedImmed:
426 OS << (long)MO.getImmedValue();
428 case MachineOperand::MO_UnextendedImmed:
429 OS << (long)MO.getImmedValue();
431 case MachineOperand::MO_PCRelativeDisp:
433 const Value* opVal = MO.getVRegValue();
434 bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal);
435 OS << "%disp(" << (isLabel? "label " : "addr-of-val ");
436 if (opVal->hasName())
437 OS << opVal->getName();
439 OS << (const void*) opVal;
443 case MachineOperand::MO_MachineBasicBlock:
445 << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName()
446 << "," << (void*)MO.getMachineBasicBlock()->getBasicBlock() << ">";
448 case MachineOperand::MO_FrameIndex:
449 OS << "<fi#" << MO.getFrameIndex() << ">";
451 case MachineOperand::MO_ConstantPoolIndex:
452 OS << "<cp#" << MO.getConstantPoolIndex() << ">";
454 case MachineOperand::MO_GlobalAddress:
455 OS << "<ga:" << ((Value*)MO.getGlobal())->getName() << ">";
457 case MachineOperand::MO_ExternalSymbol:
458 OS << "<es:" << MO.getSymbolName() << ">";
461 assert(0 && "Unrecognized operand type");
465 if (MO.isHiBits32() || MO.isLoBits32() || MO.isHiBits64() || MO.isLoBits64())