1 //===-- MachineInstr.cpp --------------------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Methods common to all machine instructions.
12 // FIXME: Now that MachineInstrs have parent pointers, they should always
13 // print themselves using their MachineFunction's TargetMachine.
15 //===----------------------------------------------------------------------===//
17 #include "llvm/CodeGen/MachineInstr.h"
18 #include "llvm/CodeGen/MachineBasicBlock.h"
19 #include "llvm/Value.h"
20 #include "llvm/Target/TargetMachine.h"
21 #include "llvm/Target/TargetInstrInfo.h"
22 #include "llvm/Target/MRegisterInfo.h"
26 // Global variable holding an array of descriptors for machine instructions.
27 // The actual object needs to be created separately for each target machine.
28 // This variable is initialized and reset by class TargetInstrInfo.
30 // FIXME: This should be a property of the target so that more than one target
31 // at a time can be active...
33 extern const TargetInstrDescriptor *TargetInstrDescriptors;
35 // Constructor for instructions with variable #operands
36 MachineInstr::MachineInstr(short opcode, unsigned numOperands)
39 operands(numOperands, MachineOperand()),
43 /// MachineInstr ctor - This constructor only does a _reserve_ of the operands,
44 /// not a resize for them. It is expected that if you use this that you call
45 /// add* methods below to fill up the operands, instead of the Set methods.
46 /// Eventually, the "resizing" ctors will be phased out.
48 MachineInstr::MachineInstr(short opcode, unsigned numOperands, bool XX, bool YY)
49 : Opcode(opcode), numImplicitRefs(0), parent(0) {
50 operands.reserve(numOperands);
53 /// MachineInstr ctor - Work exactly the same as the ctor above, except that the
54 /// MachineInstr is created and added to the end of the specified basic block.
56 MachineInstr::MachineInstr(MachineBasicBlock *MBB, short opcode,
58 : Opcode(opcode), numImplicitRefs(0), parent(0) {
59 assert(MBB && "Cannot use inserting ctor with null basic block!");
60 operands.reserve(numOperands);
61 MBB->push_back(this); // Add instruction to end of basic block!
64 /// OperandComplete - Return true if it's illegal to add a new operand
66 bool MachineInstr::OperandsComplete() const {
67 int NumOperands = TargetInstrDescriptors[Opcode].numOperands;
68 if (NumOperands >= 0 && getNumOperands() >= (unsigned)NumOperands)
69 return true; // Broken: we have all the operands of this instruction!
73 /// replace - Support for replacing opcode and operands of a MachineInstr in
74 /// place. This only resets the size of the operand vector and initializes it.
75 /// The new operands must be set explicitly later.
77 void MachineInstr::replace(short opcode, unsigned numOperands) {
78 assert(getNumImplicitRefs() == 0 &&
79 "This is probably broken because implicit refs are going to be lost.");
82 operands.resize(numOperands, MachineOperand());
85 void MachineInstr::SetMachineOperandVal(unsigned i,
86 MachineOperand::MachineOperandType opTy,
88 assert(i < operands.size()); // may be explicit or implicit op
89 operands[i].opType = opTy;
90 operands[i].value = V;
91 operands[i].regNum = -1;
95 MachineInstr::SetMachineOperandConst(unsigned i,
96 MachineOperand::MachineOperandType opTy,
98 assert(i < getNumOperands()); // must be explicit op
99 assert(TargetInstrDescriptors[Opcode].resultPos != (int) i &&
100 "immed. constant cannot be defined");
102 operands[i].opType = opTy;
103 operands[i].value = NULL;
104 operands[i].immedVal = intValue;
105 operands[i].regNum = -1;
106 operands[i].flags = 0;
109 void MachineInstr::SetMachineOperandReg(unsigned i, int regNum) {
110 assert(i < getNumOperands()); // must be explicit op
112 operands[i].opType = MachineOperand::MO_MachineRegister;
113 operands[i].value = NULL;
114 operands[i].regNum = regNum;
117 // Used only by the SPARC back-end.
118 void MachineInstr::SetRegForOperand(unsigned i, int regNum) {
119 assert(i < getNumOperands()); // must be explicit op
120 operands[i].setRegForValue(regNum);
123 // Used only by the SPARC back-end.
124 void MachineInstr::SetRegForImplicitRef(unsigned i, int regNum) {
125 getImplicitOp(i).setRegForValue(regNum);
128 /// substituteValue - Substitute all occurrences of Value* oldVal with newVal
129 /// in all operands and all implicit refs. If defsOnly == true, substitute defs
132 /// FIXME: Fold this into its single caller, at SparcInstrSelection.cpp:2865,
133 /// or make it a static function in that file.
136 MachineInstr::substituteValue(const Value* oldVal, Value* newVal,
137 bool defsOnly, bool notDefsAndUses,
138 bool& someArgsWereIgnored)
140 assert((!defsOnly || !notDefsAndUses) &&
141 "notDefsAndUses is irrelevant if defsOnly == true.");
143 unsigned numSubst = 0;
145 // Substitute operands
146 for (MachineInstr::val_op_iterator O = begin(), E = end(); O != E; ++O)
149 notDefsAndUses && (O.isDef() && !O.isUse()) ||
150 !notDefsAndUses && O.isDef())
152 O.getMachineOperand().value = newVal;
156 someArgsWereIgnored = true;
158 // Substitute implicit refs
159 for (unsigned i=0, N=getNumImplicitRefs(); i < N; ++i)
160 if (getImplicitRef(i) == oldVal)
162 notDefsAndUses && (getImplicitOp(i).isDef() && !getImplicitOp(i).isUse()) ||
163 !notDefsAndUses && getImplicitOp(i).isDef())
165 getImplicitOp(i).value = newVal;
169 someArgsWereIgnored = true;
174 void MachineInstr::dump() const {
175 std::cerr << " " << *this;
178 static inline std::ostream& OutputValue(std::ostream &os, const Value* val) {
180 os << (void*) val; // print address always
181 if (val && val->hasName())
182 os << " " << val->getName(); // print name also, if available
187 static inline void OutputReg(std::ostream &os, unsigned RegNo,
188 const MRegisterInfo *MRI = 0) {
190 if (RegNo < MRegisterInfo::FirstVirtualRegister)
191 os << "%" << MRI->get(RegNo).Name;
193 os << "%reg" << RegNo;
195 os << "%mreg(" << RegNo << ")";
198 static void print(const MachineOperand &MO, std::ostream &OS,
199 const TargetMachine &TM) {
200 const MRegisterInfo *MRI = TM.getRegisterInfo();
201 bool CloseParen = true;
204 else if (MO.isLoBits32())
206 else if (MO.isHiBits64())
208 else if (MO.isLoBits64())
213 switch (MO.getType()) {
214 case MachineOperand::MO_VirtualRegister:
215 if (MO.getVRegValue()) {
217 OutputValue(OS, MO.getVRegValue());
218 if (MO.hasAllocatedReg())
221 if (MO.hasAllocatedReg())
222 OutputReg(OS, MO.getAllocatedRegNum(), MRI);
224 case MachineOperand::MO_CCRegister:
226 OutputValue(OS, MO.getVRegValue());
227 if (MO.hasAllocatedReg()) {
229 OutputReg(OS, MO.getAllocatedRegNum(), MRI);
232 case MachineOperand::MO_MachineRegister:
233 OutputReg(OS, MO.getMachineRegNum(), MRI);
235 case MachineOperand::MO_SignExtendedImmed:
236 OS << (long)MO.getImmedValue();
238 case MachineOperand::MO_UnextendedImmed:
239 OS << (long)MO.getImmedValue();
241 case MachineOperand::MO_PCRelativeDisp: {
242 const Value* opVal = MO.getVRegValue();
243 bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal);
244 OS << "%disp(" << (isLabel? "label " : "addr-of-val ");
245 if (opVal->hasName())
246 OS << opVal->getName();
248 OS << (const void*) opVal;
252 case MachineOperand::MO_MachineBasicBlock:
254 << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName()
255 << "," << (void*)MO.getMachineBasicBlock()->getBasicBlock() << ">";
257 case MachineOperand::MO_FrameIndex:
258 OS << "<fi#" << MO.getFrameIndex() << ">";
260 case MachineOperand::MO_ConstantPoolIndex:
261 OS << "<cp#" << MO.getConstantPoolIndex() << ">";
263 case MachineOperand::MO_GlobalAddress:
264 OS << "<ga:" << ((Value*)MO.getGlobal())->getName() << ">";
266 case MachineOperand::MO_ExternalSymbol:
267 OS << "<es:" << MO.getSymbolName() << ">";
270 assert(0 && "Unrecognized operand type");
277 void MachineInstr::print(std::ostream &OS, const TargetMachine &TM) const {
278 unsigned StartOp = 0;
280 // Specialize printing if op#0 is definition
281 if (getNumOperands() && getOperand(0).isDef() && !getOperand(0).isUse()) {
282 llvm::print(getOperand(0), OS, TM);
284 ++StartOp; // Don't print this operand again!
286 OS << TM.getInstrInfo().getName(getOpcode());
288 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
289 const MachineOperand& mop = getOperand(i);
293 llvm::print(mop, OS, TM);
302 // code for printing implicit references
303 if (getNumImplicitRefs()) {
304 OS << "\tImplicitRefs: ";
305 for(unsigned i = 0, e = getNumImplicitRefs(); i != e; ++i) {
307 OutputValue(OS, getImplicitRef(i));
308 if (getImplicitOp(i).isDef())
309 if (getImplicitOp(i).isUse())
319 std::ostream &operator<<(std::ostream& os, const MachineInstr& MI) {
320 os << TargetInstrDescriptors[MI.getOpcode()].Name;
322 for (unsigned i=0, N=MI.getNumOperands(); i < N; i++) {
323 os << "\t" << MI.getOperand(i);
324 if (MI.getOperand(i).isDef())
325 if (MI.getOperand(i).isUse())
331 // code for printing implicit references
332 unsigned NumOfImpRefs = MI.getNumImplicitRefs();
333 if (NumOfImpRefs > 0) {
334 os << "\tImplicit: ";
335 for (unsigned z=0; z < NumOfImpRefs; z++) {
336 OutputValue(os, MI.getImplicitRef(z));
337 if (MI.getImplicitOp(z).isDef())
338 if (MI.getImplicitOp(z).isUse())
349 std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO) {
352 else if (MO.isLoBits32())
354 else if (MO.isHiBits64())
356 else if (MO.isLoBits64())
359 switch (MO.getType())
361 case MachineOperand::MO_VirtualRegister:
362 if (MO.hasAllocatedReg())
363 OutputReg(OS, MO.getAllocatedRegNum());
365 if (MO.getVRegValue()) {
366 if (MO.hasAllocatedReg()) OS << "==";
368 OutputValue(OS, MO.getVRegValue());
371 case MachineOperand::MO_CCRegister:
373 OutputValue(OS, MO.getVRegValue());
374 if (MO.hasAllocatedReg()) {
376 OutputReg(OS, MO.getAllocatedRegNum());
379 case MachineOperand::MO_MachineRegister:
380 OutputReg(OS, MO.getMachineRegNum());
382 case MachineOperand::MO_SignExtendedImmed:
383 OS << (long)MO.getImmedValue();
385 case MachineOperand::MO_UnextendedImmed:
386 OS << (long)MO.getImmedValue();
388 case MachineOperand::MO_PCRelativeDisp:
390 const Value* opVal = MO.getVRegValue();
391 bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal);
392 OS << "%disp(" << (isLabel? "label " : "addr-of-val ");
393 if (opVal->hasName())
394 OS << opVal->getName();
396 OS << (const void*) opVal;
400 case MachineOperand::MO_MachineBasicBlock:
402 << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName()
403 << "," << (void*)MO.getMachineBasicBlock()->getBasicBlock() << ">";
405 case MachineOperand::MO_FrameIndex:
406 OS << "<fi#" << MO.getFrameIndex() << ">";
408 case MachineOperand::MO_ConstantPoolIndex:
409 OS << "<cp#" << MO.getConstantPoolIndex() << ">";
411 case MachineOperand::MO_GlobalAddress:
412 OS << "<ga:" << ((Value*)MO.getGlobal())->getName() << ">";
414 case MachineOperand::MO_ExternalSymbol:
415 OS << "<es:" << MO.getSymbolName() << ">";
418 assert(0 && "Unrecognized operand type");
423 (MachineOperand::HIFLAG32 | MachineOperand::LOFLAG32 |
424 MachineOperand::HIFLAG64 | MachineOperand::LOFLAG64))
430 } // End llvm namespace