1 //===-- MachineInstr.cpp --------------------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Methods common to all machine instructions.
12 // FIXME: Now that MachineInstrs have parent pointers, they should always
13 // print themselves using their MachineFunction's TargetMachine.
15 //===----------------------------------------------------------------------===//
17 #include "llvm/CodeGen/MachineInstr.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/Value.h"
20 #include "llvm/Target/TargetMachine.h"
21 #include "llvm/Target/TargetInstrInfo.h"
22 #include "llvm/Target/MRegisterInfo.h"
23 #include "llvm/Support/LeakDetector.h"
28 // Global variable holding an array of descriptors for machine instructions.
29 // The actual object needs to be created separately for each target machine.
30 // This variable is initialized and reset by class TargetInstrInfo.
32 // FIXME: This should be a property of the target so that more than one target
33 // at a time can be active...
36 extern const TargetInstrDescriptor *TargetInstrDescriptors;
39 // Constructor for instructions with variable #operands
40 MachineInstr::MachineInstr(short opcode, unsigned numOperands)
42 operands(numOperands, MachineOperand()),
44 // Make sure that we get added to a machine basicblock
45 LeakDetector::addGarbageObject(this);
48 /// MachineInstr ctor - This constructor only does a _reserve_ of the operands,
49 /// not a resize for them. It is expected that if you use this that you call
50 /// add* methods below to fill up the operands, instead of the Set methods.
51 /// Eventually, the "resizing" ctors will be phased out.
53 MachineInstr::MachineInstr(short opcode, unsigned numOperands, bool XX, bool YY)
54 : Opcode(opcode), parent(0) {
55 operands.reserve(numOperands);
56 // Make sure that we get added to a machine basicblock
57 LeakDetector::addGarbageObject(this);
60 /// MachineInstr ctor - Work exactly the same as the ctor above, except that the
61 /// MachineInstr is created and added to the end of the specified basic block.
63 MachineInstr::MachineInstr(MachineBasicBlock *MBB, short opcode,
65 : Opcode(opcode), parent(0) {
66 assert(MBB && "Cannot use inserting ctor with null basic block!");
67 operands.reserve(numOperands);
68 // Make sure that we get added to a machine basicblock
69 LeakDetector::addGarbageObject(this);
70 MBB->push_back(this); // Add instruction to end of basic block!
73 /// MachineInstr ctor - Copies MachineInstr arg exactly
75 MachineInstr::MachineInstr(const MachineInstr &MI) {
76 Opcode = MI.getOpcode();
77 operands.reserve(MI.getNumOperands());
80 for (unsigned i = 0; i < MI.getNumOperands(); ++i)
81 operands.push_back(MachineOperand(MI.getOperand(i)));
83 // Set parent, next, and prev to null
90 MachineInstr::~MachineInstr() {
91 LeakDetector::removeGarbageObject(this);
94 /// clone - Create a copy of 'this' instruction that is identical in all ways
95 /// except the following: the new instruction has no parent and it has no name
97 MachineInstr* MachineInstr::clone() const {
98 return new MachineInstr(*this);
101 /// removeFromParent - This method unlinks 'this' from the containing basic
102 /// block, and returns it, but does not delete it.
103 MachineInstr *MachineInstr::removeFromParent() {
104 assert(getParent() && "Not embedded in a basic block!");
105 getParent()->remove(this);
110 /// OperandComplete - Return true if it's illegal to add a new operand
112 bool MachineInstr::OperandsComplete() const {
113 int NumOperands = TargetInstrDescriptors[Opcode].numOperands;
114 if (NumOperands >= 0 && getNumOperands() >= (unsigned)NumOperands)
115 return true; // Broken: we have all the operands of this instruction!
119 void MachineInstr::SetMachineOperandVal(unsigned i,
120 MachineOperand::MachineOperandType opTy,
122 assert(i < operands.size()); // may be explicit or implicit op
123 operands[i].opType = opTy;
124 operands[i].contents.value = V;
125 operands[i].extra.regNum = -1;
129 MachineInstr::SetMachineOperandConst(unsigned i,
130 MachineOperand::MachineOperandType opTy,
132 assert(i < getNumOperands()); // must be explicit op
134 operands[i].opType = opTy;
135 operands[i].contents.value = NULL;
136 operands[i].contents.immedVal = intValue;
137 operands[i].extra.regNum = -1;
138 operands[i].flags = 0;
141 void MachineInstr::SetMachineOperandReg(unsigned i, int regNum) {
142 assert(i < getNumOperands()); // must be explicit op
144 operands[i].opType = MachineOperand::MO_MachineRegister;
145 operands[i].contents.value = NULL;
146 operands[i].extra.regNum = regNum;
149 void MachineInstr::dump() const {
150 std::cerr << " " << *this;
153 static inline std::ostream& OutputValue(std::ostream &os, const Value* val) {
155 os << (void*) val; // print address always
156 if (val && val->hasName())
157 os << " " << val->getName(); // print name also, if available
162 static inline void OutputReg(std::ostream &os, unsigned RegNo,
163 const MRegisterInfo *MRI = 0) {
164 if (!RegNo || MRegisterInfo::isPhysicalRegister(RegNo)) {
166 os << "%" << MRI->get(RegNo).Name;
168 os << "%mreg(" << RegNo << ")";
170 os << "%reg" << RegNo;
173 static void print(const MachineOperand &MO, std::ostream &OS,
174 const TargetMachine *TM) {
175 const MRegisterInfo *MRI = 0;
177 if (TM) MRI = TM->getRegisterInfo();
179 bool CloseParen = true;
182 else if (MO.isLoBits32())
184 else if (MO.isHiBits64())
186 else if (MO.isLoBits64())
191 switch (MO.getType()) {
192 case MachineOperand::MO_VirtualRegister:
193 if (MO.getVRegValue()) {
195 OutputValue(OS, MO.getVRegValue());
196 if (MO.hasAllocatedReg())
199 if (MO.hasAllocatedReg())
200 OutputReg(OS, MO.getReg(), MRI);
202 case MachineOperand::MO_MachineRegister:
203 OutputReg(OS, MO.getMachineRegNum(), MRI);
205 case MachineOperand::MO_SignExtendedImmed:
206 OS << (long)MO.getImmedValue();
208 case MachineOperand::MO_UnextendedImmed:
209 OS << (long)MO.getImmedValue();
211 case MachineOperand::MO_MachineBasicBlock:
213 << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName()
214 << "," << (void*)MO.getMachineBasicBlock() << ">";
216 case MachineOperand::MO_FrameIndex:
217 OS << "<fi#" << MO.getFrameIndex() << ">";
219 case MachineOperand::MO_ConstantPoolIndex:
220 OS << "<cp#" << MO.getConstantPoolIndex() << ">";
222 case MachineOperand::MO_JumpTableIndex:
223 OS << "<jt#" << MO.getJumpTableIndex() << ">";
225 case MachineOperand::MO_GlobalAddress:
226 OS << "<ga:" << ((Value*)MO.getGlobal())->getName();
227 if (MO.getOffset()) OS << "+" << MO.getOffset();
230 case MachineOperand::MO_ExternalSymbol:
231 OS << "<es:" << MO.getSymbolName();
232 if (MO.getOffset()) OS << "+" << MO.getOffset();
236 assert(0 && "Unrecognized operand type");
243 void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
244 unsigned StartOp = 0;
246 // Specialize printing if op#0 is definition
247 if (getNumOperands() && getOperand(0).isDef() && !getOperand(0).isUse()) {
248 ::print(getOperand(0), OS, TM);
250 ++StartOp; // Don't print this operand again!
253 // Must check if Target machine is not null because machine BB could not
254 // be attached to a Machine function yet
256 OS << TM->getInstrInfo()->getName(getOpcode());
258 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
259 const MachineOperand& mop = getOperand(i);
263 ::print(mop, OS, TM);
276 std::ostream &operator<<(std::ostream &os, const MachineInstr &MI) {
277 // If the instruction is embedded into a basic block, we can find the target
278 // info for the instruction.
279 if (const MachineBasicBlock *MBB = MI.getParent()) {
280 const MachineFunction *MF = MBB->getParent();
282 MI.print(os, &MF->getTarget());
288 // Otherwise, print it out in the "raw" format without symbolic register names
290 os << TargetInstrDescriptors[MI.getOpcode()].Name;
292 for (unsigned i = 0, N = MI.getNumOperands(); i < N; i++) {
293 os << "\t" << MI.getOperand(i);
294 if (MI.getOperand(i).isDef())
295 if (MI.getOperand(i).isUse())
304 std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO) {
307 else if (MO.isLoBits32())
309 else if (MO.isHiBits64())
311 else if (MO.isLoBits64())
314 switch (MO.getType()) {
315 case MachineOperand::MO_VirtualRegister:
316 if (MO.hasAllocatedReg())
317 OutputReg(OS, MO.getReg());
319 if (MO.getVRegValue()) {
320 if (MO.hasAllocatedReg()) OS << "==";
322 OutputValue(OS, MO.getVRegValue());
325 case MachineOperand::MO_MachineRegister:
326 OutputReg(OS, MO.getMachineRegNum());
328 case MachineOperand::MO_SignExtendedImmed:
329 OS << (long)MO.getImmedValue();
331 case MachineOperand::MO_UnextendedImmed:
332 OS << (long)MO.getImmedValue();
334 case MachineOperand::MO_MachineBasicBlock:
336 << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName()
337 << "@" << (void*)MO.getMachineBasicBlock() << ">";
339 case MachineOperand::MO_FrameIndex:
340 OS << "<fi#" << MO.getFrameIndex() << ">";
342 case MachineOperand::MO_ConstantPoolIndex:
343 OS << "<cp#" << MO.getConstantPoolIndex() << ">";
345 case MachineOperand::MO_JumpTableIndex:
346 OS << "<jt#" << MO.getJumpTableIndex() << ">";
348 case MachineOperand::MO_GlobalAddress:
349 OS << "<ga:" << ((Value*)MO.getGlobal())->getName() << ">";
351 case MachineOperand::MO_ExternalSymbol:
352 OS << "<es:" << MO.getSymbolName() << ">";
355 assert(0 && "Unrecognized operand type");
359 if (MO.isHiBits32() || MO.isLoBits32() || MO.isHiBits64() || MO.isLoBits64())