1 //===-- MachineInstr.cpp --------------------------------------------------===//
3 //===----------------------------------------------------------------------===//
5 #include "llvm/CodeGen/MachineInstr.h"
6 #include "llvm/CodeGen/MachineBasicBlock.h"
7 #include "llvm/Value.h"
8 #include "llvm/Target/TargetMachine.h"
9 #include "llvm/Target/TargetInstrInfo.h"
10 #include "llvm/Target/MRegisterInfo.h"
12 // Global variable holding an array of descriptors for machine instructions.
13 // The actual object needs to be created separately for each target machine.
14 // This variable is initialized and reset by class TargetInstrInfo.
16 // FIXME: This should be a property of the target so that more than one target
17 // at a time can be active...
19 extern const TargetInstrDescriptor *TargetInstrDescriptors;
21 // Constructor for instructions with variable #operands
22 MachineInstr::MachineInstr(MachineOpCode OpCode, unsigned numOperands)
25 operands(numOperands, MachineOperand()),
30 /// MachineInstr ctor - This constructor only does a _reserve_ of the operands,
31 /// not a resize for them. It is expected that if you use this that you call
32 /// add* methods below to fill up the operands, instead of the Set methods.
33 /// Eventually, the "resizing" ctors will be phased out.
35 MachineInstr::MachineInstr(MachineOpCode Opcode, unsigned numOperands,
41 operands.reserve(numOperands);
44 /// MachineInstr ctor - Work exactly the same as the ctor above, except that the
45 /// MachineInstr is created and added to the end of the specified basic block.
47 MachineInstr::MachineInstr(MachineBasicBlock *MBB, MachineOpCode Opcode,
53 assert(MBB && "Cannot use inserting ctor with null basic block!");
54 operands.reserve(numOperands);
55 MBB->push_back(this); // Add instruction to end of basic block!
59 // OperandComplete - Return true if it's illegal to add a new operand
60 bool MachineInstr::OperandsComplete() const
62 int NumOperands = TargetInstrDescriptors[opCode].numOperands;
63 if (NumOperands >= 0 && getNumOperands() >= (unsigned)NumOperands)
64 return true; // Broken: we have all the operands of this instruction!
70 // Support for replacing opcode and operands of a MachineInstr in place.
71 // This only resets the size of the operand vector and initializes it.
72 // The new operands must be set explicitly later.
74 void MachineInstr::replace(MachineOpCode Opcode, unsigned numOperands)
76 assert(getNumImplicitRefs() == 0 &&
77 "This is probably broken because implicit refs are going to be lost.");
80 operands.resize(numOperands, MachineOperand());
84 MachineInstr::SetMachineOperandVal(unsigned i,
85 MachineOperand::MachineOperandType opType,
90 assert(i < operands.size()); // may be explicit or implicit op
91 operands[i].opType = opType;
92 operands[i].value = V;
93 operands[i].regNum = -1;
96 operands[i].flags = MachineOperand::DEFUSEFLAG;
97 else if (isdef || TargetInstrDescriptors[opCode].resultPos == (int) i)
98 operands[i].flags = MachineOperand::DEFONLYFLAG;
100 operands[i].flags = 0;
104 MachineInstr::SetMachineOperandConst(unsigned i,
105 MachineOperand::MachineOperandType operandType,
108 assert(i < getNumOperands()); // must be explicit op
109 assert(TargetInstrDescriptors[opCode].resultPos != (int) i &&
110 "immed. constant cannot be defined");
112 operands[i].opType = operandType;
113 operands[i].value = NULL;
114 operands[i].immedVal = intValue;
115 operands[i].regNum = -1;
116 operands[i].flags = 0;
120 MachineInstr::SetMachineOperandReg(unsigned i,
123 assert(i < getNumOperands()); // must be explicit op
125 operands[i].opType = MachineOperand::MO_MachineRegister;
126 operands[i].value = NULL;
127 operands[i].regNum = regNum;
129 if (isdef || TargetInstrDescriptors[opCode].resultPos == (int) i)
130 operands[i].flags = MachineOperand::DEFONLYFLAG;
132 operands[i].flags = 0;
134 insertUsedReg(regNum);
138 MachineInstr::SetRegForOperand(unsigned i, int regNum)
140 assert(i < getNumOperands()); // must be explicit op
141 operands[i].setRegForValue(regNum);
142 insertUsedReg(regNum);
146 MachineInstr::SetRegForImplicitRef(unsigned i, int regNum)
148 getImplicitOp(i).setRegForValue(regNum);
149 insertUsedReg(regNum);
153 // Subsitute all occurrences of Value* oldVal with newVal in all operands
154 // and all implicit refs.
155 // If defsOnly == true, substitute defs only.
157 MachineInstr::substituteValue(const Value* oldVal, Value* newVal,
158 bool defsOnly, bool notDefsAndUses,
159 bool& someArgsWereIgnored)
161 assert((defsOnly || !notDefsAndUses) &&
162 "notDefsAndUses is irrelevant if defsOnly == false.");
164 unsigned numSubst = 0;
166 // Subsitute operands
167 for (MachineInstr::val_op_iterator O = begin(), E = end(); O != E; ++O)
170 notDefsAndUses && O.isDefOnly() ||
171 !notDefsAndUses && !O.isUseOnly())
173 O.getMachineOperand().value = newVal;
177 someArgsWereIgnored = true;
179 // Subsitute implicit refs
180 for (unsigned i=0, N=getNumImplicitRefs(); i < N; ++i)
181 if (getImplicitRef(i) == oldVal)
183 notDefsAndUses && getImplicitOp(i).opIsDefOnly() ||
184 !notDefsAndUses && !getImplicitOp(i).opIsUse())
186 getImplicitOp(i).value = newVal;
190 someArgsWereIgnored = true;
197 MachineInstr::dump() const
199 std::cerr << " " << *this;
202 static inline std::ostream&
203 OutputValue(std::ostream &os, const Value* val)
206 os << (void*) val; // print address always
207 if (val && val->hasName())
208 os << " " << val->getName() << ")"; // print name also, if available
212 static inline void OutputReg(std::ostream &os, unsigned RegNo,
213 const MRegisterInfo *MRI = 0) {
215 if (RegNo < MRegisterInfo::FirstVirtualRegister)
216 os << "%" << MRI->get(RegNo).Name;
218 os << "%reg" << RegNo;
220 os << "%mreg(" << RegNo << ")";
223 static void print(const MachineOperand &MO, std::ostream &OS,
224 const TargetMachine &TM) {
225 const MRegisterInfo *MRI = TM.getRegisterInfo();
226 bool CloseParen = true;
229 else if (MO.opLoBits32())
231 else if (MO.opHiBits64())
233 else if (MO.opLoBits64())
238 switch (MO.getType()) {
239 case MachineOperand::MO_VirtualRegister:
240 if (MO.getVRegValue()) {
242 OutputValue(OS, MO.getVRegValue());
243 if (MO.hasAllocatedReg())
246 if (MO.hasAllocatedReg())
247 OutputReg(OS, MO.getAllocatedRegNum(), MRI);
249 case MachineOperand::MO_CCRegister:
251 OutputValue(OS, MO.getVRegValue());
252 if (MO.hasAllocatedReg()) {
254 OutputReg(OS, MO.getAllocatedRegNum(), MRI);
257 case MachineOperand::MO_MachineRegister:
258 OutputReg(OS, MO.getMachineRegNum(), MRI);
260 case MachineOperand::MO_SignExtendedImmed:
261 OS << (long)MO.getImmedValue();
263 case MachineOperand::MO_UnextendedImmed:
264 OS << (long)MO.getImmedValue();
266 case MachineOperand::MO_PCRelativeDisp: {
267 const Value* opVal = MO.getVRegValue();
268 bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal);
269 OS << "%disp(" << (isLabel? "label " : "addr-of-val ");
270 if (opVal->hasName())
271 OS << opVal->getName();
273 OS << (const void*) opVal;
277 case MachineOperand::MO_MachineBasicBlock:
279 << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName()
280 << "," << (void*)MO.getMachineBasicBlock()->getBasicBlock() << ">";
282 case MachineOperand::MO_FrameIndex:
283 OS << "<fi#" << MO.getFrameIndex() << ">";
285 case MachineOperand::MO_ConstantPoolIndex:
286 OS << "<cp#" << MO.getConstantPoolIndex() << ">";
288 case MachineOperand::MO_GlobalAddress:
289 OS << "<ga:" << ((Value*)MO.getGlobal())->getName() << ">";
291 case MachineOperand::MO_ExternalSymbol:
292 OS << "<es:" << MO.getSymbolName() << ">";
295 assert(0 && "Unrecognized operand type");
302 void MachineInstr::print(std::ostream &OS, const TargetMachine &TM) const {
303 unsigned StartOp = 0;
305 // Specialize printing if op#0 is definition
306 if (getNumOperands() &&
307 (getOperand(0).opIsDefOnly() || getOperand(0).opIsDefAndUse())) {
308 ::print(getOperand(0), OS, TM);
310 ++StartOp; // Don't print this operand again!
312 OS << TM.getInstrInfo().getName(getOpcode());
314 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
315 const MachineOperand& mop = getOperand(i);
319 ::print(mop, OS, TM);
321 if (mop.opIsDefAndUse())
323 else if (mop.opIsDefOnly())
327 // code for printing implict references
328 if (getNumImplicitRefs()) {
329 OS << "\tImplicitRefs: ";
330 for(unsigned i = 0, e = getNumImplicitRefs(); i != e; ++i) {
332 OutputValue(OS, getImplicitRef(i));
333 if (getImplicitOp(i).opIsDefAndUse())
335 else if (getImplicitOp(i).opIsDefOnly())
344 std::ostream &operator<<(std::ostream& os, const MachineInstr& MI)
346 os << TargetInstrDescriptors[MI.opCode].Name;
348 for (unsigned i=0, N=MI.getNumOperands(); i < N; i++) {
349 os << "\t" << MI.getOperand(i);
350 if (MI.getOperand(i).opIsDefOnly())
352 if (MI.getOperand(i).opIsDefAndUse())
356 // code for printing implict references
357 unsigned NumOfImpRefs = MI.getNumImplicitRefs();
358 if (NumOfImpRefs > 0) {
359 os << "\tImplicit: ";
360 for (unsigned z=0; z < NumOfImpRefs; z++) {
361 OutputValue(os, MI.getImplicitRef(z));
362 if (MI.getImplicitOp(z).opIsDefOnly()) os << "<d>";
363 if (MI.getImplicitOp(z).opIsDefAndUse()) os << "<d&u>";
371 std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO)
375 else if (MO.opLoBits32())
377 else if (MO.opHiBits64())
379 else if (MO.opLoBits64())
382 switch (MO.getType())
384 case MachineOperand::MO_VirtualRegister:
385 if (MO.hasAllocatedReg())
386 OutputReg(OS, MO.getAllocatedRegNum());
388 if (MO.getVRegValue()) {
389 if (MO.hasAllocatedReg()) OS << "==";
391 OutputValue(OS, MO.getVRegValue());
394 case MachineOperand::MO_CCRegister:
396 OutputValue(OS, MO.getVRegValue());
397 if (MO.hasAllocatedReg()) {
399 OutputReg(OS, MO.getAllocatedRegNum());
402 case MachineOperand::MO_MachineRegister:
403 OutputReg(OS, MO.getMachineRegNum());
405 case MachineOperand::MO_SignExtendedImmed:
406 OS << (long)MO.getImmedValue();
408 case MachineOperand::MO_UnextendedImmed:
409 OS << (long)MO.getImmedValue();
411 case MachineOperand::MO_PCRelativeDisp:
413 const Value* opVal = MO.getVRegValue();
414 bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal);
415 OS << "%disp(" << (isLabel? "label " : "addr-of-val ");
416 if (opVal->hasName())
417 OS << opVal->getName();
419 OS << (const void*) opVal;
423 case MachineOperand::MO_MachineBasicBlock:
425 << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName()
426 << "," << (void*)MO.getMachineBasicBlock()->getBasicBlock() << ">";
428 case MachineOperand::MO_FrameIndex:
429 OS << "<fi#" << MO.getFrameIndex() << ">";
431 case MachineOperand::MO_ConstantPoolIndex:
432 OS << "<cp#" << MO.getConstantPoolIndex() << ">";
434 case MachineOperand::MO_GlobalAddress:
435 OS << "<ga:" << ((Value*)MO.getGlobal())->getName() << ">";
437 case MachineOperand::MO_ExternalSymbol:
438 OS << "<es:" << MO.getSymbolName() << ">";
441 assert(0 && "Unrecognized operand type");
446 (MachineOperand::HIFLAG32 | MachineOperand::LOFLAG32 |
447 MachineOperand::HIFLAG64 | MachineOperand::LOFLAG64))