1 //===-- MachineInstr.cpp --------------------------------------------------===//
3 //===----------------------------------------------------------------------===//
5 #include "llvm/CodeGen/MachineInstr.h"
6 #include "llvm/CodeGen/MachineBasicBlock.h"
7 #include "llvm/Value.h"
8 #include "llvm/Target/TargetMachine.h"
9 #include "llvm/Target/TargetInstrInfo.h"
10 #include "llvm/Target/MRegisterInfo.h"
14 // Global variable holding an array of descriptors for machine instructions.
15 // The actual object needs to be created separately for each target machine.
16 // This variable is initialized and reset by class TargetInstrInfo.
18 // FIXME: This should be a property of the target so that more than one target
19 // at a time can be active...
21 extern const TargetInstrDescriptor *TargetInstrDescriptors;
23 // Constructor for instructions with variable #operands
24 MachineInstr::MachineInstr(MachineOpCode OpCode, unsigned numOperands)
26 operands(numOperands, MachineOperand()),
31 /// MachineInstr ctor - This constructor only does a _reserve_ of the operands,
32 /// not a resize for them. It is expected that if you use this that you call
33 /// add* methods below to fill up the operands, instead of the Set methods.
34 /// Eventually, the "resizing" ctors will be phased out.
36 MachineInstr::MachineInstr(MachineOpCode Opcode, unsigned numOperands,
41 operands.reserve(numOperands);
44 /// MachineInstr ctor - Work exactly the same as the ctor above, except that the
45 /// MachineInstr is created and added to the end of the specified basic block.
47 MachineInstr::MachineInstr(MachineBasicBlock *MBB, MachineOpCode Opcode,
52 assert(MBB && "Cannot use inserting ctor with null basic block!");
53 operands.reserve(numOperands);
54 MBB->push_back(this); // Add instruction to end of basic block!
58 // OperandComplete - Return true if it's illegal to add a new operand
59 bool MachineInstr::OperandsComplete() const
61 int NumOperands = TargetInstrDescriptors[opCode].numOperands;
62 if (NumOperands >= 0 && getNumOperands() >= (unsigned)NumOperands)
63 return true; // Broken!
69 // Support for replacing opcode and operands of a MachineInstr in place.
70 // This only resets the size of the operand vector and initializes it.
71 // The new operands must be set explicitly later.
73 void MachineInstr::replace(MachineOpCode Opcode, unsigned numOperands)
75 assert(getNumImplicitRefs() == 0 &&
76 "This is probably broken because implicit refs are going to be lost.");
79 operands.resize(numOperands, MachineOperand());
83 MachineInstr::SetMachineOperandVal(unsigned i,
84 MachineOperand::MachineOperandType opType,
89 assert(i < operands.size()); // may be explicit or implicit op
90 operands[i].opType = opType;
91 operands[i].value = V;
92 operands[i].regNum = -1;
95 operands[i].flags = MachineOperand::DEFUSEFLAG;
96 else if (isdef || TargetInstrDescriptors[opCode].resultPos == (int) i)
97 operands[i].flags = MachineOperand::DEFFLAG;
99 operands[i].flags = 0;
103 MachineInstr::SetMachineOperandConst(unsigned i,
104 MachineOperand::MachineOperandType operandType,
107 assert(i < getNumOperands()); // must be explicit op
108 assert(TargetInstrDescriptors[opCode].resultPos != (int) i &&
109 "immed. constant cannot be defined");
111 operands[i].opType = operandType;
112 operands[i].value = NULL;
113 operands[i].immedVal = intValue;
114 operands[i].regNum = -1;
115 operands[i].flags = 0;
119 MachineInstr::SetMachineOperandReg(unsigned i,
122 assert(i < getNumOperands()); // must be explicit op
124 operands[i].opType = MachineOperand::MO_MachineRegister;
125 operands[i].value = NULL;
126 operands[i].regNum = regNum;
128 if (isdef || TargetInstrDescriptors[opCode].resultPos == (int) i)
129 operands[i].flags = MachineOperand::DEFFLAG;
131 operands[i].flags = 0;
133 insertUsedReg(regNum);
137 MachineInstr::SetRegForOperand(unsigned i, int regNum)
139 assert(i < getNumOperands()); // must be explicit op
140 operands[i].setRegForValue(regNum);
141 insertUsedReg(regNum);
145 // Subsitute all occurrences of Value* oldVal with newVal in all operands
146 // and all implicit refs. If defsOnly == true, substitute defs only.
148 MachineInstr::substituteValue(const Value* oldVal, Value* newVal, bool defsOnly)
150 unsigned numSubst = 0;
152 // Subsitute operands
153 for (MachineInstr::val_op_iterator O = begin(), E = end(); O != E; ++O)
155 if (!defsOnly || O.isDef())
157 O.getMachineOperand().value = newVal;
161 // Subsitute implicit refs
162 for (unsigned i=0, N=getNumImplicitRefs(); i < N; ++i)
163 if (getImplicitRef(i) == oldVal)
164 if (!defsOnly || implicitRefIsDefined(i))
166 getImplicitOp(i).value = newVal;
175 MachineInstr::dump() const
177 cerr << " " << *this;
180 static inline std::ostream&
181 OutputValue(std::ostream &os, const Value* val)
184 if (val && val->hasName())
185 return os << val->getName() << ")";
187 return os << (void*) val << ")"; // print address only
190 static inline void OutputReg(std::ostream &os, unsigned RegNo,
191 const MRegisterInfo *MRI = 0) {
193 if (RegNo < MRegisterInfo::FirstVirtualRegister)
194 os << "%" << MRI->get(RegNo).Name;
196 os << "%reg" << RegNo;
198 os << "%mreg(" << RegNo << ")";
201 static void print(const MachineOperand &MO, std::ostream &OS,
202 const TargetMachine &TM) {
203 const MRegisterInfo *MRI = TM.getRegisterInfo();
204 bool CloseParen = true;
207 else if (MO.opLoBits32())
209 else if (MO.opHiBits64())
211 else if (MO.opLoBits64())
216 switch (MO.getType()) {
217 case MachineOperand::MO_VirtualRegister:
218 if (MO.getVRegValue()) {
220 OutputValue(OS, MO.getVRegValue());
221 if (MO.hasAllocatedReg())
224 if (MO.hasAllocatedReg())
225 OutputReg(OS, MO.getAllocatedRegNum(), MRI);
227 case MachineOperand::MO_CCRegister:
229 OutputValue(OS, MO.getVRegValue());
230 if (MO.hasAllocatedReg()) {
232 OutputReg(OS, MO.getAllocatedRegNum(), MRI);
235 case MachineOperand::MO_MachineRegister:
236 OutputReg(OS, MO.getMachineRegNum(), MRI);
238 case MachineOperand::MO_SignExtendedImmed:
239 OS << (long)MO.getImmedValue();
241 case MachineOperand::MO_UnextendedImmed:
242 OS << (long)MO.getImmedValue();
244 case MachineOperand::MO_PCRelativeDisp: {
245 const Value* opVal = MO.getVRegValue();
246 bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal);
247 OS << "%disp(" << (isLabel? "label " : "addr-of-val ");
248 if (opVal->hasName())
249 OS << opVal->getName();
251 OS << (const void*) opVal;
255 case MachineOperand::MO_MachineBasicBlock:
257 << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName()
258 << "," << (void*)MO.getMachineBasicBlock()->getBasicBlock() << ">";
260 case MachineOperand::MO_FrameIndex:
261 OS << "<fi#" << MO.getFrameIndex() << ">";
263 case MachineOperand::MO_ConstantPoolIndex:
264 OS << "<cp#" << MO.getConstantPoolIndex() << ">";
266 case MachineOperand::MO_GlobalAddress:
267 OS << "<ga:" << ((Value*)MO.getGlobal())->getName() << ">";
269 case MachineOperand::MO_ExternalSymbol:
270 OS << "<es:" << MO.getSymbolName() << ">";
273 assert(0 && "Unrecognized operand type");
280 void MachineInstr::print(std::ostream &OS, const TargetMachine &TM) const {
281 unsigned StartOp = 0;
283 // Specialize printing if op#0 is definition
284 if (getNumOperands() && operandIsDefined(0)) {
285 ::print(getOperand(0), OS, TM);
287 ++StartOp; // Don't print this operand again!
289 OS << TM.getInstrInfo().getName(getOpcode());
291 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
295 ::print(getOperand(i), OS, TM);
297 if (operandIsDefinedAndUsed(i))
299 else if (operandIsDefined(i))
303 // code for printing implict references
304 if (getNumImplicitRefs()) {
305 OS << "\tImplicitRefs: ";
306 for(unsigned i = 0, e = getNumImplicitRefs(); i != e; ++i) {
308 OutputValue(OS, getImplicitRef(i));
309 if (implicitRefIsDefinedAndUsed(i))
311 else if (implicitRefIsDefined(i))
320 std::ostream &operator<<(std::ostream& os, const MachineInstr& MI)
322 os << TargetInstrDescriptors[MI.opCode].Name;
324 for (unsigned i=0, N=MI.getNumOperands(); i < N; i++) {
325 os << "\t" << MI.getOperand(i);
326 if (MI.operandIsDefined(i))
328 if (MI.operandIsDefinedAndUsed(i))
332 // code for printing implict references
333 unsigned NumOfImpRefs = MI.getNumImplicitRefs();
334 if (NumOfImpRefs > 0) {
335 os << "\tImplicit: ";
336 for (unsigned z=0; z < NumOfImpRefs; z++) {
337 OutputValue(os, MI.getImplicitRef(z));
338 if (MI.implicitRefIsDefined(z)) os << "<d>";
339 if (MI.implicitRefIsDefinedAndUsed(z)) os << "<d&u>";
347 std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO)
351 else if (MO.opLoBits32())
353 else if (MO.opHiBits64())
355 else if (MO.opLoBits64())
358 switch (MO.getType())
360 case MachineOperand::MO_VirtualRegister:
361 if (MO.hasAllocatedReg())
362 OutputReg(OS, MO.getAllocatedRegNum());
364 if (MO.getVRegValue()) {
365 if (MO.hasAllocatedReg()) OS << "==";
367 OutputValue(OS, MO.getVRegValue());
370 case MachineOperand::MO_CCRegister:
372 OutputValue(OS, MO.getVRegValue());
373 if (MO.hasAllocatedReg()) {
375 OutputReg(OS, MO.getAllocatedRegNum());
378 case MachineOperand::MO_MachineRegister:
379 OutputReg(OS, MO.getMachineRegNum());
381 case MachineOperand::MO_SignExtendedImmed:
382 OS << (long)MO.getImmedValue();
384 case MachineOperand::MO_UnextendedImmed:
385 OS << (long)MO.getImmedValue();
387 case MachineOperand::MO_PCRelativeDisp:
389 const Value* opVal = MO.getVRegValue();
390 bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal);
391 OS << "%disp(" << (isLabel? "label " : "addr-of-val ");
392 if (opVal->hasName())
393 OS << opVal->getName();
395 OS << (const void*) opVal;
399 case MachineOperand::MO_MachineBasicBlock:
401 << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName()
402 << "," << (void*)MO.getMachineBasicBlock()->getBasicBlock() << ">";
404 case MachineOperand::MO_FrameIndex:
405 OS << "<fi#" << MO.getFrameIndex() << ">";
407 case MachineOperand::MO_ConstantPoolIndex:
408 OS << "<cp#" << MO.getConstantPoolIndex() << ">";
410 case MachineOperand::MO_GlobalAddress:
411 OS << "<ga:" << ((Value*)MO.getGlobal())->getName() << ">";
413 case MachineOperand::MO_ExternalSymbol:
414 OS << "<es:" << MO.getSymbolName() << ">";
417 assert(0 && "Unrecognized operand type");
422 (MachineOperand::HIFLAG32 | MachineOperand::LOFLAG32 |
423 MachineOperand::HIFLAG64 | MachineOperand::LOFLAG64))