1 //===-- MachineInstr.cpp --------------------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Methods common to all machine instructions.
12 // FIXME: Now that MachineInstrs have parent pointers, they should always
13 // print themselves using their MachineFunction's TargetMachine.
15 //===----------------------------------------------------------------------===//
17 #include "llvm/CodeGen/MachineInstr.h"
18 #include "llvm/CodeGen/MachineBasicBlock.h"
19 #include "llvm/Value.h"
20 #include "llvm/Target/TargetMachine.h"
21 #include "llvm/Target/TargetInstrInfo.h"
22 #include "llvm/Target/MRegisterInfo.h"
23 #include "Support/LeakDetector.h"
27 // Global variable holding an array of descriptors for machine instructions.
28 // The actual object needs to be created separately for each target machine.
29 // This variable is initialized and reset by class TargetInstrInfo.
31 // FIXME: This should be a property of the target so that more than one target
32 // at a time can be active...
34 extern const TargetInstrDescriptor *TargetInstrDescriptors;
36 // Constructor for instructions with variable #operands
37 MachineInstr::MachineInstr(short opcode, unsigned numOperands)
40 operands(numOperands, MachineOperand()),
42 // Make sure that we get added to a machine basicblock
43 LeakDetector::addGarbageObject(this);
46 /// MachineInstr ctor - This constructor only does a _reserve_ of the operands,
47 /// not a resize for them. It is expected that if you use this that you call
48 /// add* methods below to fill up the operands, instead of the Set methods.
49 /// Eventually, the "resizing" ctors will be phased out.
51 MachineInstr::MachineInstr(short opcode, unsigned numOperands, bool XX, bool YY)
52 : Opcode(opcode), numImplicitRefs(0), parent(0) {
53 operands.reserve(numOperands);
54 // Make sure that we get added to a machine basicblock
55 LeakDetector::addGarbageObject(this);
58 /// MachineInstr ctor - Work exactly the same as the ctor above, except that the
59 /// MachineInstr is created and added to the end of the specified basic block.
61 MachineInstr::MachineInstr(MachineBasicBlock *MBB, short opcode,
63 : Opcode(opcode), numImplicitRefs(0), parent(0) {
64 assert(MBB && "Cannot use inserting ctor with null basic block!");
65 operands.reserve(numOperands);
66 // Make sure that we get added to a machine basicblock
67 LeakDetector::addGarbageObject(this);
68 MBB->push_back(this); // Add instruction to end of basic block!
71 MachineInstr::~MachineInstr()
73 LeakDetector::removeGarbageObject(this);
76 /// OperandComplete - Return true if it's illegal to add a new operand
78 bool MachineInstr::OperandsComplete() const {
79 int NumOperands = TargetInstrDescriptors[Opcode].numOperands;
80 if (NumOperands >= 0 && getNumOperands() >= (unsigned)NumOperands)
81 return true; // Broken: we have all the operands of this instruction!
85 /// replace - Support for replacing opcode and operands of a MachineInstr in
86 /// place. This only resets the size of the operand vector and initializes it.
87 /// The new operands must be set explicitly later.
89 void MachineInstr::replace(short opcode, unsigned numOperands) {
90 assert(getNumImplicitRefs() == 0 &&
91 "This is probably broken because implicit refs are going to be lost.");
94 operands.resize(numOperands, MachineOperand());
97 void MachineInstr::SetMachineOperandVal(unsigned i,
98 MachineOperand::MachineOperandType opTy,
100 assert(i < operands.size()); // may be explicit or implicit op
101 operands[i].opType = opTy;
102 operands[i].value = V;
103 operands[i].regNum = -1;
107 MachineInstr::SetMachineOperandConst(unsigned i,
108 MachineOperand::MachineOperandType opTy,
110 assert(i < getNumOperands()); // must be explicit op
111 assert(TargetInstrDescriptors[Opcode].resultPos != (int) i &&
112 "immed. constant cannot be defined");
114 operands[i].opType = opTy;
115 operands[i].value = NULL;
116 operands[i].immedVal = intValue;
117 operands[i].regNum = -1;
118 operands[i].flags = 0;
121 void MachineInstr::SetMachineOperandReg(unsigned i, int regNum) {
122 assert(i < getNumOperands()); // must be explicit op
124 operands[i].opType = MachineOperand::MO_MachineRegister;
125 operands[i].value = NULL;
126 operands[i].regNum = regNum;
129 // Used only by the SPARC back-end.
130 void MachineInstr::SetRegForOperand(unsigned i, int regNum) {
131 assert(i < getNumOperands()); // must be explicit op
132 operands[i].setRegForValue(regNum);
135 // Used only by the SPARC back-end.
136 void MachineInstr::SetRegForImplicitRef(unsigned i, int regNum) {
137 getImplicitOp(i).setRegForValue(regNum);
140 /// substituteValue - Substitute all occurrences of Value* oldVal with newVal
141 /// in all operands and all implicit refs. If defsOnly == true, substitute defs
144 /// FIXME: Fold this into its single caller, at SparcInstrSelection.cpp:2865,
145 /// or make it a static function in that file.
148 MachineInstr::substituteValue(const Value* oldVal, Value* newVal,
149 bool defsOnly, bool notDefsAndUses,
150 bool& someArgsWereIgnored)
152 assert((!defsOnly || !notDefsAndUses) &&
153 "notDefsAndUses is irrelevant if defsOnly == true.");
155 unsigned numSubst = 0;
157 // Substitute operands
158 for (MachineInstr::val_op_iterator O = begin(), E = end(); O != E; ++O)
161 notDefsAndUses && (O.isDef() && !O.isUse()) ||
162 !notDefsAndUses && O.isDef())
164 O.getMachineOperand().value = newVal;
168 someArgsWereIgnored = true;
170 // Substitute implicit refs
171 for (unsigned i=0, N=getNumImplicitRefs(); i < N; ++i)
172 if (getImplicitRef(i) == oldVal)
174 notDefsAndUses && (getImplicitOp(i).isDef() && !getImplicitOp(i).isUse()) ||
175 !notDefsAndUses && getImplicitOp(i).isDef())
177 getImplicitOp(i).value = newVal;
181 someArgsWereIgnored = true;
186 void MachineInstr::dump() const {
187 std::cerr << " " << *this;
190 static inline std::ostream& OutputValue(std::ostream &os, const Value* val) {
192 os << (void*) val; // print address always
193 if (val && val->hasName())
194 os << " " << val->getName(); // print name also, if available
199 static inline void OutputReg(std::ostream &os, unsigned RegNo,
200 const MRegisterInfo *MRI = 0) {
202 if (MRegisterInfo::isPhysicalRegister(RegNo))
203 os << "%" << MRI->get(RegNo).Name;
205 os << "%reg" << RegNo;
207 os << "%mreg(" << RegNo << ")";
210 static void print(const MachineOperand &MO, std::ostream &OS,
211 const TargetMachine &TM) {
212 const MRegisterInfo *MRI = TM.getRegisterInfo();
213 bool CloseParen = true;
216 else if (MO.isLoBits32())
218 else if (MO.isHiBits64())
220 else if (MO.isLoBits64())
225 switch (MO.getType()) {
226 case MachineOperand::MO_VirtualRegister:
227 if (MO.getVRegValue()) {
229 OutputValue(OS, MO.getVRegValue());
230 if (MO.hasAllocatedReg())
233 if (MO.hasAllocatedReg())
234 OutputReg(OS, MO.getReg(), MRI);
236 case MachineOperand::MO_CCRegister:
238 OutputValue(OS, MO.getVRegValue());
239 if (MO.hasAllocatedReg()) {
241 OutputReg(OS, MO.getReg(), MRI);
244 case MachineOperand::MO_MachineRegister:
245 OutputReg(OS, MO.getMachineRegNum(), MRI);
247 case MachineOperand::MO_SignExtendedImmed:
248 OS << (long)MO.getImmedValue();
250 case MachineOperand::MO_UnextendedImmed:
251 OS << (long)MO.getImmedValue();
253 case MachineOperand::MO_PCRelativeDisp: {
254 const Value* opVal = MO.getVRegValue();
255 bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal);
256 OS << "%disp(" << (isLabel? "label " : "addr-of-val ");
257 if (opVal->hasName())
258 OS << opVal->getName();
260 OS << (const void*) opVal;
264 case MachineOperand::MO_MachineBasicBlock:
266 << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName()
267 << "," << (void*)MO.getMachineBasicBlock()->getBasicBlock() << ">";
269 case MachineOperand::MO_FrameIndex:
270 OS << "<fi#" << MO.getFrameIndex() << ">";
272 case MachineOperand::MO_ConstantPoolIndex:
273 OS << "<cp#" << MO.getConstantPoolIndex() << ">";
275 case MachineOperand::MO_GlobalAddress:
276 OS << "<ga:" << ((Value*)MO.getGlobal())->getName() << ">";
278 case MachineOperand::MO_ExternalSymbol:
279 OS << "<es:" << MO.getSymbolName() << ">";
282 assert(0 && "Unrecognized operand type");
289 void MachineInstr::print(std::ostream &OS, const TargetMachine &TM) const {
290 unsigned StartOp = 0;
292 // Specialize printing if op#0 is definition
293 if (getNumOperands() && getOperand(0).isDef() && !getOperand(0).isUse()) {
294 llvm::print(getOperand(0), OS, TM);
296 ++StartOp; // Don't print this operand again!
298 OS << TM.getInstrInfo().getName(getOpcode());
300 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
301 const MachineOperand& mop = getOperand(i);
305 llvm::print(mop, OS, TM);
314 // code for printing implicit references
315 if (getNumImplicitRefs()) {
316 OS << "\tImplicitRefs: ";
317 for(unsigned i = 0, e = getNumImplicitRefs(); i != e; ++i) {
319 OutputValue(OS, getImplicitRef(i));
320 if (getImplicitOp(i).isDef())
321 if (getImplicitOp(i).isUse())
331 std::ostream &operator<<(std::ostream& os, const MachineInstr& MI) {
332 os << TargetInstrDescriptors[MI.getOpcode()].Name;
334 for (unsigned i=0, N=MI.getNumOperands(); i < N; i++) {
335 os << "\t" << MI.getOperand(i);
336 if (MI.getOperand(i).isDef())
337 if (MI.getOperand(i).isUse())
343 // code for printing implicit references
344 unsigned NumOfImpRefs = MI.getNumImplicitRefs();
345 if (NumOfImpRefs > 0) {
346 os << "\tImplicit: ";
347 for (unsigned z=0; z < NumOfImpRefs; z++) {
348 OutputValue(os, MI.getImplicitRef(z));
349 if (MI.getImplicitOp(z).isDef())
350 if (MI.getImplicitOp(z).isUse())
361 std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO) {
364 else if (MO.isLoBits32())
366 else if (MO.isHiBits64())
368 else if (MO.isLoBits64())
371 switch (MO.getType())
373 case MachineOperand::MO_VirtualRegister:
374 if (MO.hasAllocatedReg())
375 OutputReg(OS, MO.getReg());
377 if (MO.getVRegValue()) {
378 if (MO.hasAllocatedReg()) OS << "==";
380 OutputValue(OS, MO.getVRegValue());
383 case MachineOperand::MO_CCRegister:
385 OutputValue(OS, MO.getVRegValue());
386 if (MO.hasAllocatedReg()) {
388 OutputReg(OS, MO.getReg());
391 case MachineOperand::MO_MachineRegister:
392 OutputReg(OS, MO.getMachineRegNum());
394 case MachineOperand::MO_SignExtendedImmed:
395 OS << (long)MO.getImmedValue();
397 case MachineOperand::MO_UnextendedImmed:
398 OS << (long)MO.getImmedValue();
400 case MachineOperand::MO_PCRelativeDisp:
402 const Value* opVal = MO.getVRegValue();
403 bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal);
404 OS << "%disp(" << (isLabel? "label " : "addr-of-val ");
405 if (opVal->hasName())
406 OS << opVal->getName();
408 OS << (const void*) opVal;
412 case MachineOperand::MO_MachineBasicBlock:
414 << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName()
415 << "," << (void*)MO.getMachineBasicBlock()->getBasicBlock() << ">";
417 case MachineOperand::MO_FrameIndex:
418 OS << "<fi#" << MO.getFrameIndex() << ">";
420 case MachineOperand::MO_ConstantPoolIndex:
421 OS << "<cp#" << MO.getConstantPoolIndex() << ">";
423 case MachineOperand::MO_GlobalAddress:
424 OS << "<ga:" << ((Value*)MO.getGlobal())->getName() << ">";
426 case MachineOperand::MO_ExternalSymbol:
427 OS << "<es:" << MO.getSymbolName() << ">";
430 assert(0 && "Unrecognized operand type");
435 (MachineOperand::HIFLAG32 | MachineOperand::LOFLAG32 |
436 MachineOperand::HIFLAG64 | MachineOperand::LOFLAG64))
442 } // End llvm namespace