1 //===-- MachineInstr.cpp --------------------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 #include "llvm/CodeGen/MachineInstr.h"
13 #include "llvm/CodeGen/MachineBasicBlock.h"
14 #include "llvm/Value.h"
15 #include "llvm/Target/TargetMachine.h"
16 #include "llvm/Target/TargetInstrInfo.h"
17 #include "llvm/Target/MRegisterInfo.h"
21 // Global variable holding an array of descriptors for machine instructions.
22 // The actual object needs to be created separately for each target machine.
23 // This variable is initialized and reset by class TargetInstrInfo.
25 // FIXME: This should be a property of the target so that more than one target
26 // at a time can be active...
28 extern const TargetInstrDescriptor *TargetInstrDescriptors;
30 // Constructor for instructions with variable #operands
31 MachineInstr::MachineInstr(MachineOpCode OpCode, unsigned numOperands)
33 operands(numOperands, MachineOperand()),
38 /// MachineInstr ctor - This constructor only does a _reserve_ of the operands,
39 /// not a resize for them. It is expected that if you use this that you call
40 /// add* methods below to fill up the operands, instead of the Set methods.
41 /// Eventually, the "resizing" ctors will be phased out.
43 MachineInstr::MachineInstr(MachineOpCode Opcode, unsigned numOperands,
48 operands.reserve(numOperands);
51 /// MachineInstr ctor - Work exactly the same as the ctor above, except that the
52 /// MachineInstr is created and added to the end of the specified basic block.
54 MachineInstr::MachineInstr(MachineBasicBlock *MBB, MachineOpCode Opcode,
59 assert(MBB && "Cannot use inserting ctor with null basic block!");
60 operands.reserve(numOperands);
61 MBB->push_back(this); // Add instruction to end of basic block!
65 // OperandComplete - Return true if it's illegal to add a new operand
66 bool MachineInstr::OperandsComplete() const
68 int NumOperands = TargetInstrDescriptors[opCode].numOperands;
69 if (NumOperands >= 0 && getNumOperands() >= (unsigned)NumOperands)
70 return true; // Broken: we have all the operands of this instruction!
76 // Support for replacing opcode and operands of a MachineInstr in place.
77 // This only resets the size of the operand vector and initializes it.
78 // The new operands must be set explicitly later.
80 void MachineInstr::replace(MachineOpCode Opcode, unsigned numOperands)
82 assert(getNumImplicitRefs() == 0 &&
83 "This is probably broken because implicit refs are going to be lost.");
86 operands.resize(numOperands, MachineOperand());
89 void MachineInstr::SetMachineOperandVal(unsigned i,
90 MachineOperand::MachineOperandType opTy,
92 assert(i < operands.size()); // may be explicit or implicit op
93 operands[i].opType = opTy;
94 operands[i].value = V;
95 operands[i].regNum = -1;
99 MachineInstr::SetMachineOperandConst(unsigned i,
100 MachineOperand::MachineOperandType operandType,
103 assert(i < getNumOperands()); // must be explicit op
104 assert(TargetInstrDescriptors[opCode].resultPos != (int) i &&
105 "immed. constant cannot be defined");
107 operands[i].opType = operandType;
108 operands[i].value = NULL;
109 operands[i].immedVal = intValue;
110 operands[i].regNum = -1;
111 operands[i].flags = 0;
114 void MachineInstr::SetMachineOperandReg(unsigned i, int regNum) {
115 assert(i < getNumOperands()); // must be explicit op
117 operands[i].opType = MachineOperand::MO_MachineRegister;
118 operands[i].value = NULL;
119 operands[i].regNum = regNum;
123 MachineInstr::SetRegForOperand(unsigned i, int regNum)
125 assert(i < getNumOperands()); // must be explicit op
126 operands[i].setRegForValue(regNum);
130 MachineInstr::SetRegForImplicitRef(unsigned i, int regNum)
132 getImplicitOp(i).setRegForValue(regNum);
136 // Substitute all occurrences of Value* oldVal with newVal in all operands
137 // and all implicit refs.
138 // If defsOnly == true, substitute defs only.
140 MachineInstr::substituteValue(const Value* oldVal, Value* newVal,
141 bool defsOnly, bool notDefsAndUses,
142 bool& someArgsWereIgnored)
144 assert((!defsOnly || !notDefsAndUses) &&
145 "notDefsAndUses is irrelevant if defsOnly == true.");
147 unsigned numSubst = 0;
149 // Substitute operands
150 for (MachineInstr::val_op_iterator O = begin(), E = end(); O != E; ++O)
153 notDefsAndUses && (O.isDef() && !O.isUse()) ||
154 !notDefsAndUses && O.isDef())
156 O.getMachineOperand().value = newVal;
160 someArgsWereIgnored = true;
162 // Substitute implicit refs
163 for (unsigned i=0, N=getNumImplicitRefs(); i < N; ++i)
164 if (getImplicitRef(i) == oldVal)
166 notDefsAndUses && (getImplicitOp(i).isDef() && !getImplicitOp(i).isUse()) ||
167 !notDefsAndUses && getImplicitOp(i).isDef())
169 getImplicitOp(i).value = newVal;
173 someArgsWereIgnored = true;
180 MachineInstr::dump() const
182 std::cerr << " " << *this;
185 static inline std::ostream&
186 OutputValue(std::ostream &os, const Value* val)
189 os << (void*) val; // print address always
190 if (val && val->hasName())
191 os << " " << val->getName() << ")"; // print name also, if available
195 static inline void OutputReg(std::ostream &os, unsigned RegNo,
196 const MRegisterInfo *MRI = 0) {
198 if (RegNo < MRegisterInfo::FirstVirtualRegister)
199 os << "%" << MRI->get(RegNo).Name;
201 os << "%reg" << RegNo;
203 os << "%mreg(" << RegNo << ")";
206 static void print(const MachineOperand &MO, std::ostream &OS,
207 const TargetMachine &TM) {
208 const MRegisterInfo *MRI = TM.getRegisterInfo();
209 bool CloseParen = true;
212 else if (MO.isLoBits32())
214 else if (MO.isHiBits64())
216 else if (MO.isLoBits64())
221 switch (MO.getType()) {
222 case MachineOperand::MO_VirtualRegister:
223 if (MO.getVRegValue()) {
225 OutputValue(OS, MO.getVRegValue());
226 if (MO.hasAllocatedReg())
229 if (MO.hasAllocatedReg())
230 OutputReg(OS, MO.getAllocatedRegNum(), MRI);
232 case MachineOperand::MO_CCRegister:
234 OutputValue(OS, MO.getVRegValue());
235 if (MO.hasAllocatedReg()) {
237 OutputReg(OS, MO.getAllocatedRegNum(), MRI);
240 case MachineOperand::MO_MachineRegister:
241 OutputReg(OS, MO.getMachineRegNum(), MRI);
243 case MachineOperand::MO_SignExtendedImmed:
244 OS << (long)MO.getImmedValue();
246 case MachineOperand::MO_UnextendedImmed:
247 OS << (long)MO.getImmedValue();
249 case MachineOperand::MO_PCRelativeDisp: {
250 const Value* opVal = MO.getVRegValue();
251 bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal);
252 OS << "%disp(" << (isLabel? "label " : "addr-of-val ");
253 if (opVal->hasName())
254 OS << opVal->getName();
256 OS << (const void*) opVal;
260 case MachineOperand::MO_MachineBasicBlock:
262 << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName()
263 << "," << (void*)MO.getMachineBasicBlock()->getBasicBlock() << ">";
265 case MachineOperand::MO_FrameIndex:
266 OS << "<fi#" << MO.getFrameIndex() << ">";
268 case MachineOperand::MO_ConstantPoolIndex:
269 OS << "<cp#" << MO.getConstantPoolIndex() << ">";
271 case MachineOperand::MO_GlobalAddress:
272 OS << "<ga:" << ((Value*)MO.getGlobal())->getName() << ">";
274 case MachineOperand::MO_ExternalSymbol:
275 OS << "<es:" << MO.getSymbolName() << ">";
278 assert(0 && "Unrecognized operand type");
285 void MachineInstr::print(std::ostream &OS, const TargetMachine &TM) const {
286 unsigned StartOp = 0;
288 // Specialize printing if op#0 is definition
289 if (getNumOperands() && getOperand(0).isDef() && !getOperand(0).isUse()) {
290 llvm::print(getOperand(0), OS, TM);
292 ++StartOp; // Don't print this operand again!
294 OS << TM.getInstrInfo().getName(getOpcode());
296 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
297 const MachineOperand& mop = getOperand(i);
301 llvm::print(mop, OS, TM);
310 // code for printing implicit references
311 if (getNumImplicitRefs()) {
312 OS << "\tImplicitRefs: ";
313 for(unsigned i = 0, e = getNumImplicitRefs(); i != e; ++i) {
315 OutputValue(OS, getImplicitRef(i));
316 if (getImplicitOp(i).isDef())
317 if (getImplicitOp(i).isUse())
328 std::ostream &operator<<(std::ostream& os, const MachineInstr& MI)
330 os << TargetInstrDescriptors[MI.opCode].Name;
332 for (unsigned i=0, N=MI.getNumOperands(); i < N; i++) {
333 os << "\t" << MI.getOperand(i);
334 if (MI.getOperand(i).isDef())
335 if (MI.getOperand(i).isUse())
341 // code for printing implicit references
342 unsigned NumOfImpRefs = MI.getNumImplicitRefs();
343 if (NumOfImpRefs > 0) {
344 os << "\tImplicit: ";
345 for (unsigned z=0; z < NumOfImpRefs; z++) {
346 OutputValue(os, MI.getImplicitRef(z));
347 if (MI.getImplicitOp(z).isDef())
348 if (MI.getImplicitOp(z).isUse())
359 std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO)
363 else if (MO.isLoBits32())
365 else if (MO.isHiBits64())
367 else if (MO.isLoBits64())
370 switch (MO.getType())
372 case MachineOperand::MO_VirtualRegister:
373 if (MO.hasAllocatedReg())
374 OutputReg(OS, MO.getAllocatedRegNum());
376 if (MO.getVRegValue()) {
377 if (MO.hasAllocatedReg()) OS << "==";
379 OutputValue(OS, MO.getVRegValue());
382 case MachineOperand::MO_CCRegister:
384 OutputValue(OS, MO.getVRegValue());
385 if (MO.hasAllocatedReg()) {
387 OutputReg(OS, MO.getAllocatedRegNum());
390 case MachineOperand::MO_MachineRegister:
391 OutputReg(OS, MO.getMachineRegNum());
393 case MachineOperand::MO_SignExtendedImmed:
394 OS << (long)MO.getImmedValue();
396 case MachineOperand::MO_UnextendedImmed:
397 OS << (long)MO.getImmedValue();
399 case MachineOperand::MO_PCRelativeDisp:
401 const Value* opVal = MO.getVRegValue();
402 bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal);
403 OS << "%disp(" << (isLabel? "label " : "addr-of-val ");
404 if (opVal->hasName())
405 OS << opVal->getName();
407 OS << (const void*) opVal;
411 case MachineOperand::MO_MachineBasicBlock:
413 << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName()
414 << "," << (void*)MO.getMachineBasicBlock()->getBasicBlock() << ">";
416 case MachineOperand::MO_FrameIndex:
417 OS << "<fi#" << MO.getFrameIndex() << ">";
419 case MachineOperand::MO_ConstantPoolIndex:
420 OS << "<cp#" << MO.getConstantPoolIndex() << ">";
422 case MachineOperand::MO_GlobalAddress:
423 OS << "<ga:" << ((Value*)MO.getGlobal())->getName() << ">";
425 case MachineOperand::MO_ExternalSymbol:
426 OS << "<es:" << MO.getSymbolName() << ">";
429 assert(0 && "Unrecognized operand type");
434 (MachineOperand::HIFLAG32 | MachineOperand::LOFLAG32 |
435 MachineOperand::HIFLAG64 | MachineOperand::LOFLAG64))
441 } // End llvm namespace