1 //===-- MachineInstr.cpp --------------------------------------------------===//
3 //===----------------------------------------------------------------------===//
5 #include "llvm/CodeGen/MachineInstr.h"
6 #include "llvm/CodeGen/MachineBasicBlock.h"
7 #include "llvm/Value.h"
8 #include "llvm/Target/MachineInstrInfo.h" // FIXME: shouldn't need this!
9 #include "llvm/Target/TargetMachine.h"
10 #include "llvm/Target/MRegisterInfo.h"
13 // Global variable holding an array of descriptors for machine instructions.
14 // The actual object needs to be created separately for each target machine.
15 // This variable is initialized and reset by class MachineInstrInfo.
17 // FIXME: This should be a property of the target so that more than one target
18 // at a time can be active...
20 extern const MachineInstrDescriptor *TargetInstrDescriptors;
22 // Constructor for instructions with fixed #operands (nearly all)
23 MachineInstr::MachineInstr(MachineOpCode _opCode)
25 operands(TargetInstrDescriptors[_opCode].numOperands, MachineOperand()),
28 assert(TargetInstrDescriptors[_opCode].numOperands >= 0);
31 // Constructor for instructions with variable #operands
32 MachineInstr::MachineInstr(MachineOpCode OpCode, unsigned numOperands)
34 operands(numOperands, MachineOperand()),
39 /// MachineInstr ctor - This constructor only does a _reserve_ of the operands,
40 /// not a resize for them. It is expected that if you use this that you call
41 /// add* methods below to fill up the operands, instead of the Set methods.
42 /// Eventually, the "resizing" ctors will be phased out.
44 MachineInstr::MachineInstr(MachineOpCode Opcode, unsigned numOperands,
49 operands.reserve(numOperands);
52 /// MachineInstr ctor - Work exactly the same as the ctor above, except that the
53 /// MachineInstr is created and added to the end of the specified basic block.
55 MachineInstr::MachineInstr(MachineBasicBlock *MBB, MachineOpCode Opcode,
60 assert(MBB && "Cannot use inserting ctor with null basic block!");
61 operands.reserve(numOperands);
62 MBB->push_back(this); // Add instruction to end of basic block!
66 // OperandComplete - Return true if it's illegal to add a new operand
67 bool MachineInstr::OperandsComplete() const
69 int NumOperands = TargetInstrDescriptors[opCode].numOperands;
70 if (NumOperands >= 0 && getNumOperands() >= (unsigned)NumOperands)
71 return true; // Broken!
77 // Support for replacing opcode and operands of a MachineInstr in place.
78 // This only resets the size of the operand vector and initializes it.
79 // The new operands must be set explicitly later.
81 void MachineInstr::replace(MachineOpCode Opcode, unsigned numOperands)
83 assert(getNumImplicitRefs() == 0 &&
84 "This is probably broken because implicit refs are going to be lost.");
87 operands.resize(numOperands, MachineOperand());
91 MachineInstr::SetMachineOperandVal(unsigned i,
92 MachineOperand::MachineOperandType opType,
97 assert(i < operands.size()); // may be explicit or implicit op
98 operands[i].opType = opType;
99 operands[i].value = V;
100 operands[i].regNum = -1;
101 operands[i].flags = 0;
103 if (isdef || TargetInstrDescriptors[opCode].resultPos == (int) i)
104 operands[i].markDef();
106 operands[i].markDefAndUse();
110 MachineInstr::SetMachineOperandConst(unsigned i,
111 MachineOperand::MachineOperandType operandType,
114 assert(i < getNumOperands()); // must be explicit op
115 assert(TargetInstrDescriptors[opCode].resultPos != (int) i &&
116 "immed. constant cannot be defined");
118 operands[i].opType = operandType;
119 operands[i].value = NULL;
120 operands[i].immedVal = intValue;
121 operands[i].regNum = -1;
122 operands[i].flags = 0;
126 MachineInstr::SetMachineOperandReg(unsigned i,
129 assert(i < getNumOperands()); // must be explicit op
131 operands[i].opType = MachineOperand::MO_MachineRegister;
132 operands[i].value = NULL;
133 operands[i].regNum = regNum;
134 operands[i].flags = 0;
136 if (isdef || TargetInstrDescriptors[opCode].resultPos == (int) i)
137 operands[i].markDef();
138 insertUsedReg(regNum);
142 MachineInstr::SetRegForOperand(unsigned i, int regNum)
144 assert(i < getNumOperands()); // must be explicit op
145 operands[i].setRegForValue(regNum);
146 insertUsedReg(regNum);
150 // Subsitute all occurrences of Value* oldVal with newVal in all operands
151 // and all implicit refs. If defsOnly == true, substitute defs only.
153 MachineInstr::substituteValue(const Value* oldVal, Value* newVal, bool defsOnly)
155 unsigned numSubst = 0;
157 // Subsitute operands
158 for (MachineInstr::val_op_iterator O = begin(), E = end(); O != E; ++O)
160 if (!defsOnly || O.isDef())
162 O.getMachineOperand().value = newVal;
166 // Subsitute implicit refs
167 for (unsigned i=0, N=getNumImplicitRefs(); i < N; ++i)
168 if (getImplicitRef(i) == oldVal)
169 if (!defsOnly || implicitRefIsDefined(i))
171 getImplicitOp(i).value = newVal;
180 MachineInstr::dump() const
182 cerr << " " << *this;
185 static inline std::ostream&
186 OutputValue(std::ostream &os, const Value* val)
189 if (val && val->hasName())
190 return os << val->getName() << ")";
192 return os << (void*) val << ")"; // print address only
195 static inline void OutputReg(std::ostream &os, unsigned RegNo,
196 const MRegisterInfo *MRI = 0) {
198 if (RegNo < MRegisterInfo::FirstVirtualRegister)
199 os << "%" << MRI->get(RegNo).Name;
201 os << "%reg" << RegNo;
203 os << "%mreg(" << RegNo << ")";
206 static void print(const MachineOperand &MO, std::ostream &OS,
207 const TargetMachine &TM) {
208 const MRegisterInfo *MRI = TM.getRegisterInfo();
209 bool CloseParen = true;
212 else if (MO.opLoBits32())
214 else if (MO.opHiBits64())
216 else if (MO.opLoBits64())
221 switch (MO.getType()) {
222 case MachineOperand::MO_VirtualRegister:
223 if (MO.getVRegValue()) {
225 OutputValue(OS, MO.getVRegValue());
226 if (MO.hasAllocatedReg())
229 if (MO.hasAllocatedReg())
230 OutputReg(OS, MO.getAllocatedRegNum(), MRI);
232 case MachineOperand::MO_CCRegister:
234 OutputValue(OS, MO.getVRegValue());
235 if (MO.hasAllocatedReg()) {
237 OutputReg(OS, MO.getAllocatedRegNum(), MRI);
240 case MachineOperand::MO_MachineRegister:
241 OutputReg(OS, MO.getMachineRegNum(), MRI);
243 case MachineOperand::MO_SignExtendedImmed:
244 OS << (long)MO.getImmedValue();
246 case MachineOperand::MO_UnextendedImmed:
247 OS << (long)MO.getImmedValue();
249 case MachineOperand::MO_PCRelativeDisp: {
250 const Value* opVal = MO.getVRegValue();
251 bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal);
252 OS << "%disp(" << (isLabel? "label " : "addr-of-val ");
253 if (opVal->hasName())
254 OS << opVal->getName();
256 OS << (const void*) opVal;
261 assert(0 && "Unrecognized operand type");
268 void MachineInstr::print(std::ostream &OS, const TargetMachine &TM) {
269 OS << TM.getInstrInfo().getName(getOpcode());
270 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
272 ::print(getOperand(i), OS, TM);
274 if (operandIsDefinedAndUsed(i))
276 else if (operandIsDefined(i))
280 // code for printing implict references
281 if (getNumImplicitRefs()) {
282 OS << "\tImplicitRefs: ";
283 for(unsigned i = 0, e = getNumImplicitRefs(); i != e; ++i) {
285 OutputValue(OS, getImplicitRef(i));
286 if (implicitRefIsDefinedAndUsed(i))
288 else if (implicitRefIsDefined(i))
297 std::ostream &operator<<(std::ostream& os, const MachineInstr& minstr)
299 os << TargetInstrDescriptors[minstr.opCode].Name;
301 for (unsigned i=0, N=minstr.getNumOperands(); i < N; i++) {
302 os << "\t" << minstr.getOperand(i);
303 if( minstr.operandIsDefined(i) )
305 if( minstr.operandIsDefinedAndUsed(i) )
309 // code for printing implict references
310 unsigned NumOfImpRefs = minstr.getNumImplicitRefs();
311 if( NumOfImpRefs > 0 ) {
312 os << "\tImplicit: ";
313 for(unsigned z=0; z < NumOfImpRefs; z++) {
314 OutputValue(os, minstr.getImplicitRef(z));
315 if( minstr.implicitRefIsDefined(z)) os << "*";
316 if( minstr.implicitRefIsDefinedAndUsed(z)) os << "*";
324 std::ostream &operator<<(std::ostream &os, const MachineOperand &mop)
326 if (mop.opHiBits32())
328 else if (mop.opLoBits32())
330 else if (mop.opHiBits64())
332 else if (mop.opLoBits64())
335 switch (mop.getType())
337 case MachineOperand::MO_VirtualRegister:
339 OutputValue(os, mop.getVRegValue());
340 if (mop.hasAllocatedReg()) {
342 OutputReg(os, mop.getAllocatedRegNum());
345 case MachineOperand::MO_CCRegister:
347 OutputValue(os, mop.getVRegValue());
348 if (mop.hasAllocatedReg()) {
350 OutputReg(os, mop.getAllocatedRegNum());
353 case MachineOperand::MO_MachineRegister:
354 OutputReg(os, mop.getMachineRegNum());
356 case MachineOperand::MO_SignExtendedImmed:
357 os << (long)mop.getImmedValue();
359 case MachineOperand::MO_UnextendedImmed:
360 os << (long)mop.getImmedValue();
362 case MachineOperand::MO_PCRelativeDisp:
364 const Value* opVal = mop.getVRegValue();
365 bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal);
366 os << "%disp(" << (isLabel? "label " : "addr-of-val ");
367 if (opVal->hasName())
368 os << opVal->getName();
370 os << (const void*) opVal;
375 assert(0 && "Unrecognized operand type");
380 (MachineOperand::HIFLAG32 | MachineOperand::LOFLAG32 |
381 MachineOperand::HIFLAG64 | MachineOperand::LOFLAG64))