1 //===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Methods common to all machine instructions.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "llvm/Value.h"
16 #include "llvm/CodeGen/MachineFunction.h"
17 #include "llvm/CodeGen/MachineRegisterInfo.h"
18 #include "llvm/CodeGen/PseudoSourceValue.h"
19 #include "llvm/CodeGen/SelectionDAGNodes.h"
20 #include "llvm/Target/TargetMachine.h"
21 #include "llvm/Target/TargetInstrDesc.h"
22 #include "llvm/Target/MRegisterInfo.h"
23 #include "llvm/Support/LeakDetector.h"
24 #include "llvm/Support/Streams.h"
28 //===----------------------------------------------------------------------===//
29 // MachineOperand Implementation
30 //===----------------------------------------------------------------------===//
32 /// AddRegOperandToRegInfo - Add this register operand to the specified
33 /// MachineRegisterInfo. If it is null, then the next/prev fields should be
34 /// explicitly nulled out.
35 void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) {
36 assert(isReg() && "Can only add reg operand to use lists");
38 // If the reginfo pointer is null, just explicitly null out or next/prev
39 // pointers, to ensure they are not garbage.
41 Contents.Reg.Prev = 0;
42 Contents.Reg.Next = 0;
46 // Otherwise, add this operand to the head of the registers use/def list.
47 MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg());
49 // For SSA values, we prefer to keep the definition at the start of the list.
50 // we do this by skipping over the definition if it is at the head of the
52 if (*Head && (*Head)->isDef())
53 Head = &(*Head)->Contents.Reg.Next;
55 Contents.Reg.Next = *Head;
56 if (Contents.Reg.Next) {
57 assert(getReg() == Contents.Reg.Next->getReg() &&
58 "Different regs on the same list!");
59 Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next;
62 Contents.Reg.Prev = Head;
66 void MachineOperand::setReg(unsigned Reg) {
67 if (getReg() == Reg) return; // No change.
69 // Otherwise, we have to change the register. If this operand is embedded
70 // into a machine function, we need to update the old and new register's
72 if (MachineInstr *MI = getParent())
73 if (MachineBasicBlock *MBB = MI->getParent())
74 if (MachineFunction *MF = MBB->getParent()) {
75 RemoveRegOperandFromRegInfo();
76 Contents.Reg.RegNo = Reg;
77 AddRegOperandToRegInfo(&MF->getRegInfo());
81 // Otherwise, just change the register, no problem. :)
82 Contents.Reg.RegNo = Reg;
85 /// ChangeToImmediate - Replace this operand with a new immediate operand of
86 /// the specified value. If an operand is known to be an immediate already,
87 /// the setImm method should be used.
88 void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
89 // If this operand is currently a register operand, and if this is in a
90 // function, deregister the operand from the register's use/def list.
91 if (isReg() && getParent() && getParent()->getParent() &&
92 getParent()->getParent()->getParent())
93 RemoveRegOperandFromRegInfo();
95 OpKind = MO_Immediate;
96 Contents.ImmVal = ImmVal;
99 /// ChangeToRegister - Replace this operand with a new register operand of
100 /// the specified value. If an operand is known to be an register already,
101 /// the setReg method should be used.
102 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
103 bool isKill, bool isDead) {
104 // If this operand is already a register operand, use setReg to update the
105 // register's use/def lists.
109 // Otherwise, change this to a register and set the reg#.
110 OpKind = MO_Register;
111 Contents.Reg.RegNo = Reg;
113 // If this operand is embedded in a function, add the operand to the
114 // register's use/def list.
115 if (MachineInstr *MI = getParent())
116 if (MachineBasicBlock *MBB = MI->getParent())
117 if (MachineFunction *MF = MBB->getParent())
118 AddRegOperandToRegInfo(&MF->getRegInfo());
128 /// isIdenticalTo - Return true if this operand is identical to the specified
130 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
131 if (getType() != Other.getType()) return false;
134 default: assert(0 && "Unrecognized operand type");
135 case MachineOperand::MO_Register:
136 return getReg() == Other.getReg() && isDef() == Other.isDef() &&
137 getSubReg() == Other.getSubReg();
138 case MachineOperand::MO_Immediate:
139 return getImm() == Other.getImm();
140 case MachineOperand::MO_MachineBasicBlock:
141 return getMBB() == Other.getMBB();
142 case MachineOperand::MO_FrameIndex:
143 return getIndex() == Other.getIndex();
144 case MachineOperand::MO_ConstantPoolIndex:
145 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
146 case MachineOperand::MO_JumpTableIndex:
147 return getIndex() == Other.getIndex();
148 case MachineOperand::MO_GlobalAddress:
149 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
150 case MachineOperand::MO_ExternalSymbol:
151 return !strcmp(getSymbolName(), Other.getSymbolName()) &&
152 getOffset() == Other.getOffset();
156 /// print - Print the specified machine operand.
158 void MachineOperand::print(std::ostream &OS, const TargetMachine *TM) const {
160 case MachineOperand::MO_Register:
161 if (getReg() == 0 || MRegisterInfo::isVirtualRegister(getReg())) {
162 OS << "%reg" << getReg();
164 // If the instruction is embedded into a basic block, we can find the
165 // target info for the instruction.
167 if (const MachineInstr *MI = getParent())
168 if (const MachineBasicBlock *MBB = MI->getParent())
169 if (const MachineFunction *MF = MBB->getParent())
170 TM = &MF->getTarget();
173 OS << "%" << TM->getRegisterInfo()->get(getReg()).Name;
175 OS << "%mreg" << getReg();
178 if (isDef() || isKill() || isDead() || isImplicit()) {
180 bool NeedComma = false;
182 OS << (isDef() ? "imp-def" : "imp-use");
184 } else if (isDef()) {
188 if (isKill() || isDead()) {
189 if (NeedComma) OS << ",";
190 if (isKill()) OS << "kill";
191 if (isDead()) OS << "dead";
196 case MachineOperand::MO_Immediate:
199 case MachineOperand::MO_MachineBasicBlock:
201 << ((Value*)getMBB()->getBasicBlock())->getName()
202 << "," << (void*)getMBB() << ">";
204 case MachineOperand::MO_FrameIndex:
205 OS << "<fi#" << getIndex() << ">";
207 case MachineOperand::MO_ConstantPoolIndex:
208 OS << "<cp#" << getIndex();
209 if (getOffset()) OS << "+" << getOffset();
212 case MachineOperand::MO_JumpTableIndex:
213 OS << "<jt#" << getIndex() << ">";
215 case MachineOperand::MO_GlobalAddress:
216 OS << "<ga:" << ((Value*)getGlobal())->getName();
217 if (getOffset()) OS << "+" << getOffset();
220 case MachineOperand::MO_ExternalSymbol:
221 OS << "<es:" << getSymbolName();
222 if (getOffset()) OS << "+" << getOffset();
226 assert(0 && "Unrecognized operand type");
230 //===----------------------------------------------------------------------===//
231 // MachineInstr Implementation
232 //===----------------------------------------------------------------------===//
234 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
235 /// TID NULL and no operands.
236 MachineInstr::MachineInstr()
237 : TID(0), NumImplicitOps(0), Parent(0) {
238 // Make sure that we get added to a machine basicblock
239 LeakDetector::addGarbageObject(this);
242 void MachineInstr::addImplicitDefUseOperands() {
243 if (TID->ImplicitDefs)
244 for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
245 addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
246 if (TID->ImplicitUses)
247 for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
248 addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
251 /// MachineInstr ctor - This constructor create a MachineInstr and add the
252 /// implicit operands. It reserves space for number of operands specified by
253 /// TargetInstrDesc or the numOperands if it is not zero. (for
254 /// instructions with variable number of operands).
255 MachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp)
256 : TID(&tid), NumImplicitOps(0), Parent(0) {
257 if (!NoImp && TID->getImplicitDefs())
258 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
260 if (!NoImp && TID->getImplicitUses())
261 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
263 Operands.reserve(NumImplicitOps + TID->getNumOperands());
265 addImplicitDefUseOperands();
266 // Make sure that we get added to a machine basicblock
267 LeakDetector::addGarbageObject(this);
270 /// MachineInstr ctor - Work exactly the same as the ctor above, except that the
271 /// MachineInstr is created and added to the end of the specified basic block.
273 MachineInstr::MachineInstr(MachineBasicBlock *MBB,
274 const TargetInstrDesc &tid)
275 : TID(&tid), NumImplicitOps(0), Parent(0) {
276 assert(MBB && "Cannot use inserting ctor with null basic block!");
277 if (TID->ImplicitDefs)
278 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
280 if (TID->ImplicitUses)
281 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
283 Operands.reserve(NumImplicitOps + TID->getNumOperands());
284 addImplicitDefUseOperands();
285 // Make sure that we get added to a machine basicblock
286 LeakDetector::addGarbageObject(this);
287 MBB->push_back(this); // Add instruction to end of basic block!
290 /// MachineInstr ctor - Copies MachineInstr arg exactly
292 MachineInstr::MachineInstr(const MachineInstr &MI) {
294 NumImplicitOps = MI.NumImplicitOps;
295 Operands.reserve(MI.getNumOperands());
296 MemOperands = MI.MemOperands;
299 for (unsigned i = 0; i != MI.getNumOperands(); ++i) {
300 Operands.push_back(MI.getOperand(i));
301 Operands.back().ParentMI = this;
304 // Set parent, next, and prev to null
311 MachineInstr::~MachineInstr() {
312 LeakDetector::removeGarbageObject(this);
314 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
315 assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
316 assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
317 "Reg operand def/use list corrupted");
322 /// getOpcode - Returns the opcode of this MachineInstr.
324 int MachineInstr::getOpcode() const {
328 /// getRegInfo - If this instruction is embedded into a MachineFunction,
329 /// return the MachineRegisterInfo object for the current function, otherwise
331 MachineRegisterInfo *MachineInstr::getRegInfo() {
332 if (MachineBasicBlock *MBB = getParent())
333 if (MachineFunction *MF = MBB->getParent())
334 return &MF->getRegInfo();
338 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
339 /// this instruction from their respective use lists. This requires that the
340 /// operands already be on their use lists.
341 void MachineInstr::RemoveRegOperandsFromUseLists() {
342 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
343 if (Operands[i].isReg())
344 Operands[i].RemoveRegOperandFromRegInfo();
348 /// AddRegOperandsToUseLists - Add all of the register operands in
349 /// this instruction from their respective use lists. This requires that the
350 /// operands not be on their use lists yet.
351 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) {
352 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
353 if (Operands[i].isReg())
354 Operands[i].AddRegOperandToRegInfo(&RegInfo);
359 /// addOperand - Add the specified operand to the instruction. If it is an
360 /// implicit operand, it is added to the end of the operand list. If it is
361 /// an explicit operand it is added at the end of the explicit operand list
362 /// (before the first implicit operand).
363 void MachineInstr::addOperand(const MachineOperand &Op) {
364 bool isImpReg = Op.isReg() && Op.isImplicit();
365 assert((isImpReg || !OperandsComplete()) &&
366 "Trying to add an operand to a machine instr that is already done!");
368 // If we are adding the operand to the end of the list, our job is simpler.
369 // This is true most of the time, so this is a reasonable optimization.
370 if (isImpReg || NumImplicitOps == 0) {
371 // We can only do this optimization if we know that the operand list won't
373 if (Operands.empty() || Operands.size()+1 <= Operands.capacity()) {
374 Operands.push_back(Op);
376 // Set the parent of the operand.
377 Operands.back().ParentMI = this;
379 // If the operand is a register, update the operand's use list.
381 Operands.back().AddRegOperandToRegInfo(getRegInfo());
386 // Otherwise, we have to insert a real operand before any implicit ones.
387 unsigned OpNo = Operands.size()-NumImplicitOps;
389 MachineRegisterInfo *RegInfo = getRegInfo();
391 // If this instruction isn't embedded into a function, then we don't need to
392 // update any operand lists.
394 // Simple insertion, no reginfo update needed for other register operands.
395 Operands.insert(Operands.begin()+OpNo, Op);
396 Operands[OpNo].ParentMI = this;
398 // Do explicitly set the reginfo for this operand though, to ensure the
399 // next/prev fields are properly nulled out.
400 if (Operands[OpNo].isReg())
401 Operands[OpNo].AddRegOperandToRegInfo(0);
403 } else if (Operands.size()+1 <= Operands.capacity()) {
404 // Otherwise, we have to remove register operands from their register use
405 // list, add the operand, then add the register operands back to their use
406 // list. This also must handle the case when the operand list reallocates
407 // to somewhere else.
409 // If insertion of this operand won't cause reallocation of the operand
410 // list, just remove the implicit operands, add the operand, then re-add all
411 // the rest of the operands.
412 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
413 assert(Operands[i].isReg() && "Should only be an implicit reg!");
414 Operands[i].RemoveRegOperandFromRegInfo();
417 // Add the operand. If it is a register, add it to the reg list.
418 Operands.insert(Operands.begin()+OpNo, Op);
419 Operands[OpNo].ParentMI = this;
421 if (Operands[OpNo].isReg())
422 Operands[OpNo].AddRegOperandToRegInfo(RegInfo);
424 // Re-add all the implicit ops.
425 for (unsigned i = OpNo+1, e = Operands.size(); i != e; ++i) {
426 assert(Operands[i].isReg() && "Should only be an implicit reg!");
427 Operands[i].AddRegOperandToRegInfo(RegInfo);
430 // Otherwise, we will be reallocating the operand list. Remove all reg
431 // operands from their list, then readd them after the operand list is
433 RemoveRegOperandsFromUseLists();
435 Operands.insert(Operands.begin()+OpNo, Op);
436 Operands[OpNo].ParentMI = this;
438 // Re-add all the operands.
439 AddRegOperandsToUseLists(*RegInfo);
443 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
444 /// fewer operand than it started with.
446 void MachineInstr::RemoveOperand(unsigned OpNo) {
447 assert(OpNo < Operands.size() && "Invalid operand number");
449 // Special case removing the last one.
450 if (OpNo == Operands.size()-1) {
451 // If needed, remove from the reg def/use list.
452 if (Operands.back().isReg() && Operands.back().isOnRegUseList())
453 Operands.back().RemoveRegOperandFromRegInfo();
459 // Otherwise, we are removing an interior operand. If we have reginfo to
460 // update, remove all operands that will be shifted down from their reg lists,
461 // move everything down, then re-add them.
462 MachineRegisterInfo *RegInfo = getRegInfo();
464 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
465 if (Operands[i].isReg())
466 Operands[i].RemoveRegOperandFromRegInfo();
470 Operands.erase(Operands.begin()+OpNo);
473 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
474 if (Operands[i].isReg())
475 Operands[i].AddRegOperandToRegInfo(RegInfo);
481 /// removeFromParent - This method unlinks 'this' from the containing basic
482 /// block, and returns it, but does not delete it.
483 MachineInstr *MachineInstr::removeFromParent() {
484 assert(getParent() && "Not embedded in a basic block!");
485 getParent()->remove(this);
490 /// OperandComplete - Return true if it's illegal to add a new operand
492 bool MachineInstr::OperandsComplete() const {
493 unsigned short NumOperands = TID->getNumOperands();
494 if (!TID->isVariadic() && getNumOperands()-NumImplicitOps >= NumOperands)
495 return true; // Broken: we have all the operands of this instruction!
499 /// getNumExplicitOperands - Returns the number of non-implicit operands.
501 unsigned MachineInstr::getNumExplicitOperands() const {
502 unsigned NumOperands = TID->getNumOperands();
503 if (!TID->isVariadic())
506 for (unsigned e = getNumOperands(); NumOperands != e; ++NumOperands) {
507 const MachineOperand &MO = getOperand(NumOperands);
508 if (!MO.isRegister() || !MO.isImplicit())
515 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
516 /// the specific register or -1 if it is not found. It further tightening
517 /// the search criteria to a use that kills the register if isKill is true.
518 int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill) const {
519 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
520 const MachineOperand &MO = getOperand(i);
521 if (MO.isRegister() && MO.isUse() && MO.getReg() == Reg)
522 if (!isKill || MO.isKill())
528 /// findRegisterDefOperand() - Returns the MachineOperand that is a def of
529 /// the specific register or NULL if it is not found.
530 MachineOperand *MachineInstr::findRegisterDefOperand(unsigned Reg) {
531 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
532 MachineOperand &MO = getOperand(i);
533 if (MO.isRegister() && MO.isDef() && MO.getReg() == Reg)
539 /// findFirstPredOperandIdx() - Find the index of the first operand in the
540 /// operand list that is used to represent the predicate. It returns -1 if
542 int MachineInstr::findFirstPredOperandIdx() const {
543 const TargetInstrDesc &TID = getDesc();
544 if (TID.isPredicable()) {
545 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
546 if (TID.OpInfo[i].isPredicate())
553 /// isRegReDefinedByTwoAddr - Returns true if the Reg re-definition is due
554 /// to two addr elimination.
555 bool MachineInstr::isRegReDefinedByTwoAddr(unsigned Reg) const {
556 const TargetInstrDesc &TID = getDesc();
557 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
558 const MachineOperand &MO1 = getOperand(i);
559 if (MO1.isRegister() && MO1.isDef() && MO1.getReg() == Reg) {
560 for (unsigned j = i+1; j < e; ++j) {
561 const MachineOperand &MO2 = getOperand(j);
562 if (MO2.isRegister() && MO2.isUse() && MO2.getReg() == Reg &&
563 TID.getOperandConstraint(j, TOI::TIED_TO) == (int)i)
571 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
573 void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
574 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
575 const MachineOperand &MO = MI->getOperand(i);
576 if (!MO.isRegister() || (!MO.isKill() && !MO.isDead()))
578 for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
579 MachineOperand &MOp = getOperand(j);
580 if (!MOp.isIdenticalTo(MO))
591 /// copyPredicates - Copies predicate operand(s) from MI.
592 void MachineInstr::copyPredicates(const MachineInstr *MI) {
593 const TargetInstrDesc &TID = MI->getDesc();
594 if (TID.isPredicable()) {
595 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
596 if (TID.OpInfo[i].isPredicate()) {
597 // Predicated operands must be last operands.
598 addOperand(MI->getOperand(i));
604 void MachineInstr::dump() const {
605 cerr << " " << *this;
608 void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
609 // Specialize printing if op#0 is definition
610 unsigned StartOp = 0;
611 if (getNumOperands() && getOperand(0).isRegister() && getOperand(0).isDef()) {
612 getOperand(0).print(OS, TM);
614 ++StartOp; // Don't print this operand again!
617 OS << getDesc().getName();
619 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
623 getOperand(i).print(OS, TM);
626 if (getNumMemOperands() > 0) {
628 for (unsigned i = 0; i < getNumMemOperands(); i++) {
629 const MemOperand &MRO = getMemOperand(i);
630 const Value *V = MRO.getValue();
632 assert(V && "SV missing.");
633 assert((MRO.isLoad() || MRO.isStore()) &&
634 "SV has to be a load, store or both.");
636 if (MRO.isVolatile())
645 if (!V->getName().empty())
646 OS << "[" << V->getName() << " + " << MRO.getOffset() << "]";
647 else if (isa<PseudoSourceValue>(V))
648 OS << "[" << *V << " + " << MRO.getOffset() << "]";
650 OS << "[" << V << " + " << MRO.getOffset() << "]";
657 bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
658 const MRegisterInfo *RegInfo,
659 bool AddIfNotFound) {
661 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
662 MachineOperand &MO = getOperand(i);
663 if (MO.isRegister() && MO.isUse()) {
664 unsigned Reg = MO.getReg();
667 if (Reg == IncomingReg) {
671 } else if (MRegisterInfo::isPhysicalRegister(Reg) &&
672 MRegisterInfo::isPhysicalRegister(IncomingReg) &&
673 RegInfo->isSuperRegister(IncomingReg, Reg) &&
675 // A super-register kill already exists.
680 // If not found, this means an alias of one of the operand is killed. Add a
681 // new implicit operand if required.
682 if (!Found && AddIfNotFound) {
683 addOperand(MachineOperand::CreateReg(IncomingReg, false/*IsDef*/,
684 true/*IsImp*/,true/*IsKill*/));
690 bool MachineInstr::addRegisterDead(unsigned IncomingReg,
691 const MRegisterInfo *RegInfo,
692 bool AddIfNotFound) {
694 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
695 MachineOperand &MO = getOperand(i);
696 if (MO.isRegister() && MO.isDef()) {
697 unsigned Reg = MO.getReg();
700 if (Reg == IncomingReg) {
704 } else if (MRegisterInfo::isPhysicalRegister(Reg) &&
705 MRegisterInfo::isPhysicalRegister(IncomingReg) &&
706 RegInfo->isSuperRegister(IncomingReg, Reg) &&
708 // There exists a super-register that's marked dead.
713 // If not found, this means an alias of one of the operand is dead. Add a
714 // new implicit operand.
715 if (!Found && AddIfNotFound) {
716 addOperand(MachineOperand::CreateReg(IncomingReg, true/*IsDef*/,
717 true/*IsImp*/,false/*IsKill*/,
724 /// copyKillDeadInfo - copies killed/dead information from one instr to another
725 void MachineInstr::copyKillDeadInfo(MachineInstr *OldMI,
726 const MRegisterInfo *RegInfo) {
727 // If the instruction defines any virtual registers, update the VarInfo,
728 // kill and dead information for the instruction.
729 for (unsigned i = 0, e = OldMI->getNumOperands(); i != e; ++i) {
730 MachineOperand &MO = OldMI->getOperand(i);
731 if (MO.isRegister() && MO.getReg() &&
732 MRegisterInfo::isVirtualRegister(MO.getReg())) {
733 unsigned Reg = MO.getReg();
737 addRegisterDead(Reg, RegInfo);
742 addRegisterKilled(Reg, RegInfo);