1 //===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Methods common to all machine instructions.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "llvm/Constants.h"
16 #include "llvm/DebugInfo.h"
17 #include "llvm/Function.h"
18 #include "llvm/InlineAsm.h"
19 #include "llvm/LLVMContext.h"
20 #include "llvm/Metadata.h"
21 #include "llvm/Module.h"
22 #include "llvm/Type.h"
23 #include "llvm/Value.h"
24 #include "llvm/Assembly/Writer.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineMemOperand.h"
28 #include "llvm/CodeGen/MachineModuleInfo.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/PseudoSourceValue.h"
31 #include "llvm/MC/MCInstrDesc.h"
32 #include "llvm/MC/MCSymbol.h"
33 #include "llvm/Target/TargetMachine.h"
34 #include "llvm/Target/TargetInstrInfo.h"
35 #include "llvm/Target/TargetRegisterInfo.h"
36 #include "llvm/Analysis/AliasAnalysis.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/LeakDetector.h"
40 #include "llvm/Support/MathExtras.h"
41 #include "llvm/Support/raw_ostream.h"
42 #include "llvm/ADT/FoldingSet.h"
43 #include "llvm/ADT/Hashing.h"
46 //===----------------------------------------------------------------------===//
47 // MachineOperand Implementation
48 //===----------------------------------------------------------------------===//
50 void MachineOperand::setReg(unsigned Reg) {
51 if (getReg() == Reg) return; // No change.
53 // Otherwise, we have to change the register. If this operand is embedded
54 // into a machine function, we need to update the old and new register's
56 if (MachineInstr *MI = getParent())
57 if (MachineBasicBlock *MBB = MI->getParent())
58 if (MachineFunction *MF = MBB->getParent()) {
59 MachineRegisterInfo &MRI = MF->getRegInfo();
60 MRI.removeRegOperandFromUseList(this);
61 SmallContents.RegNo = Reg;
62 MRI.addRegOperandToUseList(this);
66 // Otherwise, just change the register, no problem. :)
67 SmallContents.RegNo = Reg;
70 void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx,
71 const TargetRegisterInfo &TRI) {
72 assert(TargetRegisterInfo::isVirtualRegister(Reg));
73 if (SubIdx && getSubReg())
74 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
80 void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) {
81 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
83 Reg = TRI.getSubReg(Reg, getSubReg());
84 // Note that getSubReg() may return 0 if the sub-register doesn't exist.
85 // That won't happen in legal code.
91 /// Change a def to a use, or a use to a def.
92 void MachineOperand::setIsDef(bool Val) {
93 assert(isReg() && "Wrong MachineOperand accessor");
94 assert((!Val || !isDebug()) && "Marking a debug operation as def");
97 // MRI may keep uses and defs in different list positions.
98 if (MachineInstr *MI = getParent())
99 if (MachineBasicBlock *MBB = MI->getParent())
100 if (MachineFunction *MF = MBB->getParent()) {
101 MachineRegisterInfo &MRI = MF->getRegInfo();
102 MRI.removeRegOperandFromUseList(this);
104 MRI.addRegOperandToUseList(this);
110 /// ChangeToImmediate - Replace this operand with a new immediate operand of
111 /// the specified value. If an operand is known to be an immediate already,
112 /// the setImm method should be used.
113 void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
114 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
115 // If this operand is currently a register operand, and if this is in a
116 // function, deregister the operand from the register's use/def list.
117 if (isReg() && isOnRegUseList())
118 if (MachineInstr *MI = getParent())
119 if (MachineBasicBlock *MBB = MI->getParent())
120 if (MachineFunction *MF = MBB->getParent())
121 MF->getRegInfo().removeRegOperandFromUseList(this);
123 OpKind = MO_Immediate;
124 Contents.ImmVal = ImmVal;
127 /// ChangeToRegister - Replace this operand with a new register operand of
128 /// the specified value. If an operand is known to be an register already,
129 /// the setReg method should be used.
130 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
131 bool isKill, bool isDead, bool isUndef,
133 MachineRegisterInfo *RegInfo = 0;
134 if (MachineInstr *MI = getParent())
135 if (MachineBasicBlock *MBB = MI->getParent())
136 if (MachineFunction *MF = MBB->getParent())
137 RegInfo = &MF->getRegInfo();
138 // If this operand is already a register operand, remove it from the
139 // register's use/def lists.
140 bool WasReg = isReg();
141 if (RegInfo && WasReg)
142 RegInfo->removeRegOperandFromUseList(this);
144 // Change this to a register and set the reg#.
145 OpKind = MO_Register;
146 SmallContents.RegNo = Reg;
153 IsInternalRead = false;
154 IsEarlyClobber = false;
156 // Ensure isOnRegUseList() returns false.
157 Contents.Reg.Prev = 0;
158 // Preserve the tie bit when the operand was already a register.
162 // If this operand is embedded in a function, add the operand to the
163 // register's use/def list.
165 RegInfo->addRegOperandToUseList(this);
168 /// isIdenticalTo - Return true if this operand is identical to the specified
169 /// operand. Note that this should stay in sync with the hash_value overload
171 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
172 if (getType() != Other.getType() ||
173 getTargetFlags() != Other.getTargetFlags())
177 case MachineOperand::MO_Register:
178 return getReg() == Other.getReg() && isDef() == Other.isDef() &&
179 getSubReg() == Other.getSubReg();
180 case MachineOperand::MO_Immediate:
181 return getImm() == Other.getImm();
182 case MachineOperand::MO_CImmediate:
183 return getCImm() == Other.getCImm();
184 case MachineOperand::MO_FPImmediate:
185 return getFPImm() == Other.getFPImm();
186 case MachineOperand::MO_MachineBasicBlock:
187 return getMBB() == Other.getMBB();
188 case MachineOperand::MO_FrameIndex:
189 return getIndex() == Other.getIndex();
190 case MachineOperand::MO_ConstantPoolIndex:
191 case MachineOperand::MO_TargetIndex:
192 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
193 case MachineOperand::MO_JumpTableIndex:
194 return getIndex() == Other.getIndex();
195 case MachineOperand::MO_GlobalAddress:
196 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
197 case MachineOperand::MO_ExternalSymbol:
198 return !strcmp(getSymbolName(), Other.getSymbolName()) &&
199 getOffset() == Other.getOffset();
200 case MachineOperand::MO_BlockAddress:
201 return getBlockAddress() == Other.getBlockAddress();
202 case MO_RegisterMask:
203 return getRegMask() == Other.getRegMask();
204 case MachineOperand::MO_MCSymbol:
205 return getMCSymbol() == Other.getMCSymbol();
206 case MachineOperand::MO_Metadata:
207 return getMetadata() == Other.getMetadata();
209 llvm_unreachable("Invalid machine operand type");
212 // Note: this must stay exactly in sync with isIdenticalTo above.
213 hash_code llvm::hash_value(const MachineOperand &MO) {
214 switch (MO.getType()) {
215 case MachineOperand::MO_Register:
216 // Register operands don't have target flags.
217 return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(), MO.isDef());
218 case MachineOperand::MO_Immediate:
219 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
220 case MachineOperand::MO_CImmediate:
221 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
222 case MachineOperand::MO_FPImmediate:
223 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
224 case MachineOperand::MO_MachineBasicBlock:
225 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
226 case MachineOperand::MO_FrameIndex:
227 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
228 case MachineOperand::MO_ConstantPoolIndex:
229 case MachineOperand::MO_TargetIndex:
230 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
232 case MachineOperand::MO_JumpTableIndex:
233 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
234 case MachineOperand::MO_ExternalSymbol:
235 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
237 case MachineOperand::MO_GlobalAddress:
238 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
240 case MachineOperand::MO_BlockAddress:
241 return hash_combine(MO.getType(), MO.getTargetFlags(),
242 MO.getBlockAddress());
243 case MachineOperand::MO_RegisterMask:
244 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask());
245 case MachineOperand::MO_Metadata:
246 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
247 case MachineOperand::MO_MCSymbol:
248 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
250 llvm_unreachable("Invalid machine operand type");
253 /// print - Print the specified machine operand.
255 void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
256 // If the instruction is embedded into a basic block, we can find the
257 // target info for the instruction.
259 if (const MachineInstr *MI = getParent())
260 if (const MachineBasicBlock *MBB = MI->getParent())
261 if (const MachineFunction *MF = MBB->getParent())
262 TM = &MF->getTarget();
263 const TargetRegisterInfo *TRI = TM ? TM->getRegisterInfo() : 0;
266 case MachineOperand::MO_Register:
267 OS << PrintReg(getReg(), TRI, getSubReg());
269 if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
270 isInternalRead() || isEarlyClobber() || isTied()) {
272 bool NeedComma = false;
274 if (NeedComma) OS << ',';
275 if (isEarlyClobber())
276 OS << "earlyclobber,";
281 // <def,read-undef> only makes sense when getSubReg() is set.
282 // Don't clutter the output otherwise.
283 if (isUndef() && getSubReg())
285 } else if (isImplicit()) {
291 if (NeedComma) OS << ',';
296 if (NeedComma) OS << ',';
300 if (isUndef() && isUse()) {
301 if (NeedComma) OS << ',';
305 if (isInternalRead()) {
306 if (NeedComma) OS << ',';
311 if (NeedComma) OS << ',';
318 case MachineOperand::MO_Immediate:
321 case MachineOperand::MO_CImmediate:
322 getCImm()->getValue().print(OS, false);
324 case MachineOperand::MO_FPImmediate:
325 if (getFPImm()->getType()->isFloatTy())
326 OS << getFPImm()->getValueAPF().convertToFloat();
328 OS << getFPImm()->getValueAPF().convertToDouble();
330 case MachineOperand::MO_MachineBasicBlock:
331 OS << "<BB#" << getMBB()->getNumber() << ">";
333 case MachineOperand::MO_FrameIndex:
334 OS << "<fi#" << getIndex() << '>';
336 case MachineOperand::MO_ConstantPoolIndex:
337 OS << "<cp#" << getIndex();
338 if (getOffset()) OS << "+" << getOffset();
341 case MachineOperand::MO_TargetIndex:
342 OS << "<ti#" << getIndex();
343 if (getOffset()) OS << "+" << getOffset();
346 case MachineOperand::MO_JumpTableIndex:
347 OS << "<jt#" << getIndex() << '>';
349 case MachineOperand::MO_GlobalAddress:
351 WriteAsOperand(OS, getGlobal(), /*PrintType=*/false);
352 if (getOffset()) OS << "+" << getOffset();
355 case MachineOperand::MO_ExternalSymbol:
356 OS << "<es:" << getSymbolName();
357 if (getOffset()) OS << "+" << getOffset();
360 case MachineOperand::MO_BlockAddress:
362 WriteAsOperand(OS, getBlockAddress(), /*PrintType=*/false);
365 case MachineOperand::MO_RegisterMask:
368 case MachineOperand::MO_Metadata:
370 WriteAsOperand(OS, getMetadata(), /*PrintType=*/false);
373 case MachineOperand::MO_MCSymbol:
374 OS << "<MCSym=" << *getMCSymbol() << '>';
378 if (unsigned TF = getTargetFlags())
379 OS << "[TF=" << TF << ']';
382 //===----------------------------------------------------------------------===//
383 // MachineMemOperand Implementation
384 //===----------------------------------------------------------------------===//
386 /// getAddrSpace - Return the LLVM IR address space number that this pointer
388 unsigned MachinePointerInfo::getAddrSpace() const {
389 if (V == 0) return 0;
390 return cast<PointerType>(V->getType())->getAddressSpace();
393 /// getConstantPool - Return a MachinePointerInfo record that refers to the
395 MachinePointerInfo MachinePointerInfo::getConstantPool() {
396 return MachinePointerInfo(PseudoSourceValue::getConstantPool());
399 /// getFixedStack - Return a MachinePointerInfo record that refers to the
400 /// the specified FrameIndex.
401 MachinePointerInfo MachinePointerInfo::getFixedStack(int FI, int64_t offset) {
402 return MachinePointerInfo(PseudoSourceValue::getFixedStack(FI), offset);
405 MachinePointerInfo MachinePointerInfo::getJumpTable() {
406 return MachinePointerInfo(PseudoSourceValue::getJumpTable());
409 MachinePointerInfo MachinePointerInfo::getGOT() {
410 return MachinePointerInfo(PseudoSourceValue::getGOT());
413 MachinePointerInfo MachinePointerInfo::getStack(int64_t Offset) {
414 return MachinePointerInfo(PseudoSourceValue::getStack(), Offset);
417 MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, unsigned f,
418 uint64_t s, unsigned int a,
419 const MDNode *TBAAInfo,
420 const MDNode *Ranges)
421 : PtrInfo(ptrinfo), Size(s),
422 Flags((f & ((1 << MOMaxBits) - 1)) | ((Log2_32(a) + 1) << MOMaxBits)),
423 TBAAInfo(TBAAInfo), Ranges(Ranges) {
424 assert((PtrInfo.V == 0 || isa<PointerType>(PtrInfo.V->getType())) &&
425 "invalid pointer value");
426 assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
427 assert((isLoad() || isStore()) && "Not a load/store!");
430 /// Profile - Gather unique data for the object.
432 void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
433 ID.AddInteger(getOffset());
435 ID.AddPointer(getValue());
436 ID.AddInteger(Flags);
439 void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
440 // The Value and Offset may differ due to CSE. But the flags and size
441 // should be the same.
442 assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
443 assert(MMO->getSize() == getSize() && "Size mismatch!");
445 if (MMO->getBaseAlignment() >= getBaseAlignment()) {
446 // Update the alignment value.
447 Flags = (Flags & ((1 << MOMaxBits) - 1)) |
448 ((Log2_32(MMO->getBaseAlignment()) + 1) << MOMaxBits);
449 // Also update the base and offset, because the new alignment may
450 // not be applicable with the old ones.
451 PtrInfo = MMO->PtrInfo;
455 /// getAlignment - Return the minimum known alignment in bytes of the
456 /// actual memory reference.
457 uint64_t MachineMemOperand::getAlignment() const {
458 return MinAlign(getBaseAlignment(), getOffset());
461 raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineMemOperand &MMO) {
462 assert((MMO.isLoad() || MMO.isStore()) &&
463 "SV has to be a load, store or both.");
465 if (MMO.isVolatile())
474 // Print the address information.
479 WriteAsOperand(OS, MMO.getValue(), /*PrintType=*/false);
481 // If the alignment of the memory reference itself differs from the alignment
482 // of the base pointer, print the base alignment explicitly, next to the base
484 if (MMO.getBaseAlignment() != MMO.getAlignment())
485 OS << "(align=" << MMO.getBaseAlignment() << ")";
487 if (MMO.getOffset() != 0)
488 OS << "+" << MMO.getOffset();
491 // Print the alignment of the reference.
492 if (MMO.getBaseAlignment() != MMO.getAlignment() ||
493 MMO.getBaseAlignment() != MMO.getSize())
494 OS << "(align=" << MMO.getAlignment() << ")";
497 if (const MDNode *TBAAInfo = MMO.getTBAAInfo()) {
499 if (TBAAInfo->getNumOperands() > 0)
500 WriteAsOperand(OS, TBAAInfo->getOperand(0), /*PrintType=*/false);
506 // Print nontemporal info.
507 if (MMO.isNonTemporal())
508 OS << "(nontemporal)";
513 //===----------------------------------------------------------------------===//
514 // MachineInstr Implementation
515 //===----------------------------------------------------------------------===//
517 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
518 /// MCID NULL and no operands.
519 MachineInstr::MachineInstr()
520 : MCID(0), Flags(0), AsmPrinterFlags(0),
521 NumMemRefs(0), MemRefs(0),
523 // Make sure that we get added to a machine basicblock
524 LeakDetector::addGarbageObject(this);
527 void MachineInstr::addImplicitDefUseOperands() {
528 if (MCID->ImplicitDefs)
529 for (const uint16_t *ImpDefs = MCID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
530 addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
531 if (MCID->ImplicitUses)
532 for (const uint16_t *ImpUses = MCID->getImplicitUses(); *ImpUses; ++ImpUses)
533 addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
536 /// MachineInstr ctor - This constructor creates a MachineInstr and adds the
537 /// implicit operands. It reserves space for the number of operands specified by
539 MachineInstr::MachineInstr(const MCInstrDesc &tid, bool NoImp)
540 : MCID(&tid), Flags(0), AsmPrinterFlags(0),
541 NumMemRefs(0), MemRefs(0), Parent(0) {
542 unsigned NumImplicitOps = 0;
544 NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
545 Operands.reserve(NumImplicitOps + MCID->getNumOperands());
547 addImplicitDefUseOperands();
548 // Make sure that we get added to a machine basicblock
549 LeakDetector::addGarbageObject(this);
552 /// MachineInstr ctor - As above, but with a DebugLoc.
553 MachineInstr::MachineInstr(const MCInstrDesc &tid, const DebugLoc dl,
555 : MCID(&tid), Flags(0), AsmPrinterFlags(0),
556 NumMemRefs(0), MemRefs(0), Parent(0), debugLoc(dl) {
557 unsigned NumImplicitOps = 0;
559 NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
560 Operands.reserve(NumImplicitOps + MCID->getNumOperands());
562 addImplicitDefUseOperands();
563 // Make sure that we get added to a machine basicblock
564 LeakDetector::addGarbageObject(this);
567 /// MachineInstr ctor - Work exactly the same as the ctor two above, except
568 /// that the MachineInstr is created and added to the end of the specified
570 MachineInstr::MachineInstr(MachineBasicBlock *MBB, const MCInstrDesc &tid)
571 : MCID(&tid), Flags(0), AsmPrinterFlags(0),
572 NumMemRefs(0), MemRefs(0), Parent(0) {
573 assert(MBB && "Cannot use inserting ctor with null basic block!");
574 unsigned NumImplicitOps =
575 MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
576 Operands.reserve(NumImplicitOps + MCID->getNumOperands());
577 addImplicitDefUseOperands();
578 // Make sure that we get added to a machine basicblock
579 LeakDetector::addGarbageObject(this);
580 MBB->push_back(this); // Add instruction to end of basic block!
583 /// MachineInstr ctor - As above, but with a DebugLoc.
585 MachineInstr::MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
586 const MCInstrDesc &tid)
587 : MCID(&tid), Flags(0), AsmPrinterFlags(0),
588 NumMemRefs(0), MemRefs(0), Parent(0), debugLoc(dl) {
589 assert(MBB && "Cannot use inserting ctor with null basic block!");
590 unsigned NumImplicitOps =
591 MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
592 Operands.reserve(NumImplicitOps + MCID->getNumOperands());
593 addImplicitDefUseOperands();
594 // Make sure that we get added to a machine basicblock
595 LeakDetector::addGarbageObject(this);
596 MBB->push_back(this); // Add instruction to end of basic block!
599 /// MachineInstr ctor - Copies MachineInstr arg exactly
601 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
602 : MCID(&MI.getDesc()), Flags(0), AsmPrinterFlags(0),
603 NumMemRefs(MI.NumMemRefs), MemRefs(MI.MemRefs),
604 Parent(0), debugLoc(MI.getDebugLoc()) {
605 Operands.reserve(MI.getNumOperands());
608 for (unsigned i = 0; i != MI.getNumOperands(); ++i)
609 addOperand(MI.getOperand(i));
611 // Copy all the flags.
614 // Set parent to null.
617 LeakDetector::addGarbageObject(this);
620 MachineInstr::~MachineInstr() {
621 LeakDetector::removeGarbageObject(this);
623 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
624 assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
625 assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
626 "Reg operand def/use list corrupted");
631 /// getRegInfo - If this instruction is embedded into a MachineFunction,
632 /// return the MachineRegisterInfo object for the current function, otherwise
634 MachineRegisterInfo *MachineInstr::getRegInfo() {
635 if (MachineBasicBlock *MBB = getParent())
636 return &MBB->getParent()->getRegInfo();
640 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
641 /// this instruction from their respective use lists. This requires that the
642 /// operands already be on their use lists.
643 void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo &MRI) {
644 for (unsigned i = 0, e = Operands.size(); i != e; ++i)
645 if (Operands[i].isReg())
646 MRI.removeRegOperandFromUseList(&Operands[i]);
649 /// AddRegOperandsToUseLists - Add all of the register operands in
650 /// this instruction from their respective use lists. This requires that the
651 /// operands not be on their use lists yet.
652 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &MRI) {
653 for (unsigned i = 0, e = Operands.size(); i != e; ++i)
654 if (Operands[i].isReg())
655 MRI.addRegOperandToUseList(&Operands[i]);
658 /// addOperand - Add the specified operand to the instruction. If it is an
659 /// implicit operand, it is added to the end of the operand list. If it is
660 /// an explicit operand it is added at the end of the explicit operand list
661 /// (before the first implicit operand).
662 void MachineInstr::addOperand(const MachineOperand &Op) {
663 assert(MCID && "Cannot add operands before providing an instr descriptor");
664 bool isImpReg = Op.isReg() && Op.isImplicit();
665 MachineRegisterInfo *RegInfo = getRegInfo();
667 // If the Operands backing store is reallocated, all register operands must
668 // be removed and re-added to RegInfo. It is storing pointers to operands.
669 bool Reallocate = RegInfo &&
670 !Operands.empty() && Operands.size() == Operands.capacity();
672 // Find the insert location for the new operand. Implicit registers go at
673 // the end, everything goes before the implicit regs.
674 unsigned OpNo = Operands.size();
676 // Remove all the implicit operands from RegInfo if they need to be shifted.
677 // FIXME: Allow mixed explicit and implicit operands on inline asm.
678 // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
679 // implicit-defs, but they must not be moved around. See the FIXME in
681 if (!isImpReg && !isInlineAsm()) {
682 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
685 RegInfo->removeRegOperandFromUseList(&Operands[OpNo]);
689 // OpNo now points as the desired insertion point. Unless this is a variadic
690 // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
691 // RegMask operands go between the explicit and implicit operands.
692 assert((isImpReg || Op.isRegMask() || MCID->isVariadic() ||
693 OpNo < MCID->getNumOperands()) &&
694 "Trying to add an operand to a machine instr that is already done!");
696 // All operands from OpNo have been removed from RegInfo. If the Operands
697 // backing store needs to be reallocated, we also need to remove any other
698 // register operands.
700 for (unsigned i = 0; i != OpNo; ++i)
701 if (Operands[i].isReg())
702 RegInfo->removeRegOperandFromUseList(&Operands[i]);
704 // Insert the new operand at OpNo.
705 Operands.insert(Operands.begin() + OpNo, Op);
706 Operands[OpNo].ParentMI = this;
708 // The Operands backing store has now been reallocated, so we can re-add the
709 // operands before OpNo.
711 for (unsigned i = 0; i != OpNo; ++i)
712 if (Operands[i].isReg())
713 RegInfo->addRegOperandToUseList(&Operands[i]);
715 // When adding a register operand, tell RegInfo about it.
716 if (Operands[OpNo].isReg()) {
717 // Ensure isOnRegUseList() returns false, regardless of Op's status.
718 Operands[OpNo].Contents.Reg.Prev = 0;
719 // Ignore existing IsTied bit. This is not a property that can be copied.
720 Operands[OpNo].IsTied = false;
721 // Add the new operand to RegInfo.
723 RegInfo->addRegOperandToUseList(&Operands[OpNo]);
724 // The MCID operand information isn't accurate until we start adding
725 // explicit operands. The implicit operands are added first, then the
726 // explicits are inserted before them.
728 // Set the IsTied bit if MC indicates this use is tied to a def.
729 if (Operands[OpNo].isUse()) {
730 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO);
732 tieOperands(DefIdx, OpNo);
734 // If the register operand is flagged as early, mark the operand as such.
735 if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
736 Operands[OpNo].setIsEarlyClobber(true);
740 // Re-add all the implicit ops.
742 for (unsigned i = OpNo + 1, e = Operands.size(); i != e; ++i) {
743 assert(Operands[i].isReg() && "Should only be an implicit reg!");
744 RegInfo->addRegOperandToUseList(&Operands[i]);
749 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
750 /// fewer operand than it started with.
752 void MachineInstr::RemoveOperand(unsigned OpNo) {
753 assert(OpNo < Operands.size() && "Invalid operand number");
754 untieRegOperand(OpNo);
755 MachineRegisterInfo *RegInfo = getRegInfo();
757 // Special case removing the last one.
758 if (OpNo == Operands.size()-1) {
759 // If needed, remove from the reg def/use list.
760 if (RegInfo && Operands.back().isReg() && Operands.back().isOnRegUseList())
761 RegInfo->removeRegOperandFromUseList(&Operands.back());
767 // Otherwise, we are removing an interior operand. If we have reginfo to
768 // update, remove all operands that will be shifted down from their reg lists,
769 // move everything down, then re-add them.
771 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
772 if (Operands[i].isReg())
773 RegInfo->removeRegOperandFromUseList(&Operands[i]);
777 Operands.erase(Operands.begin()+OpNo);
780 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
781 if (Operands[i].isReg())
782 RegInfo->addRegOperandToUseList(&Operands[i]);
787 /// addMemOperand - Add a MachineMemOperand to the machine instruction.
788 /// This function should be used only occasionally. The setMemRefs function
789 /// is the primary method for setting up a MachineInstr's MemRefs list.
790 void MachineInstr::addMemOperand(MachineFunction &MF,
791 MachineMemOperand *MO) {
792 mmo_iterator OldMemRefs = MemRefs;
793 uint16_t OldNumMemRefs = NumMemRefs;
795 uint16_t NewNum = NumMemRefs + 1;
796 mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum);
798 std::copy(OldMemRefs, OldMemRefs + OldNumMemRefs, NewMemRefs);
799 NewMemRefs[NewNum - 1] = MO;
801 MemRefs = NewMemRefs;
805 bool MachineInstr::hasPropertyInBundle(unsigned Mask, QueryType Type) const {
806 const MachineBasicBlock *MBB = getParent();
807 MachineBasicBlock::const_instr_iterator MII = *this; ++MII;
808 while (MII != MBB->end() && MII->isInsideBundle()) {
809 if (MII->getDesc().getFlags() & Mask) {
810 if (Type == AnyInBundle)
813 if (Type == AllInBundle)
819 return Type == AllInBundle;
822 bool MachineInstr::isIdenticalTo(const MachineInstr *Other,
823 MICheckType Check) const {
824 // If opcodes or number of operands are not the same then the two
825 // instructions are obviously not identical.
826 if (Other->getOpcode() != getOpcode() ||
827 Other->getNumOperands() != getNumOperands())
831 // Both instructions are bundles, compare MIs inside the bundle.
832 MachineBasicBlock::const_instr_iterator I1 = *this;
833 MachineBasicBlock::const_instr_iterator E1 = getParent()->instr_end();
834 MachineBasicBlock::const_instr_iterator I2 = *Other;
835 MachineBasicBlock::const_instr_iterator E2= Other->getParent()->instr_end();
836 while (++I1 != E1 && I1->isInsideBundle()) {
838 if (I2 == E2 || !I2->isInsideBundle() || !I1->isIdenticalTo(I2, Check))
843 // Check operands to make sure they match.
844 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
845 const MachineOperand &MO = getOperand(i);
846 const MachineOperand &OMO = Other->getOperand(i);
848 if (!MO.isIdenticalTo(OMO))
853 // Clients may or may not want to ignore defs when testing for equality.
854 // For example, machine CSE pass only cares about finding common
855 // subexpressions, so it's safe to ignore virtual register defs.
857 if (Check == IgnoreDefs)
859 else if (Check == IgnoreVRegDefs) {
860 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) ||
861 TargetRegisterInfo::isPhysicalRegister(OMO.getReg()))
862 if (MO.getReg() != OMO.getReg())
865 if (!MO.isIdenticalTo(OMO))
867 if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
871 if (!MO.isIdenticalTo(OMO))
873 if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
877 // If DebugLoc does not match then two dbg.values are not identical.
879 if (!getDebugLoc().isUnknown() && !Other->getDebugLoc().isUnknown()
880 && getDebugLoc() != Other->getDebugLoc())
885 /// removeFromParent - This method unlinks 'this' from the containing basic
886 /// block, and returns it, but does not delete it.
887 MachineInstr *MachineInstr::removeFromParent() {
888 assert(getParent() && "Not embedded in a basic block!");
890 // If it's a bundle then remove the MIs inside the bundle as well.
892 MachineBasicBlock *MBB = getParent();
893 MachineBasicBlock::instr_iterator MII = *this; ++MII;
894 MachineBasicBlock::instr_iterator E = MBB->instr_end();
895 while (MII != E && MII->isInsideBundle()) {
896 MachineInstr *MI = &*MII;
901 getParent()->remove(this);
906 /// eraseFromParent - This method unlinks 'this' from the containing basic
907 /// block, and deletes it.
908 void MachineInstr::eraseFromParent() {
909 assert(getParent() && "Not embedded in a basic block!");
910 // If it's a bundle then remove the MIs inside the bundle as well.
912 MachineBasicBlock *MBB = getParent();
913 MachineBasicBlock::instr_iterator MII = *this; ++MII;
914 MachineBasicBlock::instr_iterator E = MBB->instr_end();
915 while (MII != E && MII->isInsideBundle()) {
916 MachineInstr *MI = &*MII;
921 // Erase the individual instruction, which may itself be inside a bundle.
922 getParent()->erase_instr(this);
926 /// getNumExplicitOperands - Returns the number of non-implicit operands.
928 unsigned MachineInstr::getNumExplicitOperands() const {
929 unsigned NumOperands = MCID->getNumOperands();
930 if (!MCID->isVariadic())
933 for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) {
934 const MachineOperand &MO = getOperand(i);
935 if (!MO.isReg() || !MO.isImplicit())
941 /// isBundled - Return true if this instruction part of a bundle. This is true
942 /// if either itself or its following instruction is marked "InsideBundle".
943 bool MachineInstr::isBundled() const {
944 if (isInsideBundle())
946 MachineBasicBlock::const_instr_iterator nextMI = this;
948 return nextMI != Parent->instr_end() && nextMI->isInsideBundle();
951 bool MachineInstr::isStackAligningInlineAsm() const {
953 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
954 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
960 int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx,
961 unsigned *GroupNo) const {
962 assert(isInlineAsm() && "Expected an inline asm instruction");
963 assert(OpIdx < getNumOperands() && "OpIdx out of range");
965 // Ignore queries about the initial operands.
966 if (OpIdx < InlineAsm::MIOp_FirstOperand)
971 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
973 const MachineOperand &FlagMO = getOperand(i);
974 // If we reach the implicit register operands, stop looking.
977 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
978 if (i + NumOps > OpIdx) {
988 const TargetRegisterClass*
989 MachineInstr::getRegClassConstraint(unsigned OpIdx,
990 const TargetInstrInfo *TII,
991 const TargetRegisterInfo *TRI) const {
992 assert(getParent() && "Can't have an MBB reference here!");
993 assert(getParent()->getParent() && "Can't have an MF reference here!");
994 const MachineFunction &MF = *getParent()->getParent();
996 // Most opcodes have fixed constraints in their MCInstrDesc.
998 return TII->getRegClass(getDesc(), OpIdx, TRI, MF);
1000 if (!getOperand(OpIdx).isReg())
1003 // For tied uses on inline asm, get the constraint from the def.
1005 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
1008 // Inline asm stores register class constraints in the flag word.
1009 int FlagIdx = findInlineAsmFlagIdx(OpIdx);
1013 unsigned Flag = getOperand(FlagIdx).getImm();
1015 if (InlineAsm::hasRegClassConstraint(Flag, RCID))
1016 return TRI->getRegClass(RCID);
1018 // Assume that all registers in a memory operand are pointers.
1019 if (InlineAsm::getKind(Flag) == InlineAsm::Kind_Mem)
1020 return TRI->getPointerRegClass(MF);
1025 /// getBundleSize - Return the number of instructions inside the MI bundle.
1026 unsigned MachineInstr::getBundleSize() const {
1027 assert(isBundle() && "Expecting a bundle");
1029 MachineBasicBlock::const_instr_iterator I = *this;
1031 while ((++I)->isInsideBundle()) {
1034 assert(Size > 1 && "Malformed bundle");
1039 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
1040 /// the specific register or -1 if it is not found. It further tightens
1041 /// the search criteria to a use that kills the register if isKill is true.
1042 int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
1043 const TargetRegisterInfo *TRI) const {
1044 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1045 const MachineOperand &MO = getOperand(i);
1046 if (!MO.isReg() || !MO.isUse())
1048 unsigned MOReg = MO.getReg();
1053 TargetRegisterInfo::isPhysicalRegister(MOReg) &&
1054 TargetRegisterInfo::isPhysicalRegister(Reg) &&
1055 TRI->isSubRegister(MOReg, Reg)))
1056 if (!isKill || MO.isKill())
1062 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
1063 /// indicating if this instruction reads or writes Reg. This also considers
1064 /// partial defines.
1065 std::pair<bool,bool>
1066 MachineInstr::readsWritesVirtualRegister(unsigned Reg,
1067 SmallVectorImpl<unsigned> *Ops) const {
1068 bool PartDef = false; // Partial redefine.
1069 bool FullDef = false; // Full define.
1072 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1073 const MachineOperand &MO = getOperand(i);
1074 if (!MO.isReg() || MO.getReg() != Reg)
1079 Use |= !MO.isUndef();
1080 else if (MO.getSubReg() && !MO.isUndef())
1081 // A partial <def,undef> doesn't count as reading the register.
1086 // A partial redefine uses Reg unless there is also a full define.
1087 return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
1090 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
1091 /// the specified register or -1 if it is not found. If isDead is true, defs
1092 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
1093 /// also checks if there is a def of a super-register.
1095 MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap,
1096 const TargetRegisterInfo *TRI) const {
1097 bool isPhys = TargetRegisterInfo::isPhysicalRegister(Reg);
1098 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1099 const MachineOperand &MO = getOperand(i);
1100 // Accept regmask operands when Overlap is set.
1101 // Ignore them when looking for a specific def operand (Overlap == false).
1102 if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg))
1104 if (!MO.isReg() || !MO.isDef())
1106 unsigned MOReg = MO.getReg();
1107 bool Found = (MOReg == Reg);
1108 if (!Found && TRI && isPhys &&
1109 TargetRegisterInfo::isPhysicalRegister(MOReg)) {
1111 Found = TRI->regsOverlap(MOReg, Reg);
1113 Found = TRI->isSubRegister(MOReg, Reg);
1115 if (Found && (!isDead || MO.isDead()))
1121 /// findFirstPredOperandIdx() - Find the index of the first operand in the
1122 /// operand list that is used to represent the predicate. It returns -1 if
1124 int MachineInstr::findFirstPredOperandIdx() const {
1125 // Don't call MCID.findFirstPredOperandIdx() because this variant
1126 // is sometimes called on an instruction that's not yet complete, and
1127 // so the number of operands is less than the MCID indicates. In
1128 // particular, the PTX target does this.
1129 const MCInstrDesc &MCID = getDesc();
1130 if (MCID.isPredicable()) {
1131 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
1132 if (MCID.OpInfo[i].isPredicate())
1139 /// Mark operands at DefIdx and UseIdx as tied to each other.
1140 void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) {
1141 assert(DefIdx < UseIdx && "Tied defs must precede the use");
1142 MachineOperand &DefMO = getOperand(DefIdx);
1143 MachineOperand &UseMO = getOperand(UseIdx);
1144 assert(DefMO.isDef() && "DefIdx must be a def operand");
1145 assert(UseMO.isUse() && "UseIdx must be a use operand");
1146 assert(!DefMO.isTied() && "Def is already tied to another use");
1147 assert(!UseMO.isTied() && "Use is already tied to another def");
1149 DefMO.IsTied = true;
1150 UseMO.IsTied = true;
1153 /// Given the index of a tied register operand, find the operand it is tied to.
1154 /// Defs are tied to uses and vice versa. Returns the index of the tied operand
1155 /// which must exist.
1156 unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const {
1157 // It doesn't usually happen, but an instruction can have multiple pairs of
1159 SmallVector<unsigned, 4> Uses, Defs;
1160 unsigned PairNo = ~0u;
1161 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1162 const MachineOperand &MO = getOperand(i);
1163 if (!MO.isReg() || !MO.isTied())
1167 PairNo = Uses.size();
1171 PairNo = Defs.size();
1175 // For each tied use there must be a tied def and vice versa.
1176 assert(Uses.size() == Defs.size() && "Tied uses and defs don't match");
1177 assert(PairNo < Uses.size() && "OpIdx must be a tied register operand");
1179 // Find the matching operand.
1180 return (getOperand(OpIdx).isDef() ? Uses : Defs)[PairNo];
1183 /// isRegTiedToUseOperand - Given the index of a register def operand,
1184 /// check if the register def is tied to a source operand, due to either
1185 /// two-address elimination or inline assembly constraints. Returns the
1186 /// first tied use operand index by reference is UseOpIdx is not null.
1188 isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx) const {
1189 if (isInlineAsm()) {
1190 assert(DefOpIdx > InlineAsm::MIOp_FirstOperand);
1191 const MachineOperand &MO = getOperand(DefOpIdx);
1192 if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
1194 // Determine the actual operand index that corresponds to this index.
1196 int FlagIdx = findInlineAsmFlagIdx(DefOpIdx, &DefNo);
1200 // Which part of the group is DefOpIdx?
1201 unsigned DefPart = DefOpIdx - (FlagIdx + 1);
1203 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands();
1205 const MachineOperand &FMO = getOperand(i);
1208 if (i+1 >= e || !getOperand(i+1).isReg() || !getOperand(i+1).isUse())
1211 if (InlineAsm::isUseOperandTiedToDef(FMO.getImm(), Idx) &&
1214 *UseOpIdx = (unsigned)i + 1 + DefPart;
1221 assert(getOperand(DefOpIdx).isDef() && "DefOpIdx is not a def!");
1222 const MCInstrDesc &MCID = getDesc();
1223 for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i) {
1224 const MachineOperand &MO = getOperand(i);
1225 if (MO.isReg() && MO.isUse() &&
1226 MCID.getOperandConstraint(i, MCOI::TIED_TO) == (int)DefOpIdx) {
1228 *UseOpIdx = (unsigned)i;
1235 /// isRegTiedToDefOperand - Return true if the operand of the specified index
1236 /// is a register use and it is tied to an def operand. It also returns the def
1237 /// operand index by reference.
1239 isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx) const {
1240 if (isInlineAsm()) {
1241 const MachineOperand &MO = getOperand(UseOpIdx);
1242 if (!MO.isReg() || !MO.isUse() || MO.getReg() == 0)
1245 // Find the flag operand corresponding to UseOpIdx
1246 int FlagIdx = findInlineAsmFlagIdx(UseOpIdx);
1250 const MachineOperand &UFMO = getOperand(FlagIdx);
1252 if (InlineAsm::isUseOperandTiedToDef(UFMO.getImm(), DefNo)) {
1256 unsigned DefIdx = InlineAsm::MIOp_FirstOperand;
1257 // Remember to adjust the index. First operand is asm string, second is
1258 // the HasSideEffects and AlignStack bits, then there is a flag for each.
1260 const MachineOperand &FMO = getOperand(DefIdx);
1261 assert(FMO.isImm());
1262 // Skip over this def.
1263 DefIdx += InlineAsm::getNumOperandRegisters(FMO.getImm()) + 1;
1266 *DefOpIdx = DefIdx + UseOpIdx - FlagIdx;
1272 const MCInstrDesc &MCID = getDesc();
1273 if (UseOpIdx >= MCID.getNumOperands())
1275 const MachineOperand &MO = getOperand(UseOpIdx);
1276 if (!MO.isReg() || !MO.isUse())
1278 int DefIdx = MCID.getOperandConstraint(UseOpIdx, MCOI::TIED_TO);
1282 *DefOpIdx = (unsigned)DefIdx;
1286 /// clearKillInfo - Clears kill flags on all operands.
1288 void MachineInstr::clearKillInfo() {
1289 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1290 MachineOperand &MO = getOperand(i);
1291 if (MO.isReg() && MO.isUse())
1292 MO.setIsKill(false);
1296 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
1298 void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
1299 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1300 const MachineOperand &MO = MI->getOperand(i);
1301 if (!MO.isReg() || (!MO.isKill() && !MO.isDead()))
1303 for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
1304 MachineOperand &MOp = getOperand(j);
1305 if (!MOp.isIdenticalTo(MO))
1316 /// copyPredicates - Copies predicate operand(s) from MI.
1317 void MachineInstr::copyPredicates(const MachineInstr *MI) {
1318 assert(!isBundle() && "MachineInstr::copyPredicates() can't handle bundles");
1320 const MCInstrDesc &MCID = MI->getDesc();
1321 if (!MCID.isPredicable())
1323 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1324 if (MCID.OpInfo[i].isPredicate()) {
1325 // Predicated operands must be last operands.
1326 addOperand(MI->getOperand(i));
1331 void MachineInstr::substituteRegister(unsigned FromReg,
1334 const TargetRegisterInfo &RegInfo) {
1335 if (TargetRegisterInfo::isPhysicalRegister(ToReg)) {
1337 ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1338 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1339 MachineOperand &MO = getOperand(i);
1340 if (!MO.isReg() || MO.getReg() != FromReg)
1342 MO.substPhysReg(ToReg, RegInfo);
1345 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1346 MachineOperand &MO = getOperand(i);
1347 if (!MO.isReg() || MO.getReg() != FromReg)
1349 MO.substVirtReg(ToReg, SubIdx, RegInfo);
1354 /// isSafeToMove - Return true if it is safe to move this instruction. If
1355 /// SawStore is set to true, it means that there is a store (or call) between
1356 /// the instruction's location and its intended destination.
1357 bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII,
1359 bool &SawStore) const {
1360 // Ignore stuff that we obviously can't move.
1362 // Treat volatile loads as stores. This is not strictly necessary for
1363 // volatiles, but it is required for atomic loads. It is now allowed to move
1364 // a load across an atomic load with Ordering > Monotonic.
1365 if (mayStore() || isCall() ||
1366 (mayLoad() && hasOrderedMemoryRef())) {
1371 if (isLabel() || isDebugValue() ||
1372 isTerminator() || hasUnmodeledSideEffects())
1375 // See if this instruction does a load. If so, we have to guarantee that the
1376 // loaded value doesn't change between the load and the its intended
1377 // destination. The check for isInvariantLoad gives the targe the chance to
1378 // classify the load as always returning a constant, e.g. a constant pool
1380 if (mayLoad() && !isInvariantLoad(AA))
1381 // Otherwise, this is a real load. If there is a store between the load and
1382 // end of block, we can't move it.
1388 /// isSafeToReMat - Return true if it's safe to rematerialize the specified
1389 /// instruction which defined the specified register instead of copying it.
1390 bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII,
1392 unsigned DstReg) const {
1393 bool SawStore = false;
1394 if (!TII->isTriviallyReMaterializable(this, AA) ||
1395 !isSafeToMove(TII, AA, SawStore))
1397 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1398 const MachineOperand &MO = getOperand(i);
1401 // FIXME: For now, do not remat any instruction with register operands.
1402 // Later on, we can loosen the restriction is the register operands have
1403 // not been modified between the def and use. Note, this is different from
1404 // MachineSink because the code is no longer in two-address form (at least
1408 else if (!MO.isDead() && MO.getReg() != DstReg)
1414 /// hasOrderedMemoryRef - Return true if this instruction may have an ordered
1415 /// or volatile memory reference, or if the information describing the memory
1416 /// reference is not available. Return false if it is known to have no ordered
1417 /// memory references.
1418 bool MachineInstr::hasOrderedMemoryRef() const {
1419 // An instruction known never to access memory won't have a volatile access.
1423 !hasUnmodeledSideEffects())
1426 // Otherwise, if the instruction has no memory reference information,
1427 // conservatively assume it wasn't preserved.
1428 if (memoperands_empty())
1431 // Check the memory reference information for ordered references.
1432 for (mmo_iterator I = memoperands_begin(), E = memoperands_end(); I != E; ++I)
1433 if (!(*I)->isUnordered())
1439 /// isInvariantLoad - Return true if this instruction is loading from a
1440 /// location whose value is invariant across the function. For example,
1441 /// loading a value from the constant pool or from the argument area
1442 /// of a function if it does not change. This should only return true of
1443 /// *all* loads the instruction does are invariant (if it does multiple loads).
1444 bool MachineInstr::isInvariantLoad(AliasAnalysis *AA) const {
1445 // If the instruction doesn't load at all, it isn't an invariant load.
1449 // If the instruction has lost its memoperands, conservatively assume that
1450 // it may not be an invariant load.
1451 if (memoperands_empty())
1454 const MachineFrameInfo *MFI = getParent()->getParent()->getFrameInfo();
1456 for (mmo_iterator I = memoperands_begin(),
1457 E = memoperands_end(); I != E; ++I) {
1458 if ((*I)->isVolatile()) return false;
1459 if ((*I)->isStore()) return false;
1460 if ((*I)->isInvariant()) return true;
1462 if (const Value *V = (*I)->getValue()) {
1463 // A load from a constant PseudoSourceValue is invariant.
1464 if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V))
1465 if (PSV->isConstant(MFI))
1467 // If we have an AliasAnalysis, ask it whether the memory is constant.
1468 if (AA && AA->pointsToConstantMemory(
1469 AliasAnalysis::Location(V, (*I)->getSize(),
1470 (*I)->getTBAAInfo())))
1474 // Otherwise assume conservatively.
1478 // Everything checks out.
1482 /// isConstantValuePHI - If the specified instruction is a PHI that always
1483 /// merges together the same virtual register, return the register, otherwise
1485 unsigned MachineInstr::isConstantValuePHI() const {
1488 assert(getNumOperands() >= 3 &&
1489 "It's illegal to have a PHI without source operands");
1491 unsigned Reg = getOperand(1).getReg();
1492 for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1493 if (getOperand(i).getReg() != Reg)
1498 bool MachineInstr::hasUnmodeledSideEffects() const {
1499 if (hasProperty(MCID::UnmodeledSideEffects))
1501 if (isInlineAsm()) {
1502 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1503 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1510 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
1512 bool MachineInstr::allDefsAreDead() const {
1513 for (unsigned i = 0, e = getNumOperands(); i < e; ++i) {
1514 const MachineOperand &MO = getOperand(i);
1515 if (!MO.isReg() || MO.isUse())
1523 /// copyImplicitOps - Copy implicit register operands from specified
1524 /// instruction to this instruction.
1525 void MachineInstr::copyImplicitOps(const MachineInstr *MI) {
1526 for (unsigned i = MI->getDesc().getNumOperands(), e = MI->getNumOperands();
1528 const MachineOperand &MO = MI->getOperand(i);
1529 if (MO.isReg() && MO.isImplicit())
1534 void MachineInstr::dump() const {
1535 dbgs() << " " << *this;
1538 static void printDebugLoc(DebugLoc DL, const MachineFunction *MF,
1539 raw_ostream &CommentOS) {
1540 const LLVMContext &Ctx = MF->getFunction()->getContext();
1541 if (!DL.isUnknown()) { // Print source line info.
1542 DIScope Scope(DL.getScope(Ctx));
1543 // Omit the directory, because it's likely to be long and uninteresting.
1545 CommentOS << Scope.getFilename();
1547 CommentOS << "<unknown>";
1548 CommentOS << ':' << DL.getLine();
1549 if (DL.getCol() != 0)
1550 CommentOS << ':' << DL.getCol();
1551 DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(DL.getInlinedAt(Ctx));
1552 if (!InlinedAtDL.isUnknown()) {
1553 CommentOS << " @[ ";
1554 printDebugLoc(InlinedAtDL, MF, CommentOS);
1560 void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const {
1561 // We can be a bit tidier if we know the TargetMachine and/or MachineFunction.
1562 const MachineFunction *MF = 0;
1563 const MachineRegisterInfo *MRI = 0;
1564 if (const MachineBasicBlock *MBB = getParent()) {
1565 MF = MBB->getParent();
1567 TM = &MF->getTarget();
1569 MRI = &MF->getRegInfo();
1572 // Save a list of virtual registers.
1573 SmallVector<unsigned, 8> VirtRegs;
1575 // Print explicitly defined operands on the left of an assignment syntax.
1576 unsigned StartOp = 0, e = getNumOperands();
1577 for (; StartOp < e && getOperand(StartOp).isReg() &&
1578 getOperand(StartOp).isDef() &&
1579 !getOperand(StartOp).isImplicit();
1581 if (StartOp != 0) OS << ", ";
1582 getOperand(StartOp).print(OS, TM);
1583 unsigned Reg = getOperand(StartOp).getReg();
1584 if (TargetRegisterInfo::isVirtualRegister(Reg))
1585 VirtRegs.push_back(Reg);
1591 // Print the opcode name.
1592 if (TM && TM->getInstrInfo())
1593 OS << TM->getInstrInfo()->getName(getOpcode());
1597 // Print the rest of the operands.
1598 bool OmittedAnyCallClobbers = false;
1599 bool FirstOp = true;
1600 unsigned AsmDescOp = ~0u;
1601 unsigned AsmOpCount = 0;
1603 if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) {
1604 // Print asm string.
1606 getOperand(InlineAsm::MIOp_AsmString).print(OS, TM);
1608 // Print HasSideEffects, IsAlignStack
1609 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1610 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1611 OS << " [sideeffect]";
1612 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1613 OS << " [alignstack]";
1615 StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
1620 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1621 const MachineOperand &MO = getOperand(i);
1623 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1624 VirtRegs.push_back(MO.getReg());
1626 // Omit call-clobbered registers which aren't used anywhere. This makes
1627 // call instructions much less noisy on targets where calls clobber lots
1628 // of registers. Don't rely on MO.isDead() because we may be called before
1629 // LiveVariables is run, or we may be looking at a non-allocatable reg.
1630 if (MF && isCall() &&
1631 MO.isReg() && MO.isImplicit() && MO.isDef()) {
1632 unsigned Reg = MO.getReg();
1633 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
1634 const MachineRegisterInfo &MRI = MF->getRegInfo();
1635 if (MRI.use_empty(Reg) && !MRI.isLiveOut(Reg)) {
1636 bool HasAliasLive = false;
1637 for (MCRegAliasIterator AI(Reg, TM->getRegisterInfo(), true);
1638 AI.isValid(); ++AI) {
1639 unsigned AliasReg = *AI;
1640 if (!MRI.use_empty(AliasReg) || MRI.isLiveOut(AliasReg)) {
1641 HasAliasLive = true;
1645 if (!HasAliasLive) {
1646 OmittedAnyCallClobbers = true;
1653 if (FirstOp) FirstOp = false; else OS << ",";
1655 if (i < getDesc().NumOperands) {
1656 const MCOperandInfo &MCOI = getDesc().OpInfo[i];
1657 if (MCOI.isPredicate())
1659 if (MCOI.isOptionalDef())
1662 if (isDebugValue() && MO.isMetadata()) {
1663 // Pretty print DBG_VALUE instructions.
1664 const MDNode *MD = MO.getMetadata();
1665 if (const MDString *MDS = dyn_cast<MDString>(MD->getOperand(2)))
1666 OS << "!\"" << MDS->getString() << '\"';
1669 } else if (TM && (isInsertSubreg() || isRegSequence()) && MO.isImm()) {
1670 OS << TM->getRegisterInfo()->getSubRegIndexName(MO.getImm());
1671 } else if (i == AsmDescOp && MO.isImm()) {
1672 // Pretty print the inline asm operand descriptor.
1673 OS << '$' << AsmOpCount++;
1674 unsigned Flag = MO.getImm();
1675 switch (InlineAsm::getKind(Flag)) {
1676 case InlineAsm::Kind_RegUse: OS << ":[reguse"; break;
1677 case InlineAsm::Kind_RegDef: OS << ":[regdef"; break;
1678 case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec"; break;
1679 case InlineAsm::Kind_Clobber: OS << ":[clobber"; break;
1680 case InlineAsm::Kind_Imm: OS << ":[imm"; break;
1681 case InlineAsm::Kind_Mem: OS << ":[mem"; break;
1682 default: OS << ":[??" << InlineAsm::getKind(Flag); break;
1686 if (InlineAsm::hasRegClassConstraint(Flag, RCID)) {
1688 OS << ':' << TM->getRegisterInfo()->getRegClass(RCID)->getName();
1690 OS << ":RC" << RCID;
1693 unsigned TiedTo = 0;
1694 if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo))
1695 OS << " tiedto:$" << TiedTo;
1699 // Compute the index of the next operand descriptor.
1700 AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
1705 // Briefly indicate whether any call clobbers were omitted.
1706 if (OmittedAnyCallClobbers) {
1707 if (!FirstOp) OS << ",";
1711 bool HaveSemi = false;
1713 if (!HaveSemi) OS << ";"; HaveSemi = true;
1716 if (Flags & FrameSetup)
1720 if (!memoperands_empty()) {
1721 if (!HaveSemi) OS << ";"; HaveSemi = true;
1724 for (mmo_iterator i = memoperands_begin(), e = memoperands_end();
1727 if (llvm::next(i) != e)
1732 // Print the regclass of any virtual registers encountered.
1733 if (MRI && !VirtRegs.empty()) {
1734 if (!HaveSemi) OS << ";"; HaveSemi = true;
1735 for (unsigned i = 0; i != VirtRegs.size(); ++i) {
1736 const TargetRegisterClass *RC = MRI->getRegClass(VirtRegs[i]);
1737 OS << " " << RC->getName() << ':' << PrintReg(VirtRegs[i]);
1738 for (unsigned j = i+1; j != VirtRegs.size();) {
1739 if (MRI->getRegClass(VirtRegs[j]) != RC) {
1743 if (VirtRegs[i] != VirtRegs[j])
1744 OS << "," << PrintReg(VirtRegs[j]);
1745 VirtRegs.erase(VirtRegs.begin()+j);
1750 // Print debug location information.
1751 if (isDebugValue() && getOperand(e - 1).isMetadata()) {
1752 if (!HaveSemi) OS << ";"; HaveSemi = true;
1753 DIVariable DV(getOperand(e - 1).getMetadata());
1754 OS << " line no:" << DV.getLineNumber();
1755 if (MDNode *InlinedAt = DV.getInlinedAt()) {
1756 DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(InlinedAt);
1757 if (!InlinedAtDL.isUnknown()) {
1758 OS << " inlined @[ ";
1759 printDebugLoc(InlinedAtDL, MF, OS);
1763 } else if (!debugLoc.isUnknown() && MF) {
1764 if (!HaveSemi) OS << ";"; HaveSemi = true;
1766 printDebugLoc(debugLoc, MF, OS);
1772 bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
1773 const TargetRegisterInfo *RegInfo,
1774 bool AddIfNotFound) {
1775 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1776 bool hasAliases = isPhysReg &&
1777 MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
1779 SmallVector<unsigned,4> DeadOps;
1780 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1781 MachineOperand &MO = getOperand(i);
1782 if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1784 unsigned Reg = MO.getReg();
1788 if (Reg == IncomingReg) {
1791 // The register is already marked kill.
1793 if (isPhysReg && isRegTiedToDefOperand(i))
1794 // Two-address uses of physregs must not be marked kill.
1799 } else if (hasAliases && MO.isKill() &&
1800 TargetRegisterInfo::isPhysicalRegister(Reg)) {
1801 // A super-register kill already exists.
1802 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1804 if (RegInfo->isSubRegister(IncomingReg, Reg))
1805 DeadOps.push_back(i);
1809 // Trim unneeded kill operands.
1810 while (!DeadOps.empty()) {
1811 unsigned OpIdx = DeadOps.back();
1812 if (getOperand(OpIdx).isImplicit())
1813 RemoveOperand(OpIdx);
1815 getOperand(OpIdx).setIsKill(false);
1819 // If not found, this means an alias of one of the operands is killed. Add a
1820 // new implicit operand if required.
1821 if (!Found && AddIfNotFound) {
1822 addOperand(MachineOperand::CreateReg(IncomingReg,
1831 void MachineInstr::clearRegisterKills(unsigned Reg,
1832 const TargetRegisterInfo *RegInfo) {
1833 if (!TargetRegisterInfo::isPhysicalRegister(Reg))
1835 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1836 MachineOperand &MO = getOperand(i);
1837 if (!MO.isReg() || !MO.isUse() || !MO.isKill())
1839 unsigned OpReg = MO.getReg();
1840 if (OpReg == Reg || (RegInfo && RegInfo->isSuperRegister(Reg, OpReg)))
1841 MO.setIsKill(false);
1845 bool MachineInstr::addRegisterDead(unsigned IncomingReg,
1846 const TargetRegisterInfo *RegInfo,
1847 bool AddIfNotFound) {
1848 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1849 bool hasAliases = isPhysReg &&
1850 MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
1852 SmallVector<unsigned,4> DeadOps;
1853 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1854 MachineOperand &MO = getOperand(i);
1855 if (!MO.isReg() || !MO.isDef())
1857 unsigned Reg = MO.getReg();
1861 if (Reg == IncomingReg) {
1864 } else if (hasAliases && MO.isDead() &&
1865 TargetRegisterInfo::isPhysicalRegister(Reg)) {
1866 // There exists a super-register that's marked dead.
1867 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1869 if (RegInfo->isSubRegister(IncomingReg, Reg))
1870 DeadOps.push_back(i);
1874 // Trim unneeded dead operands.
1875 while (!DeadOps.empty()) {
1876 unsigned OpIdx = DeadOps.back();
1877 if (getOperand(OpIdx).isImplicit())
1878 RemoveOperand(OpIdx);
1880 getOperand(OpIdx).setIsDead(false);
1884 // If not found, this means an alias of one of the operands is dead. Add a
1885 // new implicit operand if required.
1886 if (Found || !AddIfNotFound)
1889 addOperand(MachineOperand::CreateReg(IncomingReg,
1897 void MachineInstr::addRegisterDefined(unsigned IncomingReg,
1898 const TargetRegisterInfo *RegInfo) {
1899 if (TargetRegisterInfo::isPhysicalRegister(IncomingReg)) {
1900 MachineOperand *MO = findRegisterDefOperand(IncomingReg, false, RegInfo);
1904 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1905 const MachineOperand &MO = getOperand(i);
1906 if (MO.isReg() && MO.getReg() == IncomingReg && MO.isDef() &&
1907 MO.getSubReg() == 0)
1911 addOperand(MachineOperand::CreateReg(IncomingReg,
1916 void MachineInstr::setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs,
1917 const TargetRegisterInfo &TRI) {
1918 bool HasRegMask = false;
1919 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1920 MachineOperand &MO = getOperand(i);
1921 if (MO.isRegMask()) {
1925 if (!MO.isReg() || !MO.isDef()) continue;
1926 unsigned Reg = MO.getReg();
1927 if (!TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
1929 for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end();
1931 if (TRI.regsOverlap(*I, Reg)) {
1935 // If there are no uses, including partial uses, the def is dead.
1936 if (Dead) MO.setIsDead();
1939 // This is a call with a register mask operand.
1940 // Mask clobbers are always dead, so add defs for the non-dead defines.
1942 for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end();
1944 addRegisterDefined(*I, &TRI);
1948 MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
1949 // Build up a buffer of hash code components.
1950 SmallVector<size_t, 8> HashComponents;
1951 HashComponents.reserve(MI->getNumOperands() + 1);
1952 HashComponents.push_back(MI->getOpcode());
1953 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1954 const MachineOperand &MO = MI->getOperand(i);
1955 if (MO.isReg() && MO.isDef() &&
1956 TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1957 continue; // Skip virtual register defs.
1959 HashComponents.push_back(hash_value(MO));
1961 return hash_combine_range(HashComponents.begin(), HashComponents.end());
1964 void MachineInstr::emitError(StringRef Msg) const {
1965 // Find the source location cookie.
1966 unsigned LocCookie = 0;
1967 const MDNode *LocMD = 0;
1968 for (unsigned i = getNumOperands(); i != 0; --i) {
1969 if (getOperand(i-1).isMetadata() &&
1970 (LocMD = getOperand(i-1).getMetadata()) &&
1971 LocMD->getNumOperands() != 0) {
1972 if (const ConstantInt *CI = dyn_cast<ConstantInt>(LocMD->getOperand(0))) {
1973 LocCookie = CI->getZExtValue();
1979 if (const MachineBasicBlock *MBB = getParent())
1980 if (const MachineFunction *MF = MBB->getParent())
1981 return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
1982 report_fatal_error(Msg);