1 //===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Methods common to all machine instructions.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "llvm/ADT/FoldingSet.h"
16 #include "llvm/ADT/Hashing.h"
17 #include "llvm/Analysis/AliasAnalysis.h"
18 #include "llvm/CodeGen/MachineConstantPool.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineMemOperand.h"
21 #include "llvm/CodeGen/MachineModuleInfo.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/PseudoSourceValue.h"
24 #include "llvm/IR/Constants.h"
25 #include "llvm/IR/DebugInfo.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/IR/InlineAsm.h"
28 #include "llvm/IR/LLVMContext.h"
29 #include "llvm/IR/Metadata.h"
30 #include "llvm/IR/Module.h"
31 #include "llvm/IR/ModuleSlotTracker.h"
32 #include "llvm/IR/Type.h"
33 #include "llvm/IR/Value.h"
34 #include "llvm/MC/MCInstrDesc.h"
35 #include "llvm/MC/MCSymbol.h"
36 #include "llvm/Support/CommandLine.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/MathExtras.h"
40 #include "llvm/Support/raw_ostream.h"
41 #include "llvm/Target/TargetInstrInfo.h"
42 #include "llvm/Target/TargetMachine.h"
43 #include "llvm/Target/TargetRegisterInfo.h"
44 #include "llvm/Target/TargetSubtargetInfo.h"
47 static cl::opt<bool> PrintWholeRegMask(
48 "print-whole-regmask",
49 cl::desc("Print the full contents of regmask operands in IR dumps"),
50 cl::init(true), cl::Hidden);
52 //===----------------------------------------------------------------------===//
53 // MachineOperand Implementation
54 //===----------------------------------------------------------------------===//
56 void MachineOperand::setReg(unsigned Reg) {
57 if (getReg() == Reg) return; // No change.
59 // Otherwise, we have to change the register. If this operand is embedded
60 // into a machine function, we need to update the old and new register's
62 if (MachineInstr *MI = getParent())
63 if (MachineBasicBlock *MBB = MI->getParent())
64 if (MachineFunction *MF = MBB->getParent()) {
65 MachineRegisterInfo &MRI = MF->getRegInfo();
66 MRI.removeRegOperandFromUseList(this);
67 SmallContents.RegNo = Reg;
68 MRI.addRegOperandToUseList(this);
72 // Otherwise, just change the register, no problem. :)
73 SmallContents.RegNo = Reg;
76 void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx,
77 const TargetRegisterInfo &TRI) {
78 assert(TargetRegisterInfo::isVirtualRegister(Reg));
79 if (SubIdx && getSubReg())
80 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
86 void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) {
87 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
89 Reg = TRI.getSubReg(Reg, getSubReg());
90 // Note that getSubReg() may return 0 if the sub-register doesn't exist.
91 // That won't happen in legal code.
97 /// Change a def to a use, or a use to a def.
98 void MachineOperand::setIsDef(bool Val) {
99 assert(isReg() && "Wrong MachineOperand accessor");
100 assert((!Val || !isDebug()) && "Marking a debug operation as def");
103 // MRI may keep uses and defs in different list positions.
104 if (MachineInstr *MI = getParent())
105 if (MachineBasicBlock *MBB = MI->getParent())
106 if (MachineFunction *MF = MBB->getParent()) {
107 MachineRegisterInfo &MRI = MF->getRegInfo();
108 MRI.removeRegOperandFromUseList(this);
110 MRI.addRegOperandToUseList(this);
116 // If this operand is currently a register operand, and if this is in a
117 // function, deregister the operand from the register's use/def list.
118 void MachineOperand::removeRegFromUses() {
119 if (!isReg() || !isOnRegUseList())
122 if (MachineInstr *MI = getParent()) {
123 if (MachineBasicBlock *MBB = MI->getParent()) {
124 if (MachineFunction *MF = MBB->getParent())
125 MF->getRegInfo().removeRegOperandFromUseList(this);
130 /// ChangeToImmediate - Replace this operand with a new immediate operand of
131 /// the specified value. If an operand is known to be an immediate already,
132 /// the setImm method should be used.
133 void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
134 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
138 OpKind = MO_Immediate;
139 Contents.ImmVal = ImmVal;
142 void MachineOperand::ChangeToFPImmediate(const ConstantFP *FPImm) {
143 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
147 OpKind = MO_FPImmediate;
148 Contents.CFP = FPImm;
151 void MachineOperand::ChangeToES(const char *SymName, unsigned char TargetFlags) {
152 assert((!isReg() || !isTied()) &&
153 "Cannot change a tied operand into an external symbol");
157 OpKind = MO_ExternalSymbol;
158 Contents.OffsetedInfo.Val.SymbolName = SymName;
159 setOffset(0); // Offset is always 0.
160 setTargetFlags(TargetFlags);
163 void MachineOperand::ChangeToMCSymbol(MCSymbol *Sym) {
164 assert((!isReg() || !isTied()) &&
165 "Cannot change a tied operand into an MCSymbol");
169 OpKind = MO_MCSymbol;
173 /// ChangeToRegister - Replace this operand with a new register operand of
174 /// the specified value. If an operand is known to be an register already,
175 /// the setReg method should be used.
176 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
177 bool isKill, bool isDead, bool isUndef,
179 MachineRegisterInfo *RegInfo = nullptr;
180 if (MachineInstr *MI = getParent())
181 if (MachineBasicBlock *MBB = MI->getParent())
182 if (MachineFunction *MF = MBB->getParent())
183 RegInfo = &MF->getRegInfo();
184 // If this operand is already a register operand, remove it from the
185 // register's use/def lists.
186 bool WasReg = isReg();
187 if (RegInfo && WasReg)
188 RegInfo->removeRegOperandFromUseList(this);
190 // Change this to a register and set the reg#.
191 OpKind = MO_Register;
192 SmallContents.RegNo = Reg;
193 SubReg_TargetFlags = 0;
199 IsInternalRead = false;
200 IsEarlyClobber = false;
202 // Ensure isOnRegUseList() returns false.
203 Contents.Reg.Prev = nullptr;
204 // Preserve the tie when the operand was already a register.
208 // If this operand is embedded in a function, add the operand to the
209 // register's use/def list.
211 RegInfo->addRegOperandToUseList(this);
214 /// isIdenticalTo - Return true if this operand is identical to the specified
215 /// operand. Note that this should stay in sync with the hash_value overload
217 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
218 if (getType() != Other.getType() ||
219 getTargetFlags() != Other.getTargetFlags())
223 case MachineOperand::MO_Register:
224 return getReg() == Other.getReg() && isDef() == Other.isDef() &&
225 getSubReg() == Other.getSubReg();
226 case MachineOperand::MO_Immediate:
227 return getImm() == Other.getImm();
228 case MachineOperand::MO_CImmediate:
229 return getCImm() == Other.getCImm();
230 case MachineOperand::MO_FPImmediate:
231 return getFPImm() == Other.getFPImm();
232 case MachineOperand::MO_MachineBasicBlock:
233 return getMBB() == Other.getMBB();
234 case MachineOperand::MO_FrameIndex:
235 return getIndex() == Other.getIndex();
236 case MachineOperand::MO_ConstantPoolIndex:
237 case MachineOperand::MO_TargetIndex:
238 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
239 case MachineOperand::MO_JumpTableIndex:
240 return getIndex() == Other.getIndex();
241 case MachineOperand::MO_GlobalAddress:
242 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
243 case MachineOperand::MO_ExternalSymbol:
244 return !strcmp(getSymbolName(), Other.getSymbolName()) &&
245 getOffset() == Other.getOffset();
246 case MachineOperand::MO_BlockAddress:
247 return getBlockAddress() == Other.getBlockAddress() &&
248 getOffset() == Other.getOffset();
249 case MachineOperand::MO_RegisterMask:
250 case MachineOperand::MO_RegisterLiveOut:
251 return getRegMask() == Other.getRegMask();
252 case MachineOperand::MO_MCSymbol:
253 return getMCSymbol() == Other.getMCSymbol();
254 case MachineOperand::MO_CFIIndex:
255 return getCFIIndex() == Other.getCFIIndex();
256 case MachineOperand::MO_Metadata:
257 return getMetadata() == Other.getMetadata();
259 llvm_unreachable("Invalid machine operand type");
262 // Note: this must stay exactly in sync with isIdenticalTo above.
263 hash_code llvm::hash_value(const MachineOperand &MO) {
264 switch (MO.getType()) {
265 case MachineOperand::MO_Register:
266 // Register operands don't have target flags.
267 return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(), MO.isDef());
268 case MachineOperand::MO_Immediate:
269 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
270 case MachineOperand::MO_CImmediate:
271 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
272 case MachineOperand::MO_FPImmediate:
273 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
274 case MachineOperand::MO_MachineBasicBlock:
275 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
276 case MachineOperand::MO_FrameIndex:
277 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
278 case MachineOperand::MO_ConstantPoolIndex:
279 case MachineOperand::MO_TargetIndex:
280 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
282 case MachineOperand::MO_JumpTableIndex:
283 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
284 case MachineOperand::MO_ExternalSymbol:
285 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
287 case MachineOperand::MO_GlobalAddress:
288 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
290 case MachineOperand::MO_BlockAddress:
291 return hash_combine(MO.getType(), MO.getTargetFlags(),
292 MO.getBlockAddress(), MO.getOffset());
293 case MachineOperand::MO_RegisterMask:
294 case MachineOperand::MO_RegisterLiveOut:
295 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask());
296 case MachineOperand::MO_Metadata:
297 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
298 case MachineOperand::MO_MCSymbol:
299 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
300 case MachineOperand::MO_CFIIndex:
301 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCFIIndex());
303 llvm_unreachable("Invalid machine operand type");
306 void MachineOperand::print(raw_ostream &OS,
307 const TargetRegisterInfo *TRI) const {
308 ModuleSlotTracker DummyMST(nullptr);
309 print(OS, DummyMST, TRI);
312 void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
313 const TargetRegisterInfo *TRI) const {
315 case MachineOperand::MO_Register:
316 OS << PrintReg(getReg(), TRI, getSubReg());
318 if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
319 isInternalRead() || isEarlyClobber() || isTied()) {
321 bool NeedComma = false;
323 if (NeedComma) OS << ',';
324 if (isEarlyClobber())
325 OS << "earlyclobber,";
330 // <def,read-undef> only makes sense when getSubReg() is set.
331 // Don't clutter the output otherwise.
332 if (isUndef() && getSubReg())
334 } else if (isImplicit()) {
340 if (NeedComma) OS << ',';
345 if (NeedComma) OS << ',';
349 if (isUndef() && isUse()) {
350 if (NeedComma) OS << ',';
354 if (isInternalRead()) {
355 if (NeedComma) OS << ',';
360 if (NeedComma) OS << ',';
363 OS << unsigned(TiedTo - 1);
368 case MachineOperand::MO_Immediate:
371 case MachineOperand::MO_CImmediate:
372 getCImm()->getValue().print(OS, false);
374 case MachineOperand::MO_FPImmediate:
375 if (getFPImm()->getType()->isFloatTy())
376 OS << getFPImm()->getValueAPF().convertToFloat();
378 OS << getFPImm()->getValueAPF().convertToDouble();
380 case MachineOperand::MO_MachineBasicBlock:
381 OS << "<BB#" << getMBB()->getNumber() << ">";
383 case MachineOperand::MO_FrameIndex:
384 OS << "<fi#" << getIndex() << '>';
386 case MachineOperand::MO_ConstantPoolIndex:
387 OS << "<cp#" << getIndex();
388 if (getOffset()) OS << "+" << getOffset();
391 case MachineOperand::MO_TargetIndex:
392 OS << "<ti#" << getIndex();
393 if (getOffset()) OS << "+" << getOffset();
396 case MachineOperand::MO_JumpTableIndex:
397 OS << "<jt#" << getIndex() << '>';
399 case MachineOperand::MO_GlobalAddress:
401 getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
402 if (getOffset()) OS << "+" << getOffset();
405 case MachineOperand::MO_ExternalSymbol:
406 OS << "<es:" << getSymbolName();
407 if (getOffset()) OS << "+" << getOffset();
410 case MachineOperand::MO_BlockAddress:
412 getBlockAddress()->printAsOperand(OS, /*PrintType=*/false, MST);
413 if (getOffset()) OS << "+" << getOffset();
416 case MachineOperand::MO_RegisterMask: {
417 unsigned NumRegsInMask = 0;
418 unsigned NumRegsEmitted = 0;
420 for (unsigned i = 0; i < TRI->getNumRegs(); ++i) {
421 unsigned MaskWord = i / 32;
422 unsigned MaskBit = i % 32;
423 if (getRegMask()[MaskWord] & (1 << MaskBit)) {
424 if (PrintWholeRegMask || NumRegsEmitted <= 10) {
425 OS << " " << PrintReg(i, TRI);
431 if (NumRegsEmitted != NumRegsInMask)
432 OS << " and " << (NumRegsInMask - NumRegsEmitted) << " more...";
436 case MachineOperand::MO_RegisterLiveOut:
437 OS << "<regliveout>";
439 case MachineOperand::MO_Metadata:
441 getMetadata()->printAsOperand(OS, MST);
444 case MachineOperand::MO_MCSymbol:
445 OS << "<MCSym=" << *getMCSymbol() << '>';
447 case MachineOperand::MO_CFIIndex:
448 OS << "<call frame instruction>";
452 if (unsigned TF = getTargetFlags())
453 OS << "[TF=" << TF << ']';
456 //===----------------------------------------------------------------------===//
457 // MachineMemOperand Implementation
458 //===----------------------------------------------------------------------===//
460 /// getAddrSpace - Return the LLVM IR address space number that this pointer
462 unsigned MachinePointerInfo::getAddrSpace() const {
463 if (V.isNull() || V.is<const PseudoSourceValue*>()) return 0;
464 return cast<PointerType>(V.get<const Value*>()->getType())->getAddressSpace();
467 /// getConstantPool - Return a MachinePointerInfo record that refers to the
469 MachinePointerInfo MachinePointerInfo::getConstantPool(MachineFunction &MF) {
470 return MachinePointerInfo(MF.getPSVManager().getConstantPool());
473 /// getFixedStack - Return a MachinePointerInfo record that refers to the
474 /// the specified FrameIndex.
475 MachinePointerInfo MachinePointerInfo::getFixedStack(MachineFunction &MF,
476 int FI, int64_t Offset) {
477 return MachinePointerInfo(MF.getPSVManager().getFixedStack(FI), Offset);
480 MachinePointerInfo MachinePointerInfo::getJumpTable(MachineFunction &MF) {
481 return MachinePointerInfo(MF.getPSVManager().getJumpTable());
484 MachinePointerInfo MachinePointerInfo::getGOT(MachineFunction &MF) {
485 return MachinePointerInfo(MF.getPSVManager().getGOT());
488 MachinePointerInfo MachinePointerInfo::getStack(MachineFunction &MF,
490 return MachinePointerInfo(MF.getPSVManager().getStack(), Offset);
493 MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, unsigned f,
494 uint64_t s, unsigned int a,
495 const AAMDNodes &AAInfo,
496 const MDNode *Ranges)
497 : PtrInfo(ptrinfo), Size(s),
498 Flags((f & ((1 << MOMaxBits) - 1)) | ((Log2_32(a) + 1) << MOMaxBits)),
499 AAInfo(AAInfo), Ranges(Ranges) {
500 assert((PtrInfo.V.isNull() || PtrInfo.V.is<const PseudoSourceValue*>() ||
501 isa<PointerType>(PtrInfo.V.get<const Value*>()->getType())) &&
502 "invalid pointer value");
503 assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
504 assert((isLoad() || isStore()) && "Not a load/store!");
507 /// Profile - Gather unique data for the object.
509 void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
510 ID.AddInteger(getOffset());
512 ID.AddPointer(getOpaqueValue());
513 ID.AddInteger(Flags);
516 void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
517 // The Value and Offset may differ due to CSE. But the flags and size
518 // should be the same.
519 assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
520 assert(MMO->getSize() == getSize() && "Size mismatch!");
522 if (MMO->getBaseAlignment() >= getBaseAlignment()) {
523 // Update the alignment value.
524 Flags = (Flags & ((1 << MOMaxBits) - 1)) |
525 ((Log2_32(MMO->getBaseAlignment()) + 1) << MOMaxBits);
526 // Also update the base and offset, because the new alignment may
527 // not be applicable with the old ones.
528 PtrInfo = MMO->PtrInfo;
532 /// getAlignment - Return the minimum known alignment in bytes of the
533 /// actual memory reference.
534 uint64_t MachineMemOperand::getAlignment() const {
535 return MinAlign(getBaseAlignment(), getOffset());
538 void MachineMemOperand::print(raw_ostream &OS) const {
539 ModuleSlotTracker DummyMST(nullptr);
542 void MachineMemOperand::print(raw_ostream &OS, ModuleSlotTracker &MST) const {
543 assert((isLoad() || isStore()) &&
544 "SV has to be a load, store or both.");
555 // Print the address information.
557 if (const Value *V = getValue())
558 V->printAsOperand(OS, /*PrintType=*/false, MST);
559 else if (const PseudoSourceValue *PSV = getPseudoValue())
560 PSV->printCustom(OS);
564 unsigned AS = getAddrSpace();
566 OS << "(addrspace=" << AS << ')';
568 // If the alignment of the memory reference itself differs from the alignment
569 // of the base pointer, print the base alignment explicitly, next to the base
571 if (getBaseAlignment() != getAlignment())
572 OS << "(align=" << getBaseAlignment() << ")";
574 if (getOffset() != 0)
575 OS << "+" << getOffset();
578 // Print the alignment of the reference.
579 if (getBaseAlignment() != getAlignment() || getBaseAlignment() != getSize())
580 OS << "(align=" << getAlignment() << ")";
583 if (const MDNode *TBAAInfo = getAAInfo().TBAA) {
585 if (TBAAInfo->getNumOperands() > 0)
586 TBAAInfo->getOperand(0)->printAsOperand(OS, MST);
592 // Print AA scope info.
593 if (const MDNode *ScopeInfo = getAAInfo().Scope) {
594 OS << "(alias.scope=";
595 if (ScopeInfo->getNumOperands() > 0)
596 for (unsigned i = 0, ie = ScopeInfo->getNumOperands(); i != ie; ++i) {
597 ScopeInfo->getOperand(i)->printAsOperand(OS, MST);
606 // Print AA noalias scope info.
607 if (const MDNode *NoAliasInfo = getAAInfo().NoAlias) {
609 if (NoAliasInfo->getNumOperands() > 0)
610 for (unsigned i = 0, ie = NoAliasInfo->getNumOperands(); i != ie; ++i) {
611 NoAliasInfo->getOperand(i)->printAsOperand(OS, MST);
620 // Print nontemporal info.
622 OS << "(nontemporal)";
628 //===----------------------------------------------------------------------===//
629 // MachineInstr Implementation
630 //===----------------------------------------------------------------------===//
632 void MachineInstr::addImplicitDefUseOperands(MachineFunction &MF) {
633 if (MCID->ImplicitDefs)
634 for (const MCPhysReg *ImpDefs = MCID->getImplicitDefs(); *ImpDefs;
636 addOperand(MF, MachineOperand::CreateReg(*ImpDefs, true, true));
637 if (MCID->ImplicitUses)
638 for (const MCPhysReg *ImpUses = MCID->getImplicitUses(); *ImpUses;
640 addOperand(MF, MachineOperand::CreateReg(*ImpUses, false, true));
643 /// MachineInstr ctor - This constructor creates a MachineInstr and adds the
644 /// implicit operands. It reserves space for the number of operands specified by
646 MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &tid,
647 DebugLoc dl, bool NoImp)
648 : MCID(&tid), Parent(nullptr), Operands(nullptr), NumOperands(0), Flags(0),
649 AsmPrinterFlags(0), NumMemRefs(0), MemRefs(nullptr),
650 debugLoc(std::move(dl)) {
651 assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
653 // Reserve space for the expected number of operands.
654 if (unsigned NumOps = MCID->getNumOperands() +
655 MCID->getNumImplicitDefs() + MCID->getNumImplicitUses()) {
656 CapOperands = OperandCapacity::get(NumOps);
657 Operands = MF.allocateOperandArray(CapOperands);
661 addImplicitDefUseOperands(MF);
664 /// MachineInstr ctor - Copies MachineInstr arg exactly
666 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
667 : MCID(&MI.getDesc()), Parent(nullptr), Operands(nullptr), NumOperands(0),
668 Flags(0), AsmPrinterFlags(0),
669 NumMemRefs(MI.NumMemRefs), MemRefs(MI.MemRefs),
670 debugLoc(MI.getDebugLoc()) {
671 assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
673 CapOperands = OperandCapacity::get(MI.getNumOperands());
674 Operands = MF.allocateOperandArray(CapOperands);
677 for (const MachineOperand &MO : MI.operands())
680 // Copy all the sensible flags.
684 /// getRegInfo - If this instruction is embedded into a MachineFunction,
685 /// return the MachineRegisterInfo object for the current function, otherwise
687 MachineRegisterInfo *MachineInstr::getRegInfo() {
688 if (MachineBasicBlock *MBB = getParent())
689 return &MBB->getParent()->getRegInfo();
693 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
694 /// this instruction from their respective use lists. This requires that the
695 /// operands already be on their use lists.
696 void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo &MRI) {
697 for (MachineOperand &MO : operands())
699 MRI.removeRegOperandFromUseList(&MO);
702 /// AddRegOperandsToUseLists - Add all of the register operands in
703 /// this instruction from their respective use lists. This requires that the
704 /// operands not be on their use lists yet.
705 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &MRI) {
706 for (MachineOperand &MO : operands())
708 MRI.addRegOperandToUseList(&MO);
711 void MachineInstr::addOperand(const MachineOperand &Op) {
712 MachineBasicBlock *MBB = getParent();
713 assert(MBB && "Use MachineInstrBuilder to add operands to dangling instrs");
714 MachineFunction *MF = MBB->getParent();
715 assert(MF && "Use MachineInstrBuilder to add operands to dangling instrs");
719 /// Move NumOps MachineOperands from Src to Dst, with support for overlapping
720 /// ranges. If MRI is non-null also update use-def chains.
721 static void moveOperands(MachineOperand *Dst, MachineOperand *Src,
722 unsigned NumOps, MachineRegisterInfo *MRI) {
724 return MRI->moveOperands(Dst, Src, NumOps);
726 // MachineOperand is a trivially copyable type so we can just use memmove.
727 std::memmove(Dst, Src, NumOps * sizeof(MachineOperand));
730 /// addOperand - Add the specified operand to the instruction. If it is an
731 /// implicit operand, it is added to the end of the operand list. If it is
732 /// an explicit operand it is added at the end of the explicit operand list
733 /// (before the first implicit operand).
734 void MachineInstr::addOperand(MachineFunction &MF, const MachineOperand &Op) {
735 assert(MCID && "Cannot add operands before providing an instr descriptor");
737 // Check if we're adding one of our existing operands.
738 if (&Op >= Operands && &Op < Operands + NumOperands) {
739 // This is unusual: MI->addOperand(MI->getOperand(i)).
740 // If adding Op requires reallocating or moving existing operands around,
741 // the Op reference could go stale. Support it by copying Op.
742 MachineOperand CopyOp(Op);
743 return addOperand(MF, CopyOp);
746 // Find the insert location for the new operand. Implicit registers go at
747 // the end, everything else goes before the implicit regs.
749 // FIXME: Allow mixed explicit and implicit operands on inline asm.
750 // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
751 // implicit-defs, but they must not be moved around. See the FIXME in
753 unsigned OpNo = getNumOperands();
754 bool isImpReg = Op.isReg() && Op.isImplicit();
755 if (!isImpReg && !isInlineAsm()) {
756 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
758 assert(!Operands[OpNo].isTied() && "Cannot move tied operands");
763 bool isMetaDataOp = Op.getType() == MachineOperand::MO_Metadata;
764 // OpNo now points as the desired insertion point. Unless this is a variadic
765 // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
766 // RegMask operands go between the explicit and implicit operands.
767 assert((isImpReg || Op.isRegMask() || MCID->isVariadic() ||
768 OpNo < MCID->getNumOperands() || isMetaDataOp) &&
769 "Trying to add an operand to a machine instr that is already done!");
772 MachineRegisterInfo *MRI = getRegInfo();
774 // Determine if the Operands array needs to be reallocated.
775 // Save the old capacity and operand array.
776 OperandCapacity OldCap = CapOperands;
777 MachineOperand *OldOperands = Operands;
778 if (!OldOperands || OldCap.getSize() == getNumOperands()) {
779 CapOperands = OldOperands ? OldCap.getNext() : OldCap.get(1);
780 Operands = MF.allocateOperandArray(CapOperands);
781 // Move the operands before the insertion point.
783 moveOperands(Operands, OldOperands, OpNo, MRI);
786 // Move the operands following the insertion point.
787 if (OpNo != NumOperands)
788 moveOperands(Operands + OpNo + 1, OldOperands + OpNo, NumOperands - OpNo,
792 // Deallocate the old operand array.
793 if (OldOperands != Operands && OldOperands)
794 MF.deallocateOperandArray(OldCap, OldOperands);
796 // Copy Op into place. It still needs to be inserted into the MRI use lists.
797 MachineOperand *NewMO = new (Operands + OpNo) MachineOperand(Op);
798 NewMO->ParentMI = this;
800 // When adding a register operand, tell MRI about it.
801 if (NewMO->isReg()) {
802 // Ensure isOnRegUseList() returns false, regardless of Op's status.
803 NewMO->Contents.Reg.Prev = nullptr;
804 // Ignore existing ties. This is not a property that can be copied.
806 // Add the new operand to MRI, but only for instructions in an MBB.
808 MRI->addRegOperandToUseList(NewMO);
809 // The MCID operand information isn't accurate until we start adding
810 // explicit operands. The implicit operands are added first, then the
811 // explicits are inserted before them.
813 // Tie uses to defs as indicated in MCInstrDesc.
814 if (NewMO->isUse()) {
815 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO);
817 tieOperands(DefIdx, OpNo);
819 // If the register operand is flagged as early, mark the operand as such.
820 if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
821 NewMO->setIsEarlyClobber(true);
826 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
827 /// fewer operand than it started with.
829 void MachineInstr::RemoveOperand(unsigned OpNo) {
830 assert(OpNo < getNumOperands() && "Invalid operand number");
831 untieRegOperand(OpNo);
834 // Moving tied operands would break the ties.
835 for (unsigned i = OpNo + 1, e = getNumOperands(); i != e; ++i)
836 if (Operands[i].isReg())
837 assert(!Operands[i].isTied() && "Cannot move tied operands");
840 MachineRegisterInfo *MRI = getRegInfo();
841 if (MRI && Operands[OpNo].isReg())
842 MRI->removeRegOperandFromUseList(Operands + OpNo);
844 // Don't call the MachineOperand destructor. A lot of this code depends on
845 // MachineOperand having a trivial destructor anyway, and adding a call here
846 // wouldn't make it 'destructor-correct'.
848 if (unsigned N = NumOperands - 1 - OpNo)
849 moveOperands(Operands + OpNo, Operands + OpNo + 1, N, MRI);
853 /// addMemOperand - Add a MachineMemOperand to the machine instruction.
854 /// This function should be used only occasionally. The setMemRefs function
855 /// is the primary method for setting up a MachineInstr's MemRefs list.
856 void MachineInstr::addMemOperand(MachineFunction &MF,
857 MachineMemOperand *MO) {
858 mmo_iterator OldMemRefs = MemRefs;
859 unsigned OldNumMemRefs = NumMemRefs;
861 unsigned NewNum = NumMemRefs + 1;
862 mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum);
864 std::copy(OldMemRefs, OldMemRefs + OldNumMemRefs, NewMemRefs);
865 NewMemRefs[NewNum - 1] = MO;
866 setMemRefs(NewMemRefs, NewMemRefs + NewNum);
869 bool MachineInstr::hasPropertyInBundle(unsigned Mask, QueryType Type) const {
870 assert(!isBundledWithPred() && "Must be called on bundle header");
871 for (MachineBasicBlock::const_instr_iterator MII = getIterator();; ++MII) {
872 if (MII->getDesc().getFlags() & Mask) {
873 if (Type == AnyInBundle)
876 if (Type == AllInBundle && !MII->isBundle())
879 // This was the last instruction in the bundle.
880 if (!MII->isBundledWithSucc())
881 return Type == AllInBundle;
885 bool MachineInstr::isIdenticalTo(const MachineInstr *Other,
886 MICheckType Check) const {
887 // If opcodes or number of operands are not the same then the two
888 // instructions are obviously not identical.
889 if (Other->getOpcode() != getOpcode() ||
890 Other->getNumOperands() != getNumOperands())
894 // Both instructions are bundles, compare MIs inside the bundle.
895 MachineBasicBlock::const_instr_iterator I1 = getIterator();
896 MachineBasicBlock::const_instr_iterator E1 = getParent()->instr_end();
897 MachineBasicBlock::const_instr_iterator I2 = Other->getIterator();
898 MachineBasicBlock::const_instr_iterator E2= Other->getParent()->instr_end();
899 while (++I1 != E1 && I1->isInsideBundle()) {
901 if (I2 == E2 || !I2->isInsideBundle() || !I1->isIdenticalTo(&*I2, Check))
906 // Check operands to make sure they match.
907 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
908 const MachineOperand &MO = getOperand(i);
909 const MachineOperand &OMO = Other->getOperand(i);
911 if (!MO.isIdenticalTo(OMO))
916 // Clients may or may not want to ignore defs when testing for equality.
917 // For example, machine CSE pass only cares about finding common
918 // subexpressions, so it's safe to ignore virtual register defs.
920 if (Check == IgnoreDefs)
922 else if (Check == IgnoreVRegDefs) {
923 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) ||
924 TargetRegisterInfo::isPhysicalRegister(OMO.getReg()))
925 if (MO.getReg() != OMO.getReg())
928 if (!MO.isIdenticalTo(OMO))
930 if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
934 if (!MO.isIdenticalTo(OMO))
936 if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
940 // If DebugLoc does not match then two dbg.values are not identical.
942 if (getDebugLoc() && Other->getDebugLoc() &&
943 getDebugLoc() != Other->getDebugLoc())
948 MachineInstr *MachineInstr::removeFromParent() {
949 assert(getParent() && "Not embedded in a basic block!");
950 return getParent()->remove(this);
953 MachineInstr *MachineInstr::removeFromBundle() {
954 assert(getParent() && "Not embedded in a basic block!");
955 return getParent()->remove_instr(this);
958 void MachineInstr::eraseFromParent() {
959 assert(getParent() && "Not embedded in a basic block!");
960 getParent()->erase(this);
963 void MachineInstr::eraseFromParentAndMarkDBGValuesForRemoval() {
964 assert(getParent() && "Not embedded in a basic block!");
965 MachineBasicBlock *MBB = getParent();
966 MachineFunction *MF = MBB->getParent();
967 assert(MF && "Not embedded in a function!");
969 MachineInstr *MI = (MachineInstr *)this;
970 MachineRegisterInfo &MRI = MF->getRegInfo();
972 for (const MachineOperand &MO : MI->operands()) {
973 if (!MO.isReg() || !MO.isDef())
975 unsigned Reg = MO.getReg();
976 if (!TargetRegisterInfo::isVirtualRegister(Reg))
978 MRI.markUsesInDebugValueAsUndef(Reg);
980 MI->eraseFromParent();
983 void MachineInstr::eraseFromBundle() {
984 assert(getParent() && "Not embedded in a basic block!");
985 getParent()->erase_instr(this);
988 /// getNumExplicitOperands - Returns the number of non-implicit operands.
990 unsigned MachineInstr::getNumExplicitOperands() const {
991 unsigned NumOperands = MCID->getNumOperands();
992 if (!MCID->isVariadic())
995 for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) {
996 const MachineOperand &MO = getOperand(i);
997 if (!MO.isReg() || !MO.isImplicit())
1003 void MachineInstr::bundleWithPred() {
1004 assert(!isBundledWithPred() && "MI is already bundled with its predecessor");
1005 setFlag(BundledPred);
1006 MachineBasicBlock::instr_iterator Pred = getIterator();
1008 assert(!Pred->isBundledWithSucc() && "Inconsistent bundle flags");
1009 Pred->setFlag(BundledSucc);
1012 void MachineInstr::bundleWithSucc() {
1013 assert(!isBundledWithSucc() && "MI is already bundled with its successor");
1014 setFlag(BundledSucc);
1015 MachineBasicBlock::instr_iterator Succ = getIterator();
1017 assert(!Succ->isBundledWithPred() && "Inconsistent bundle flags");
1018 Succ->setFlag(BundledPred);
1021 void MachineInstr::unbundleFromPred() {
1022 assert(isBundledWithPred() && "MI isn't bundled with its predecessor");
1023 clearFlag(BundledPred);
1024 MachineBasicBlock::instr_iterator Pred = getIterator();
1026 assert(Pred->isBundledWithSucc() && "Inconsistent bundle flags");
1027 Pred->clearFlag(BundledSucc);
1030 void MachineInstr::unbundleFromSucc() {
1031 assert(isBundledWithSucc() && "MI isn't bundled with its successor");
1032 clearFlag(BundledSucc);
1033 MachineBasicBlock::instr_iterator Succ = getIterator();
1035 assert(Succ->isBundledWithPred() && "Inconsistent bundle flags");
1036 Succ->clearFlag(BundledPred);
1039 bool MachineInstr::isStackAligningInlineAsm() const {
1040 if (isInlineAsm()) {
1041 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1042 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1048 InlineAsm::AsmDialect MachineInstr::getInlineAsmDialect() const {
1049 assert(isInlineAsm() && "getInlineAsmDialect() only works for inline asms!");
1050 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1051 return InlineAsm::AsmDialect((ExtraInfo & InlineAsm::Extra_AsmDialect) != 0);
1054 int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx,
1055 unsigned *GroupNo) const {
1056 assert(isInlineAsm() && "Expected an inline asm instruction");
1057 assert(OpIdx < getNumOperands() && "OpIdx out of range");
1059 // Ignore queries about the initial operands.
1060 if (OpIdx < InlineAsm::MIOp_FirstOperand)
1065 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
1067 const MachineOperand &FlagMO = getOperand(i);
1068 // If we reach the implicit register operands, stop looking.
1069 if (!FlagMO.isImm())
1071 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
1072 if (i + NumOps > OpIdx) {
1082 const TargetRegisterClass*
1083 MachineInstr::getRegClassConstraint(unsigned OpIdx,
1084 const TargetInstrInfo *TII,
1085 const TargetRegisterInfo *TRI) const {
1086 assert(getParent() && "Can't have an MBB reference here!");
1087 assert(getParent()->getParent() && "Can't have an MF reference here!");
1088 const MachineFunction &MF = *getParent()->getParent();
1090 // Most opcodes have fixed constraints in their MCInstrDesc.
1092 return TII->getRegClass(getDesc(), OpIdx, TRI, MF);
1094 if (!getOperand(OpIdx).isReg())
1097 // For tied uses on inline asm, get the constraint from the def.
1099 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
1102 // Inline asm stores register class constraints in the flag word.
1103 int FlagIdx = findInlineAsmFlagIdx(OpIdx);
1107 unsigned Flag = getOperand(FlagIdx).getImm();
1109 if (InlineAsm::hasRegClassConstraint(Flag, RCID))
1110 return TRI->getRegClass(RCID);
1112 // Assume that all registers in a memory operand are pointers.
1113 if (InlineAsm::getKind(Flag) == InlineAsm::Kind_Mem)
1114 return TRI->getPointerRegClass(MF);
1119 const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVReg(
1120 unsigned Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII,
1121 const TargetRegisterInfo *TRI, bool ExploreBundle) const {
1122 // Check every operands inside the bundle if we have
1125 for (ConstMIBundleOperands OpndIt(this); OpndIt.isValid() && CurRC;
1127 CurRC = OpndIt->getParent()->getRegClassConstraintEffectForVRegImpl(
1128 OpndIt.getOperandNo(), Reg, CurRC, TII, TRI);
1130 // Otherwise, just check the current operands.
1131 for (unsigned i = 0, e = NumOperands; i < e && CurRC; ++i)
1132 CurRC = getRegClassConstraintEffectForVRegImpl(i, Reg, CurRC, TII, TRI);
1136 const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVRegImpl(
1137 unsigned OpIdx, unsigned Reg, const TargetRegisterClass *CurRC,
1138 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
1139 assert(CurRC && "Invalid initial register class");
1140 // Check if Reg is constrained by some of its use/def from MI.
1141 const MachineOperand &MO = getOperand(OpIdx);
1142 if (!MO.isReg() || MO.getReg() != Reg)
1144 // If yes, accumulate the constraints through the operand.
1145 return getRegClassConstraintEffect(OpIdx, CurRC, TII, TRI);
1148 const TargetRegisterClass *MachineInstr::getRegClassConstraintEffect(
1149 unsigned OpIdx, const TargetRegisterClass *CurRC,
1150 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
1151 const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI);
1152 const MachineOperand &MO = getOperand(OpIdx);
1153 assert(MO.isReg() &&
1154 "Cannot get register constraints for non-register operand");
1155 assert(CurRC && "Invalid initial register class");
1156 if (unsigned SubIdx = MO.getSubReg()) {
1158 CurRC = TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx);
1160 CurRC = TRI->getSubClassWithSubReg(CurRC, SubIdx);
1162 CurRC = TRI->getCommonSubClass(CurRC, OpRC);
1166 /// Return the number of instructions inside the MI bundle, not counting the
1167 /// header instruction.
1168 unsigned MachineInstr::getBundleSize() const {
1169 MachineBasicBlock::const_instr_iterator I = getIterator();
1171 while (I->isBundledWithSucc())
1176 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
1177 /// the specific register or -1 if it is not found. It further tightens
1178 /// the search criteria to a use that kills the register if isKill is true.
1179 int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
1180 const TargetRegisterInfo *TRI) const {
1181 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1182 const MachineOperand &MO = getOperand(i);
1183 if (!MO.isReg() || !MO.isUse())
1185 unsigned MOReg = MO.getReg();
1190 TargetRegisterInfo::isPhysicalRegister(MOReg) &&
1191 TargetRegisterInfo::isPhysicalRegister(Reg) &&
1192 TRI->isSubRegister(MOReg, Reg)))
1193 if (!isKill || MO.isKill())
1199 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
1200 /// indicating if this instruction reads or writes Reg. This also considers
1201 /// partial defines.
1202 std::pair<bool,bool>
1203 MachineInstr::readsWritesVirtualRegister(unsigned Reg,
1204 SmallVectorImpl<unsigned> *Ops) const {
1205 bool PartDef = false; // Partial redefine.
1206 bool FullDef = false; // Full define.
1209 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1210 const MachineOperand &MO = getOperand(i);
1211 if (!MO.isReg() || MO.getReg() != Reg)
1216 Use |= !MO.isUndef();
1217 else if (MO.getSubReg() && !MO.isUndef())
1218 // A partial <def,undef> doesn't count as reading the register.
1223 // A partial redefine uses Reg unless there is also a full define.
1224 return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
1227 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
1228 /// the specified register or -1 if it is not found. If isDead is true, defs
1229 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
1230 /// also checks if there is a def of a super-register.
1232 MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap,
1233 const TargetRegisterInfo *TRI) const {
1234 bool isPhys = TargetRegisterInfo::isPhysicalRegister(Reg);
1235 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1236 const MachineOperand &MO = getOperand(i);
1237 // Accept regmask operands when Overlap is set.
1238 // Ignore them when looking for a specific def operand (Overlap == false).
1239 if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg))
1241 if (!MO.isReg() || !MO.isDef())
1243 unsigned MOReg = MO.getReg();
1244 bool Found = (MOReg == Reg);
1245 if (!Found && TRI && isPhys &&
1246 TargetRegisterInfo::isPhysicalRegister(MOReg)) {
1248 Found = TRI->regsOverlap(MOReg, Reg);
1250 Found = TRI->isSubRegister(MOReg, Reg);
1252 if (Found && (!isDead || MO.isDead()))
1258 /// findFirstPredOperandIdx() - Find the index of the first operand in the
1259 /// operand list that is used to represent the predicate. It returns -1 if
1261 int MachineInstr::findFirstPredOperandIdx() const {
1262 // Don't call MCID.findFirstPredOperandIdx() because this variant
1263 // is sometimes called on an instruction that's not yet complete, and
1264 // so the number of operands is less than the MCID indicates. In
1265 // particular, the PTX target does this.
1266 const MCInstrDesc &MCID = getDesc();
1267 if (MCID.isPredicable()) {
1268 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
1269 if (MCID.OpInfo[i].isPredicate())
1276 // MachineOperand::TiedTo is 4 bits wide.
1277 const unsigned TiedMax = 15;
1279 /// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other.
1281 /// Use and def operands can be tied together, indicated by a non-zero TiedTo
1282 /// field. TiedTo can have these values:
1284 /// 0: Operand is not tied to anything.
1285 /// 1 to TiedMax-1: Tied to getOperand(TiedTo-1).
1286 /// TiedMax: Tied to an operand >= TiedMax-1.
1288 /// The tied def must be one of the first TiedMax operands on a normal
1289 /// instruction. INLINEASM instructions allow more tied defs.
1291 void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) {
1292 MachineOperand &DefMO = getOperand(DefIdx);
1293 MachineOperand &UseMO = getOperand(UseIdx);
1294 assert(DefMO.isDef() && "DefIdx must be a def operand");
1295 assert(UseMO.isUse() && "UseIdx must be a use operand");
1296 assert(!DefMO.isTied() && "Def is already tied to another use");
1297 assert(!UseMO.isTied() && "Use is already tied to another def");
1299 if (DefIdx < TiedMax)
1300 UseMO.TiedTo = DefIdx + 1;
1302 // Inline asm can use the group descriptors to find tied operands, but on
1303 // normal instruction, the tied def must be within the first TiedMax
1305 assert(isInlineAsm() && "DefIdx out of range");
1306 UseMO.TiedTo = TiedMax;
1309 // UseIdx can be out of range, we'll search for it in findTiedOperandIdx().
1310 DefMO.TiedTo = std::min(UseIdx + 1, TiedMax);
1313 /// Given the index of a tied register operand, find the operand it is tied to.
1314 /// Defs are tied to uses and vice versa. Returns the index of the tied operand
1315 /// which must exist.
1316 unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const {
1317 const MachineOperand &MO = getOperand(OpIdx);
1318 assert(MO.isTied() && "Operand isn't tied");
1320 // Normally TiedTo is in range.
1321 if (MO.TiedTo < TiedMax)
1322 return MO.TiedTo - 1;
1324 // Uses on normal instructions can be out of range.
1325 if (!isInlineAsm()) {
1326 // Normal tied defs must be in the 0..TiedMax-1 range.
1329 // MO is a def. Search for the tied use.
1330 for (unsigned i = TiedMax - 1, e = getNumOperands(); i != e; ++i) {
1331 const MachineOperand &UseMO = getOperand(i);
1332 if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1)
1335 llvm_unreachable("Can't find tied use");
1338 // Now deal with inline asm by parsing the operand group descriptor flags.
1339 // Find the beginning of each operand group.
1340 SmallVector<unsigned, 8> GroupIdx;
1341 unsigned OpIdxGroup = ~0u;
1343 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
1345 const MachineOperand &FlagMO = getOperand(i);
1346 assert(FlagMO.isImm() && "Invalid tied operand on inline asm");
1347 unsigned CurGroup = GroupIdx.size();
1348 GroupIdx.push_back(i);
1349 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
1350 // OpIdx belongs to this operand group.
1351 if (OpIdx > i && OpIdx < i + NumOps)
1352 OpIdxGroup = CurGroup;
1354 if (!InlineAsm::isUseOperandTiedToDef(FlagMO.getImm(), TiedGroup))
1356 // Operands in this group are tied to operands in TiedGroup which must be
1357 // earlier. Find the number of operands between the two groups.
1358 unsigned Delta = i - GroupIdx[TiedGroup];
1360 // OpIdx is a use tied to TiedGroup.
1361 if (OpIdxGroup == CurGroup)
1362 return OpIdx - Delta;
1364 // OpIdx is a def tied to this use group.
1365 if (OpIdxGroup == TiedGroup)
1366 return OpIdx + Delta;
1368 llvm_unreachable("Invalid tied operand on inline asm");
1371 /// clearKillInfo - Clears kill flags on all operands.
1373 void MachineInstr::clearKillInfo() {
1374 for (MachineOperand &MO : operands()) {
1375 if (MO.isReg() && MO.isUse())
1376 MO.setIsKill(false);
1380 void MachineInstr::substituteRegister(unsigned FromReg,
1383 const TargetRegisterInfo &RegInfo) {
1384 if (TargetRegisterInfo::isPhysicalRegister(ToReg)) {
1386 ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1387 for (MachineOperand &MO : operands()) {
1388 if (!MO.isReg() || MO.getReg() != FromReg)
1390 MO.substPhysReg(ToReg, RegInfo);
1393 for (MachineOperand &MO : operands()) {
1394 if (!MO.isReg() || MO.getReg() != FromReg)
1396 MO.substVirtReg(ToReg, SubIdx, RegInfo);
1401 /// isSafeToMove - Return true if it is safe to move this instruction. If
1402 /// SawStore is set to true, it means that there is a store (or call) between
1403 /// the instruction's location and its intended destination.
1404 bool MachineInstr::isSafeToMove(AliasAnalysis *AA, bool &SawStore) const {
1405 // Ignore stuff that we obviously can't move.
1407 // Treat volatile loads as stores. This is not strictly necessary for
1408 // volatiles, but it is required for atomic loads. It is not allowed to move
1409 // a load across an atomic load with Ordering > Monotonic.
1410 if (mayStore() || isCall() ||
1411 (mayLoad() && hasOrderedMemoryRef())) {
1416 if (isPosition() || isDebugValue() || isTerminator() ||
1417 hasUnmodeledSideEffects())
1420 // See if this instruction does a load. If so, we have to guarantee that the
1421 // loaded value doesn't change between the load and the its intended
1422 // destination. The check for isInvariantLoad gives the targe the chance to
1423 // classify the load as always returning a constant, e.g. a constant pool
1425 if (mayLoad() && !isInvariantLoad(AA))
1426 // Otherwise, this is a real load. If there is a store between the load and
1427 // end of block, we can't move it.
1433 /// hasOrderedMemoryRef - Return true if this instruction may have an ordered
1434 /// or volatile memory reference, or if the information describing the memory
1435 /// reference is not available. Return false if it is known to have no ordered
1436 /// memory references.
1437 bool MachineInstr::hasOrderedMemoryRef() const {
1438 // An instruction known never to access memory won't have a volatile access.
1442 !hasUnmodeledSideEffects())
1445 // Otherwise, if the instruction has no memory reference information,
1446 // conservatively assume it wasn't preserved.
1447 if (memoperands_empty())
1450 // Check the memory reference information for ordered references.
1451 for (mmo_iterator I = memoperands_begin(), E = memoperands_end(); I != E; ++I)
1452 if (!(*I)->isUnordered())
1458 /// isInvariantLoad - Return true if this instruction is loading from a
1459 /// location whose value is invariant across the function. For example,
1460 /// loading a value from the constant pool or from the argument area
1461 /// of a function if it does not change. This should only return true of
1462 /// *all* loads the instruction does are invariant (if it does multiple loads).
1463 bool MachineInstr::isInvariantLoad(AliasAnalysis *AA) const {
1464 // If the instruction doesn't load at all, it isn't an invariant load.
1468 // If the instruction has lost its memoperands, conservatively assume that
1469 // it may not be an invariant load.
1470 if (memoperands_empty())
1473 const MachineFrameInfo *MFI = getParent()->getParent()->getFrameInfo();
1475 for (mmo_iterator I = memoperands_begin(),
1476 E = memoperands_end(); I != E; ++I) {
1477 if ((*I)->isVolatile()) return false;
1478 if ((*I)->isStore()) return false;
1479 if ((*I)->isInvariant()) return true;
1482 // A load from a constant PseudoSourceValue is invariant.
1483 if (const PseudoSourceValue *PSV = (*I)->getPseudoValue())
1484 if (PSV->isConstant(MFI))
1487 if (const Value *V = (*I)->getValue()) {
1488 // If we have an AliasAnalysis, ask it whether the memory is constant.
1490 AA->pointsToConstantMemory(
1491 MemoryLocation(V, (*I)->getSize(), (*I)->getAAInfo())))
1495 // Otherwise assume conservatively.
1499 // Everything checks out.
1503 /// isConstantValuePHI - If the specified instruction is a PHI that always
1504 /// merges together the same virtual register, return the register, otherwise
1506 unsigned MachineInstr::isConstantValuePHI() const {
1509 assert(getNumOperands() >= 3 &&
1510 "It's illegal to have a PHI without source operands");
1512 unsigned Reg = getOperand(1).getReg();
1513 for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1514 if (getOperand(i).getReg() != Reg)
1519 bool MachineInstr::hasUnmodeledSideEffects() const {
1520 if (hasProperty(MCID::UnmodeledSideEffects))
1522 if (isInlineAsm()) {
1523 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1524 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1531 bool MachineInstr::isLoadFoldBarrier() const {
1532 return mayStore() || isCall() || hasUnmodeledSideEffects();
1535 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
1537 bool MachineInstr::allDefsAreDead() const {
1538 for (const MachineOperand &MO : operands()) {
1539 if (!MO.isReg() || MO.isUse())
1547 /// copyImplicitOps - Copy implicit register operands from specified
1548 /// instruction to this instruction.
1549 void MachineInstr::copyImplicitOps(MachineFunction &MF,
1550 const MachineInstr *MI) {
1551 for (unsigned i = MI->getDesc().getNumOperands(), e = MI->getNumOperands();
1553 const MachineOperand &MO = MI->getOperand(i);
1554 if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask())
1559 void MachineInstr::dump() const {
1560 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1561 dbgs() << " " << *this;
1565 void MachineInstr::print(raw_ostream &OS, bool SkipOpers) const {
1566 const Module *M = nullptr;
1567 if (const MachineBasicBlock *MBB = getParent())
1568 if (const MachineFunction *MF = MBB->getParent())
1569 M = MF->getFunction()->getParent();
1571 ModuleSlotTracker MST(M);
1572 print(OS, MST, SkipOpers);
1575 void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
1576 bool SkipOpers) const {
1577 // We can be a bit tidier if we know the MachineFunction.
1578 const MachineFunction *MF = nullptr;
1579 const TargetRegisterInfo *TRI = nullptr;
1580 const MachineRegisterInfo *MRI = nullptr;
1581 const TargetInstrInfo *TII = nullptr;
1582 if (const MachineBasicBlock *MBB = getParent()) {
1583 MF = MBB->getParent();
1585 MRI = &MF->getRegInfo();
1586 TRI = MF->getSubtarget().getRegisterInfo();
1587 TII = MF->getSubtarget().getInstrInfo();
1591 // Save a list of virtual registers.
1592 SmallVector<unsigned, 8> VirtRegs;
1594 // Print explicitly defined operands on the left of an assignment syntax.
1595 unsigned StartOp = 0, e = getNumOperands();
1596 for (; StartOp < e && getOperand(StartOp).isReg() &&
1597 getOperand(StartOp).isDef() &&
1598 !getOperand(StartOp).isImplicit();
1600 if (StartOp != 0) OS << ", ";
1601 getOperand(StartOp).print(OS, MST, TRI);
1602 unsigned Reg = getOperand(StartOp).getReg();
1603 if (TargetRegisterInfo::isVirtualRegister(Reg))
1604 VirtRegs.push_back(Reg);
1610 // Print the opcode name.
1612 OS << TII->getName(getOpcode());
1619 // Print the rest of the operands.
1620 bool OmittedAnyCallClobbers = false;
1621 bool FirstOp = true;
1622 unsigned AsmDescOp = ~0u;
1623 unsigned AsmOpCount = 0;
1625 if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) {
1626 // Print asm string.
1628 getOperand(InlineAsm::MIOp_AsmString).print(OS, MST, TRI);
1630 // Print HasSideEffects, MayLoad, MayStore, IsAlignStack
1631 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1632 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1633 OS << " [sideeffect]";
1634 if (ExtraInfo & InlineAsm::Extra_MayLoad)
1636 if (ExtraInfo & InlineAsm::Extra_MayStore)
1637 OS << " [maystore]";
1638 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1639 OS << " [alignstack]";
1640 if (getInlineAsmDialect() == InlineAsm::AD_ATT)
1641 OS << " [attdialect]";
1642 if (getInlineAsmDialect() == InlineAsm::AD_Intel)
1643 OS << " [inteldialect]";
1645 StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
1649 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1650 const MachineOperand &MO = getOperand(i);
1652 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1653 VirtRegs.push_back(MO.getReg());
1655 // Omit call-clobbered registers which aren't used anywhere. This makes
1656 // call instructions much less noisy on targets where calls clobber lots
1657 // of registers. Don't rely on MO.isDead() because we may be called before
1658 // LiveVariables is run, or we may be looking at a non-allocatable reg.
1659 if (MRI && isCall() &&
1660 MO.isReg() && MO.isImplicit() && MO.isDef()) {
1661 unsigned Reg = MO.getReg();
1662 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
1663 if (MRI->use_empty(Reg)) {
1664 bool HasAliasLive = false;
1665 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
1666 unsigned AliasReg = *AI;
1667 if (!MRI->use_empty(AliasReg)) {
1668 HasAliasLive = true;
1672 if (!HasAliasLive) {
1673 OmittedAnyCallClobbers = true;
1680 if (FirstOp) FirstOp = false; else OS << ",";
1682 if (i < getDesc().NumOperands) {
1683 const MCOperandInfo &MCOI = getDesc().OpInfo[i];
1684 if (MCOI.isPredicate())
1686 if (MCOI.isOptionalDef())
1689 if (isDebugValue() && MO.isMetadata()) {
1690 // Pretty print DBG_VALUE instructions.
1691 auto *DIV = dyn_cast<DILocalVariable>(MO.getMetadata());
1692 if (DIV && !DIV->getName().empty())
1693 OS << "!\"" << DIV->getName() << '\"';
1695 MO.print(OS, MST, TRI);
1696 } else if (TRI && (isInsertSubreg() || isRegSequence()) && MO.isImm()) {
1697 OS << TRI->getSubRegIndexName(MO.getImm());
1698 } else if (i == AsmDescOp && MO.isImm()) {
1699 // Pretty print the inline asm operand descriptor.
1700 OS << '$' << AsmOpCount++;
1701 unsigned Flag = MO.getImm();
1702 switch (InlineAsm::getKind(Flag)) {
1703 case InlineAsm::Kind_RegUse: OS << ":[reguse"; break;
1704 case InlineAsm::Kind_RegDef: OS << ":[regdef"; break;
1705 case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec"; break;
1706 case InlineAsm::Kind_Clobber: OS << ":[clobber"; break;
1707 case InlineAsm::Kind_Imm: OS << ":[imm"; break;
1708 case InlineAsm::Kind_Mem: OS << ":[mem"; break;
1709 default: OS << ":[??" << InlineAsm::getKind(Flag); break;
1713 if (InlineAsm::hasRegClassConstraint(Flag, RCID)) {
1715 OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID));
1717 OS << ":RC" << RCID;
1720 unsigned TiedTo = 0;
1721 if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo))
1722 OS << " tiedto:$" << TiedTo;
1726 // Compute the index of the next operand descriptor.
1727 AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
1729 MO.print(OS, MST, TRI);
1732 // Briefly indicate whether any call clobbers were omitted.
1733 if (OmittedAnyCallClobbers) {
1734 if (!FirstOp) OS << ",";
1738 bool HaveSemi = false;
1739 const unsigned PrintableFlags = FrameSetup | FrameDestroy;
1740 if (Flags & PrintableFlags) {
1741 if (!HaveSemi) OS << ";"; HaveSemi = true;
1744 if (Flags & FrameSetup)
1747 if (Flags & FrameDestroy)
1748 OS << "FrameDestroy";
1751 if (!memoperands_empty()) {
1752 if (!HaveSemi) OS << ";"; HaveSemi = true;
1755 for (mmo_iterator i = memoperands_begin(), e = memoperands_end();
1757 (*i)->print(OS, MST);
1758 if (std::next(i) != e)
1763 // Print the regclass of any virtual registers encountered.
1764 if (MRI && !VirtRegs.empty()) {
1765 if (!HaveSemi) OS << ";"; HaveSemi = true;
1766 for (unsigned i = 0; i != VirtRegs.size(); ++i) {
1767 const TargetRegisterClass *RC = MRI->getRegClass(VirtRegs[i]);
1768 OS << " " << TRI->getRegClassName(RC)
1769 << ':' << PrintReg(VirtRegs[i]);
1770 for (unsigned j = i+1; j != VirtRegs.size();) {
1771 if (MRI->getRegClass(VirtRegs[j]) != RC) {
1775 if (VirtRegs[i] != VirtRegs[j])
1776 OS << "," << PrintReg(VirtRegs[j]);
1777 VirtRegs.erase(VirtRegs.begin()+j);
1782 // Print debug location information.
1783 if (isDebugValue() && getOperand(e - 2).isMetadata()) {
1784 if (!HaveSemi) OS << ";";
1785 auto *DV = cast<DILocalVariable>(getOperand(e - 2).getMetadata());
1786 OS << " line no:" << DV->getLine();
1787 if (auto *InlinedAt = debugLoc->getInlinedAt()) {
1788 DebugLoc InlinedAtDL(InlinedAt);
1789 if (InlinedAtDL && MF) {
1790 OS << " inlined @[ ";
1791 InlinedAtDL.print(OS);
1795 if (isIndirectDebugValue())
1797 } else if (debugLoc && MF) {
1798 if (!HaveSemi) OS << ";";
1806 bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
1807 const TargetRegisterInfo *RegInfo,
1808 bool AddIfNotFound) {
1809 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1810 bool hasAliases = isPhysReg &&
1811 MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
1813 SmallVector<unsigned,4> DeadOps;
1814 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1815 MachineOperand &MO = getOperand(i);
1816 if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1818 unsigned Reg = MO.getReg();
1822 if (Reg == IncomingReg) {
1825 // The register is already marked kill.
1827 if (isPhysReg && isRegTiedToDefOperand(i))
1828 // Two-address uses of physregs must not be marked kill.
1833 } else if (hasAliases && MO.isKill() &&
1834 TargetRegisterInfo::isPhysicalRegister(Reg)) {
1835 // A super-register kill already exists.
1836 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1838 if (RegInfo->isSubRegister(IncomingReg, Reg))
1839 DeadOps.push_back(i);
1843 // Trim unneeded kill operands.
1844 while (!DeadOps.empty()) {
1845 unsigned OpIdx = DeadOps.back();
1846 if (getOperand(OpIdx).isImplicit())
1847 RemoveOperand(OpIdx);
1849 getOperand(OpIdx).setIsKill(false);
1853 // If not found, this means an alias of one of the operands is killed. Add a
1854 // new implicit operand if required.
1855 if (!Found && AddIfNotFound) {
1856 addOperand(MachineOperand::CreateReg(IncomingReg,
1865 void MachineInstr::clearRegisterKills(unsigned Reg,
1866 const TargetRegisterInfo *RegInfo) {
1867 if (!TargetRegisterInfo::isPhysicalRegister(Reg))
1869 for (MachineOperand &MO : operands()) {
1870 if (!MO.isReg() || !MO.isUse() || !MO.isKill())
1872 unsigned OpReg = MO.getReg();
1873 if (OpReg == Reg || (RegInfo && RegInfo->isSuperRegister(Reg, OpReg)))
1874 MO.setIsKill(false);
1878 bool MachineInstr::addRegisterDead(unsigned Reg,
1879 const TargetRegisterInfo *RegInfo,
1880 bool AddIfNotFound) {
1881 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(Reg);
1882 bool hasAliases = isPhysReg &&
1883 MCRegAliasIterator(Reg, RegInfo, false).isValid();
1885 SmallVector<unsigned,4> DeadOps;
1886 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1887 MachineOperand &MO = getOperand(i);
1888 if (!MO.isReg() || !MO.isDef())
1890 unsigned MOReg = MO.getReg();
1897 } else if (hasAliases && MO.isDead() &&
1898 TargetRegisterInfo::isPhysicalRegister(MOReg)) {
1899 // There exists a super-register that's marked dead.
1900 if (RegInfo->isSuperRegister(Reg, MOReg))
1902 if (RegInfo->isSubRegister(Reg, MOReg))
1903 DeadOps.push_back(i);
1907 // Trim unneeded dead operands.
1908 while (!DeadOps.empty()) {
1909 unsigned OpIdx = DeadOps.back();
1910 if (getOperand(OpIdx).isImplicit())
1911 RemoveOperand(OpIdx);
1913 getOperand(OpIdx).setIsDead(false);
1917 // If not found, this means an alias of one of the operands is dead. Add a
1918 // new implicit operand if required.
1919 if (Found || !AddIfNotFound)
1922 addOperand(MachineOperand::CreateReg(Reg,
1930 void MachineInstr::clearRegisterDeads(unsigned Reg) {
1931 for (MachineOperand &MO : operands()) {
1932 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg)
1934 MO.setIsDead(false);
1938 void MachineInstr::setRegisterDefReadUndef(unsigned Reg, bool IsUndef) {
1939 for (MachineOperand &MO : operands()) {
1940 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg || MO.getSubReg() == 0)
1942 MO.setIsUndef(IsUndef);
1946 void MachineInstr::addRegisterDefined(unsigned Reg,
1947 const TargetRegisterInfo *RegInfo) {
1948 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
1949 MachineOperand *MO = findRegisterDefOperand(Reg, false, RegInfo);
1953 for (const MachineOperand &MO : operands()) {
1954 if (MO.isReg() && MO.getReg() == Reg && MO.isDef() &&
1955 MO.getSubReg() == 0)
1959 addOperand(MachineOperand::CreateReg(Reg,
1964 void MachineInstr::setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs,
1965 const TargetRegisterInfo &TRI) {
1966 bool HasRegMask = false;
1967 for (MachineOperand &MO : operands()) {
1968 if (MO.isRegMask()) {
1972 if (!MO.isReg() || !MO.isDef()) continue;
1973 unsigned Reg = MO.getReg();
1974 if (!TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
1975 // If there are no uses, including partial uses, the def is dead.
1976 if (std::none_of(UsedRegs.begin(), UsedRegs.end(),
1977 [&](unsigned Use) { return TRI.regsOverlap(Use, Reg); }))
1981 // This is a call with a register mask operand.
1982 // Mask clobbers are always dead, so add defs for the non-dead defines.
1984 for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end();
1986 addRegisterDefined(*I, &TRI);
1990 MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
1991 // Build up a buffer of hash code components.
1992 SmallVector<size_t, 8> HashComponents;
1993 HashComponents.reserve(MI->getNumOperands() + 1);
1994 HashComponents.push_back(MI->getOpcode());
1995 for (const MachineOperand &MO : MI->operands()) {
1996 if (MO.isReg() && MO.isDef() &&
1997 TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1998 continue; // Skip virtual register defs.
2000 HashComponents.push_back(hash_value(MO));
2002 return hash_combine_range(HashComponents.begin(), HashComponents.end());
2005 void MachineInstr::emitError(StringRef Msg) const {
2006 // Find the source location cookie.
2007 unsigned LocCookie = 0;
2008 const MDNode *LocMD = nullptr;
2009 for (unsigned i = getNumOperands(); i != 0; --i) {
2010 if (getOperand(i-1).isMetadata() &&
2011 (LocMD = getOperand(i-1).getMetadata()) &&
2012 LocMD->getNumOperands() != 0) {
2013 if (const ConstantInt *CI =
2014 mdconst::dyn_extract<ConstantInt>(LocMD->getOperand(0))) {
2015 LocCookie = CI->getZExtValue();
2021 if (const MachineBasicBlock *MBB = getParent())
2022 if (const MachineFunction *MF = MBB->getParent())
2023 return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
2024 report_fatal_error(Msg);