1 //===-- llvm/CodeGen/MachineBasicBlock.cpp ----------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Collect the sequence of machine instructions for a basic block.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/MachineBasicBlock.h"
15 #include "llvm/ADT/SmallPtrSet.h"
16 #include "llvm/ADT/SmallString.h"
17 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
18 #include "llvm/CodeGen/LiveVariables.h"
19 #include "llvm/CodeGen/MachineDominators.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineLoopInfo.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/SlotIndexes.h"
25 #include "llvm/IR/BasicBlock.h"
26 #include "llvm/IR/DataLayout.h"
27 #include "llvm/IR/ModuleSlotTracker.h"
28 #include "llvm/MC/MCAsmInfo.h"
29 #include "llvm/MC/MCContext.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/raw_ostream.h"
32 #include "llvm/Target/TargetInstrInfo.h"
33 #include "llvm/Target/TargetMachine.h"
34 #include "llvm/Target/TargetRegisterInfo.h"
35 #include "llvm/Target/TargetSubtargetInfo.h"
39 #define DEBUG_TYPE "codegen"
41 MachineBasicBlock::MachineBasicBlock(MachineFunction &mf, const BasicBlock *bb)
42 : BB(bb), Number(-1), xParent(&mf) {
46 MachineBasicBlock::~MachineBasicBlock() {
49 /// Return the MCSymbol for this basic block.
50 MCSymbol *MachineBasicBlock::getSymbol() const {
51 if (!CachedMCSymbol) {
52 const MachineFunction *MF = getParent();
53 MCContext &Ctx = MF->getContext();
54 const char *Prefix = Ctx.getAsmInfo()->getPrivateLabelPrefix();
55 CachedMCSymbol = Ctx.getOrCreateSymbol(Twine(Prefix) + "BB" +
56 Twine(MF->getFunctionNumber()) +
57 "_" + Twine(getNumber()));
60 return CachedMCSymbol;
64 raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineBasicBlock &MBB) {
69 /// When an MBB is added to an MF, we need to update the parent pointer of the
70 /// MBB, the MBB numbering, and any instructions in the MBB to be on the right
71 /// operand list for registers.
73 /// MBBs start out as #-1. When a MBB is added to a MachineFunction, it
74 /// gets the next available unique MBB number. If it is removed from a
75 /// MachineFunction, it goes back to being #-1.
76 void ilist_traits<MachineBasicBlock>::addNodeToList(MachineBasicBlock *N) {
77 MachineFunction &MF = *N->getParent();
78 N->Number = MF.addToMBBNumbering(N);
80 // Make sure the instructions have their operands in the reginfo lists.
81 MachineRegisterInfo &RegInfo = MF.getRegInfo();
82 for (MachineBasicBlock::instr_iterator
83 I = N->instr_begin(), E = N->instr_end(); I != E; ++I)
84 I->AddRegOperandsToUseLists(RegInfo);
87 void ilist_traits<MachineBasicBlock>::removeNodeFromList(MachineBasicBlock *N) {
88 N->getParent()->removeFromMBBNumbering(N->Number);
92 /// When we add an instruction to a basic block list, we update its parent
93 /// pointer and add its operands from reg use/def lists if appropriate.
94 void ilist_traits<MachineInstr>::addNodeToList(MachineInstr *N) {
95 assert(!N->getParent() && "machine instruction already in a basic block");
98 // Add the instruction's register operands to their corresponding
100 MachineFunction *MF = Parent->getParent();
101 N->AddRegOperandsToUseLists(MF->getRegInfo());
104 /// When we remove an instruction from a basic block list, we update its parent
105 /// pointer and remove its operands from reg use/def lists if appropriate.
106 void ilist_traits<MachineInstr>::removeNodeFromList(MachineInstr *N) {
107 assert(N->getParent() && "machine instruction not in a basic block");
109 // Remove from the use/def lists.
110 if (MachineFunction *MF = N->getParent()->getParent())
111 N->RemoveRegOperandsFromUseLists(MF->getRegInfo());
113 N->setParent(nullptr);
116 /// When moving a range of instructions from one MBB list to another, we need to
117 /// update the parent pointers and the use/def lists.
118 void ilist_traits<MachineInstr>::
119 transferNodesFromList(ilist_traits<MachineInstr> &fromList,
120 ilist_iterator<MachineInstr> first,
121 ilist_iterator<MachineInstr> last) {
122 assert(Parent->getParent() == fromList.Parent->getParent() &&
123 "MachineInstr parent mismatch!");
125 // Splice within the same MBB -> no change.
126 if (Parent == fromList.Parent) return;
128 // If splicing between two blocks within the same function, just update the
130 for (; first != last; ++first)
131 first->setParent(Parent);
134 void ilist_traits<MachineInstr>::deleteNode(MachineInstr* MI) {
135 assert(!MI->getParent() && "MI is still in a block!");
136 Parent->getParent()->DeleteMachineInstr(MI);
139 MachineBasicBlock::iterator MachineBasicBlock::getFirstNonPHI() {
140 instr_iterator I = instr_begin(), E = instr_end();
141 while (I != E && I->isPHI())
143 assert((I == E || !I->isInsideBundle()) &&
144 "First non-phi MI cannot be inside a bundle!");
148 MachineBasicBlock::iterator
149 MachineBasicBlock::SkipPHIsAndLabels(MachineBasicBlock::iterator I) {
151 while (I != E && (I->isPHI() || I->isPosition() || I->isDebugValue()))
153 // FIXME: This needs to change if we wish to bundle labels / dbg_values
154 // inside the bundle.
155 assert((I == E || !I->isInsideBundle()) &&
156 "First non-phi / non-label instruction is inside a bundle!");
160 MachineBasicBlock::iterator MachineBasicBlock::getFirstTerminator() {
161 iterator B = begin(), E = end(), I = E;
162 while (I != B && ((--I)->isTerminator() || I->isDebugValue()))
164 while (I != E && !I->isTerminator())
169 MachineBasicBlock::instr_iterator MachineBasicBlock::getFirstInstrTerminator() {
170 instr_iterator B = instr_begin(), E = instr_end(), I = E;
171 while (I != B && ((--I)->isTerminator() || I->isDebugValue()))
173 while (I != E && !I->isTerminator())
178 MachineBasicBlock::iterator MachineBasicBlock::getFirstNonDebugInstr() {
179 // Skip over begin-of-block dbg_value instructions.
180 iterator I = begin(), E = end();
181 while (I != E && I->isDebugValue())
186 MachineBasicBlock::iterator MachineBasicBlock::getLastNonDebugInstr() {
187 // Skip over end-of-block dbg_value instructions.
188 instr_iterator B = instr_begin(), I = instr_end();
191 // Return instruction that starts a bundle.
192 if (I->isDebugValue() || I->isInsideBundle())
196 // The block is all debug values.
200 const MachineBasicBlock *MachineBasicBlock::getLandingPadSuccessor() const {
201 // A block with a landing pad successor only has one other successor.
204 for (const_succ_iterator I = succ_begin(), E = succ_end(); I != E; ++I)
210 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
211 void MachineBasicBlock::dump() const {
216 StringRef MachineBasicBlock::getName() const {
217 if (const BasicBlock *LBB = getBasicBlock())
218 return LBB->getName();
223 /// Return a hopefully unique identifier for this block.
224 std::string MachineBasicBlock::getFullName() const {
227 Name = (getParent()->getName() + ":").str();
229 Name += getBasicBlock()->getName();
231 Name += ("BB" + Twine(getNumber())).str();
235 void MachineBasicBlock::print(raw_ostream &OS, SlotIndexes *Indexes) const {
236 const MachineFunction *MF = getParent();
238 OS << "Can't print out MachineBasicBlock because parent MachineFunction"
242 const Function *F = MF->getFunction();
243 const Module *M = F ? F->getParent() : nullptr;
244 ModuleSlotTracker MST(M);
245 print(OS, MST, Indexes);
248 void MachineBasicBlock::print(raw_ostream &OS, ModuleSlotTracker &MST,
249 SlotIndexes *Indexes) const {
250 const MachineFunction *MF = getParent();
252 OS << "Can't print out MachineBasicBlock because parent MachineFunction"
258 OS << Indexes->getMBBStartIdx(this) << '\t';
260 OS << "BB#" << getNumber() << ": ";
262 const char *Comma = "";
263 if (const BasicBlock *LBB = getBasicBlock()) {
264 OS << Comma << "derived from LLVM BB ";
265 LBB->printAsOperand(OS, /*PrintType=*/false, MST);
268 if (isEHPad()) { OS << Comma << "EH LANDING PAD"; Comma = ", "; }
269 if (hasAddressTaken()) { OS << Comma << "ADDRESS TAKEN"; Comma = ", "; }
271 OS << Comma << "Align " << Alignment << " (" << (1u << Alignment)
276 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
277 if (!livein_empty()) {
278 if (Indexes) OS << '\t';
280 for (unsigned LI : make_range(livein_begin(), livein_end())) {
281 OS << ' ' << PrintReg(LI, TRI);
285 // Print the preds of this block according to the CFG.
287 if (Indexes) OS << '\t';
288 OS << " Predecessors according to CFG:";
289 for (const_pred_iterator PI = pred_begin(), E = pred_end(); PI != E; ++PI)
290 OS << " BB#" << (*PI)->getNumber();
294 for (const_instr_iterator I = instr_begin(); I != instr_end(); ++I) {
296 if (Indexes->hasIndex(I))
297 OS << Indexes->getInstructionIndex(I);
301 if (I->isInsideBundle())
306 // Print the successors of this block according to the CFG.
308 if (Indexes) OS << '\t';
309 OS << " Successors according to CFG:";
310 for (const_succ_iterator SI = succ_begin(), E = succ_end(); SI != E; ++SI) {
311 OS << " BB#" << (*SI)->getNumber();
312 if (!Weights.empty())
313 OS << '(' << *getWeightIterator(SI) << ')';
319 void MachineBasicBlock::printAsOperand(raw_ostream &OS,
320 bool /*PrintType*/) const {
321 OS << "BB#" << getNumber();
324 void MachineBasicBlock::removeLiveIn(MCPhysReg Reg) {
325 LiveInVector::iterator I = std::find(LiveIns.begin(), LiveIns.end(), Reg);
326 if (I != LiveIns.end())
330 bool MachineBasicBlock::isLiveIn(MCPhysReg Reg) const {
331 livein_iterator I = std::find(livein_begin(), livein_end(), Reg);
332 return I != livein_end();
336 MachineBasicBlock::addLiveIn(MCPhysReg PhysReg, const TargetRegisterClass *RC) {
337 assert(getParent() && "MBB must be inserted in function");
338 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg) && "Expected physreg");
339 assert(RC && "Register class is required");
340 assert((isEHPad() || this == &getParent()->front()) &&
341 "Only the entry block and landing pads can have physreg live ins");
343 bool LiveIn = isLiveIn(PhysReg);
344 iterator I = SkipPHIsAndLabels(begin()), E = end();
345 MachineRegisterInfo &MRI = getParent()->getRegInfo();
346 const TargetInstrInfo &TII = *getParent()->getSubtarget().getInstrInfo();
348 // Look for an existing copy.
350 for (;I != E && I->isCopy(); ++I)
351 if (I->getOperand(1).getReg() == PhysReg) {
352 unsigned VirtReg = I->getOperand(0).getReg();
353 if (!MRI.constrainRegClass(VirtReg, RC))
354 llvm_unreachable("Incompatible live-in register class.");
358 // No luck, create a virtual register.
359 unsigned VirtReg = MRI.createVirtualRegister(RC);
360 BuildMI(*this, I, DebugLoc(), TII.get(TargetOpcode::COPY), VirtReg)
361 .addReg(PhysReg, RegState::Kill);
367 void MachineBasicBlock::moveBefore(MachineBasicBlock *NewAfter) {
368 getParent()->splice(NewAfter, this);
371 void MachineBasicBlock::moveAfter(MachineBasicBlock *NewBefore) {
372 MachineFunction::iterator BBI = NewBefore;
373 getParent()->splice(++BBI, this);
376 void MachineBasicBlock::updateTerminator() {
377 const TargetInstrInfo *TII = getParent()->getSubtarget().getInstrInfo();
378 // A block with no successors has no concerns with fall-through edges.
379 if (this->succ_empty()) return;
381 MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
382 SmallVector<MachineOperand, 4> Cond;
383 DebugLoc dl; // FIXME: this is nowhere
384 bool B = TII->AnalyzeBranch(*this, TBB, FBB, Cond);
386 assert(!B && "UpdateTerminators requires analyzable predecessors!");
389 // The block has an unconditional branch. If its successor is now
390 // its layout successor, delete the branch.
391 if (isLayoutSuccessor(TBB))
392 TII->RemoveBranch(*this);
394 // The block has an unconditional fallthrough. If its successor is not
395 // its layout successor, insert a branch. First we have to locate the
396 // only non-landing-pad successor, as that is the fallthrough block.
397 for (succ_iterator SI = succ_begin(), SE = succ_end(); SI != SE; ++SI) {
398 if ((*SI)->isEHPad())
400 assert(!TBB && "Found more than one non-landing-pad successor!");
404 // If there is no non-landing-pad successor, the block has no
405 // fall-through edges to be concerned with.
409 // Finally update the unconditional successor to be reached via a branch
410 // if it would not be reached by fallthrough.
411 if (!isLayoutSuccessor(TBB))
412 TII->InsertBranch(*this, TBB, nullptr, Cond, dl);
416 // The block has a non-fallthrough conditional branch. If one of its
417 // successors is its layout successor, rewrite it to a fallthrough
418 // conditional branch.
419 if (isLayoutSuccessor(TBB)) {
420 if (TII->ReverseBranchCondition(Cond))
422 TII->RemoveBranch(*this);
423 TII->InsertBranch(*this, FBB, nullptr, Cond, dl);
424 } else if (isLayoutSuccessor(FBB)) {
425 TII->RemoveBranch(*this);
426 TII->InsertBranch(*this, TBB, nullptr, Cond, dl);
429 // Walk through the successors and find the successor which is not
430 // a landing pad and is not the conditional branch destination (in TBB)
431 // as the fallthrough successor.
432 MachineBasicBlock *FallthroughBB = nullptr;
433 for (succ_iterator SI = succ_begin(), SE = succ_end(); SI != SE; ++SI) {
434 if ((*SI)->isEHPad() || *SI == TBB)
436 assert(!FallthroughBB && "Found more than one fallthrough successor.");
439 if (!FallthroughBB && canFallThrough()) {
440 // We fallthrough to the same basic block as the conditional jump
441 // targets. Remove the conditional jump, leaving unconditional
443 // FIXME: This does not seem like a reasonable pattern to support, but
444 // it has been seen in the wild coming out of degenerate ARM test cases.
445 TII->RemoveBranch(*this);
447 // Finally update the unconditional successor to be reached via a branch
448 // if it would not be reached by fallthrough.
449 if (!isLayoutSuccessor(TBB))
450 TII->InsertBranch(*this, TBB, nullptr, Cond, dl);
454 // The block has a fallthrough conditional branch.
455 if (isLayoutSuccessor(TBB)) {
456 if (TII->ReverseBranchCondition(Cond)) {
457 // We can't reverse the condition, add an unconditional branch.
459 TII->InsertBranch(*this, FallthroughBB, nullptr, Cond, dl);
462 TII->RemoveBranch(*this);
463 TII->InsertBranch(*this, FallthroughBB, nullptr, Cond, dl);
464 } else if (!isLayoutSuccessor(FallthroughBB)) {
465 TII->RemoveBranch(*this);
466 TII->InsertBranch(*this, TBB, FallthroughBB, Cond, dl);
472 void MachineBasicBlock::addSuccessor(MachineBasicBlock *succ, uint32_t weight) {
474 // If we see non-zero value for the first time it means we actually use Weight
475 // list, so we fill all Weights with 0's.
476 if (weight != 0 && Weights.empty())
477 Weights.resize(Successors.size());
479 if (weight != 0 || !Weights.empty())
480 Weights.push_back(weight);
482 Successors.push_back(succ);
483 succ->addPredecessor(this);
486 void MachineBasicBlock::removeSuccessor(MachineBasicBlock *succ) {
487 succ->removePredecessor(this);
488 succ_iterator I = std::find(Successors.begin(), Successors.end(), succ);
489 assert(I != Successors.end() && "Not a current successor!");
491 // If Weight list is empty it means we don't use it (disabled optimization).
492 if (!Weights.empty()) {
493 weight_iterator WI = getWeightIterator(I);
500 MachineBasicBlock::succ_iterator
501 MachineBasicBlock::removeSuccessor(succ_iterator I) {
502 assert(I != Successors.end() && "Not a current successor!");
504 // If Weight list is empty it means we don't use it (disabled optimization).
505 if (!Weights.empty()) {
506 weight_iterator WI = getWeightIterator(I);
510 (*I)->removePredecessor(this);
511 return Successors.erase(I);
514 void MachineBasicBlock::replaceSuccessor(MachineBasicBlock *Old,
515 MachineBasicBlock *New) {
519 succ_iterator E = succ_end();
520 succ_iterator NewI = E;
521 succ_iterator OldI = E;
522 for (succ_iterator I = succ_begin(); I != E; ++I) {
534 assert(OldI != E && "Old is not a successor of this block");
535 Old->removePredecessor(this);
537 // If New isn't already a successor, let it take Old's place.
539 New->addPredecessor(this);
544 // New is already a successor.
545 // Update its weight instead of adding a duplicate edge.
546 if (!Weights.empty()) {
547 weight_iterator OldWI = getWeightIterator(OldI);
548 *getWeightIterator(NewI) += *OldWI;
549 Weights.erase(OldWI);
551 Successors.erase(OldI);
554 void MachineBasicBlock::addPredecessor(MachineBasicBlock *pred) {
555 Predecessors.push_back(pred);
558 void MachineBasicBlock::removePredecessor(MachineBasicBlock *pred) {
559 pred_iterator I = std::find(Predecessors.begin(), Predecessors.end(), pred);
560 assert(I != Predecessors.end() && "Pred is not a predecessor of this block!");
561 Predecessors.erase(I);
564 void MachineBasicBlock::transferSuccessors(MachineBasicBlock *fromMBB) {
568 while (!fromMBB->succ_empty()) {
569 MachineBasicBlock *Succ = *fromMBB->succ_begin();
572 // If Weight list is empty it means we don't use it (disabled optimization).
573 if (!fromMBB->Weights.empty())
574 Weight = *fromMBB->Weights.begin();
576 addSuccessor(Succ, Weight);
577 fromMBB->removeSuccessor(Succ);
582 MachineBasicBlock::transferSuccessorsAndUpdatePHIs(MachineBasicBlock *fromMBB) {
586 while (!fromMBB->succ_empty()) {
587 MachineBasicBlock *Succ = *fromMBB->succ_begin();
589 if (!fromMBB->Weights.empty())
590 Weight = *fromMBB->Weights.begin();
591 addSuccessor(Succ, Weight);
592 fromMBB->removeSuccessor(Succ);
594 // Fix up any PHI nodes in the successor.
595 for (MachineBasicBlock::instr_iterator MI = Succ->instr_begin(),
596 ME = Succ->instr_end(); MI != ME && MI->isPHI(); ++MI)
597 for (unsigned i = 2, e = MI->getNumOperands()+1; i != e; i += 2) {
598 MachineOperand &MO = MI->getOperand(i);
599 if (MO.getMBB() == fromMBB)
605 bool MachineBasicBlock::isPredecessor(const MachineBasicBlock *MBB) const {
606 return std::find(pred_begin(), pred_end(), MBB) != pred_end();
609 bool MachineBasicBlock::isSuccessor(const MachineBasicBlock *MBB) const {
610 return std::find(succ_begin(), succ_end(), MBB) != succ_end();
613 bool MachineBasicBlock::isLayoutSuccessor(const MachineBasicBlock *MBB) const {
614 MachineFunction::const_iterator I(this);
615 return std::next(I) == MachineFunction::const_iterator(MBB);
618 bool MachineBasicBlock::canFallThrough() {
619 MachineFunction::iterator Fallthrough = this;
621 // If FallthroughBlock is off the end of the function, it can't fall through.
622 if (Fallthrough == getParent()->end())
625 // If FallthroughBlock isn't a successor, no fallthrough is possible.
626 if (!isSuccessor(Fallthrough))
629 // Analyze the branches, if any, at the end of the block.
630 MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
631 SmallVector<MachineOperand, 4> Cond;
632 const TargetInstrInfo *TII = getParent()->getSubtarget().getInstrInfo();
633 if (TII->AnalyzeBranch(*this, TBB, FBB, Cond)) {
634 // If we couldn't analyze the branch, examine the last instruction.
635 // If the block doesn't end in a known control barrier, assume fallthrough
636 // is possible. The isPredicated check is needed because this code can be
637 // called during IfConversion, where an instruction which is normally a
638 // Barrier is predicated and thus no longer an actual control barrier.
639 return empty() || !back().isBarrier() || TII->isPredicated(&back());
642 // If there is no branch, control always falls through.
643 if (!TBB) return true;
645 // If there is some explicit branch to the fallthrough block, it can obviously
646 // reach, even though the branch should get folded to fall through implicitly.
647 if (MachineFunction::iterator(TBB) == Fallthrough ||
648 MachineFunction::iterator(FBB) == Fallthrough)
651 // If it's an unconditional branch to some block not the fall through, it
652 // doesn't fall through.
653 if (Cond.empty()) return false;
655 // Otherwise, if it is conditional and has no explicit false block, it falls
657 return FBB == nullptr;
661 MachineBasicBlock::SplitCriticalEdge(MachineBasicBlock *Succ, Pass *P) {
662 // Splitting the critical edge to a landing pad block is non-trivial. Don't do
663 // it in this generic function.
667 MachineFunction *MF = getParent();
668 DebugLoc dl; // FIXME: this is nowhere
670 // Performance might be harmed on HW that implements branching using exec mask
671 // where both sides of the branches are always executed.
672 if (MF->getTarget().requiresStructuredCFG())
675 // We may need to update this's terminator, but we can't do that if
676 // AnalyzeBranch fails. If this uses a jump table, we won't touch it.
677 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
678 MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
679 SmallVector<MachineOperand, 4> Cond;
680 if (TII->AnalyzeBranch(*this, TBB, FBB, Cond))
683 // Avoid bugpoint weirdness: A block may end with a conditional branch but
684 // jumps to the same MBB is either case. We have duplicate CFG edges in that
685 // case that we can't handle. Since this never happens in properly optimized
686 // code, just skip those edges.
687 if (TBB && TBB == FBB) {
688 DEBUG(dbgs() << "Won't split critical edge after degenerate BB#"
689 << getNumber() << '\n');
693 MachineBasicBlock *NMBB = MF->CreateMachineBasicBlock();
694 MF->insert(std::next(MachineFunction::iterator(this)), NMBB);
695 DEBUG(dbgs() << "Splitting critical edge:"
696 " BB#" << getNumber()
697 << " -- BB#" << NMBB->getNumber()
698 << " -- BB#" << Succ->getNumber() << '\n');
700 LiveIntervals *LIS = P->getAnalysisIfAvailable<LiveIntervals>();
701 SlotIndexes *Indexes = P->getAnalysisIfAvailable<SlotIndexes>();
703 LIS->insertMBBInMaps(NMBB);
705 Indexes->insertMBBInMaps(NMBB);
707 // On some targets like Mips, branches may kill virtual registers. Make sure
708 // that LiveVariables is properly updated after updateTerminator replaces the
710 LiveVariables *LV = P->getAnalysisIfAvailable<LiveVariables>();
712 // Collect a list of virtual registers killed by the terminators.
713 SmallVector<unsigned, 4> KilledRegs;
715 for (instr_iterator I = getFirstInstrTerminator(), E = instr_end();
717 MachineInstr *MI = I;
718 for (MachineInstr::mop_iterator OI = MI->operands_begin(),
719 OE = MI->operands_end(); OI != OE; ++OI) {
720 if (!OI->isReg() || OI->getReg() == 0 ||
721 !OI->isUse() || !OI->isKill() || OI->isUndef())
723 unsigned Reg = OI->getReg();
724 if (TargetRegisterInfo::isPhysicalRegister(Reg) ||
725 LV->getVarInfo(Reg).removeKill(MI)) {
726 KilledRegs.push_back(Reg);
727 DEBUG(dbgs() << "Removing terminator kill: " << *MI);
728 OI->setIsKill(false);
733 SmallVector<unsigned, 4> UsedRegs;
735 for (instr_iterator I = getFirstInstrTerminator(), E = instr_end();
737 MachineInstr *MI = I;
739 for (MachineInstr::mop_iterator OI = MI->operands_begin(),
740 OE = MI->operands_end(); OI != OE; ++OI) {
741 if (!OI->isReg() || OI->getReg() == 0)
744 unsigned Reg = OI->getReg();
745 if (std::find(UsedRegs.begin(), UsedRegs.end(), Reg) == UsedRegs.end())
746 UsedRegs.push_back(Reg);
751 ReplaceUsesOfBlockWith(Succ, NMBB);
753 // If updateTerminator() removes instructions, we need to remove them from
755 SmallVector<MachineInstr*, 4> Terminators;
757 for (instr_iterator I = getFirstInstrTerminator(), E = instr_end();
759 Terminators.push_back(I);
765 SmallVector<MachineInstr*, 4> NewTerminators;
766 for (instr_iterator I = getFirstInstrTerminator(), E = instr_end();
768 NewTerminators.push_back(I);
770 for (SmallVectorImpl<MachineInstr*>::iterator I = Terminators.begin(),
771 E = Terminators.end(); I != E; ++I) {
772 if (std::find(NewTerminators.begin(), NewTerminators.end(), *I) ==
773 NewTerminators.end())
774 Indexes->removeMachineInstrFromMaps(*I);
778 // Insert unconditional "jump Succ" instruction in NMBB if necessary.
779 NMBB->addSuccessor(Succ);
780 if (!NMBB->isLayoutSuccessor(Succ)) {
782 MF->getSubtarget().getInstrInfo()->InsertBranch(*NMBB, Succ, nullptr, Cond,
786 for (instr_iterator I = NMBB->instr_begin(), E = NMBB->instr_end();
788 // Some instructions may have been moved to NMBB by updateTerminator(),
789 // so we first remove any instruction that already has an index.
790 if (Indexes->hasIndex(I))
791 Indexes->removeMachineInstrFromMaps(I);
792 Indexes->insertMachineInstrInMaps(I);
797 // Fix PHI nodes in Succ so they refer to NMBB instead of this
798 for (MachineBasicBlock::instr_iterator
799 i = Succ->instr_begin(),e = Succ->instr_end();
800 i != e && i->isPHI(); ++i)
801 for (unsigned ni = 1, ne = i->getNumOperands(); ni != ne; ni += 2)
802 if (i->getOperand(ni+1).getMBB() == this)
803 i->getOperand(ni+1).setMBB(NMBB);
805 // Inherit live-ins from the successor
806 for (unsigned LI : Succ->liveins())
809 // Update LiveVariables.
810 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
812 // Restore kills of virtual registers that were killed by the terminators.
813 while (!KilledRegs.empty()) {
814 unsigned Reg = KilledRegs.pop_back_val();
815 for (instr_iterator I = instr_end(), E = instr_begin(); I != E;) {
816 if (!(--I)->addRegisterKilled(Reg, TRI, /* addIfNotFound= */ false))
818 if (TargetRegisterInfo::isVirtualRegister(Reg))
819 LV->getVarInfo(Reg).Kills.push_back(I);
820 DEBUG(dbgs() << "Restored terminator kill: " << *I);
824 // Update relevant live-through information.
825 LV->addNewBlock(NMBB, this, Succ);
829 // After splitting the edge and updating SlotIndexes, live intervals may be
830 // in one of two situations, depending on whether this block was the last in
831 // the function. If the original block was the last in the function, all
832 // live intervals will end prior to the beginning of the new split block. If
833 // the original block was not at the end of the function, all live intervals
834 // will extend to the end of the new split block.
837 std::next(MachineFunction::iterator(NMBB)) == getParent()->end();
839 SlotIndex StartIndex = Indexes->getMBBEndIdx(this);
840 SlotIndex PrevIndex = StartIndex.getPrevSlot();
841 SlotIndex EndIndex = Indexes->getMBBEndIdx(NMBB);
843 // Find the registers used from NMBB in PHIs in Succ.
844 SmallSet<unsigned, 8> PHISrcRegs;
845 for (MachineBasicBlock::instr_iterator
846 I = Succ->instr_begin(), E = Succ->instr_end();
847 I != E && I->isPHI(); ++I) {
848 for (unsigned ni = 1, ne = I->getNumOperands(); ni != ne; ni += 2) {
849 if (I->getOperand(ni+1).getMBB() == NMBB) {
850 MachineOperand &MO = I->getOperand(ni);
851 unsigned Reg = MO.getReg();
852 PHISrcRegs.insert(Reg);
856 LiveInterval &LI = LIS->getInterval(Reg);
857 VNInfo *VNI = LI.getVNInfoAt(PrevIndex);
859 "PHI sources should be live out of their predecessors.");
860 LI.addSegment(LiveInterval::Segment(StartIndex, EndIndex, VNI));
865 MachineRegisterInfo *MRI = &getParent()->getRegInfo();
866 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
867 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
868 if (PHISrcRegs.count(Reg) || !LIS->hasInterval(Reg))
871 LiveInterval &LI = LIS->getInterval(Reg);
872 if (!LI.liveAt(PrevIndex))
875 bool isLiveOut = LI.liveAt(LIS->getMBBStartIdx(Succ));
876 if (isLiveOut && isLastMBB) {
877 VNInfo *VNI = LI.getVNInfoAt(PrevIndex);
878 assert(VNI && "LiveInterval should have VNInfo where it is live.");
879 LI.addSegment(LiveInterval::Segment(StartIndex, EndIndex, VNI));
880 } else if (!isLiveOut && !isLastMBB) {
881 LI.removeSegment(StartIndex, EndIndex);
885 // Update all intervals for registers whose uses may have been modified by
886 // updateTerminator().
887 LIS->repairIntervalsInRange(this, getFirstTerminator(), end(), UsedRegs);
890 if (MachineDominatorTree *MDT =
891 P->getAnalysisIfAvailable<MachineDominatorTree>())
892 MDT->recordSplitCriticalEdge(this, Succ, NMBB);
894 if (MachineLoopInfo *MLI = P->getAnalysisIfAvailable<MachineLoopInfo>())
895 if (MachineLoop *TIL = MLI->getLoopFor(this)) {
896 // If one or the other blocks were not in a loop, the new block is not
897 // either, and thus LI doesn't need to be updated.
898 if (MachineLoop *DestLoop = MLI->getLoopFor(Succ)) {
899 if (TIL == DestLoop) {
900 // Both in the same loop, the NMBB joins loop.
901 DestLoop->addBasicBlockToLoop(NMBB, MLI->getBase());
902 } else if (TIL->contains(DestLoop)) {
903 // Edge from an outer loop to an inner loop. Add to the outer loop.
904 TIL->addBasicBlockToLoop(NMBB, MLI->getBase());
905 } else if (DestLoop->contains(TIL)) {
906 // Edge from an inner loop to an outer loop. Add to the outer loop.
907 DestLoop->addBasicBlockToLoop(NMBB, MLI->getBase());
909 // Edge from two loops with no containment relation. Because these
910 // are natural loops, we know that the destination block must be the
911 // header of its loop (adding a branch into a loop elsewhere would
912 // create an irreducible loop).
913 assert(DestLoop->getHeader() == Succ &&
914 "Should not create irreducible loops!");
915 if (MachineLoop *P = DestLoop->getParentLoop())
916 P->addBasicBlockToLoop(NMBB, MLI->getBase());
924 /// Prepare MI to be removed from its bundle. This fixes bundle flags on MI's
925 /// neighboring instructions so the bundle won't be broken by removing MI.
926 static void unbundleSingleMI(MachineInstr *MI) {
927 // Removing the first instruction in a bundle.
928 if (MI->isBundledWithSucc() && !MI->isBundledWithPred())
929 MI->unbundleFromSucc();
930 // Removing the last instruction in a bundle.
931 if (MI->isBundledWithPred() && !MI->isBundledWithSucc())
932 MI->unbundleFromPred();
933 // If MI is not bundled, or if it is internal to a bundle, the neighbor flags
937 MachineBasicBlock::instr_iterator
938 MachineBasicBlock::erase(MachineBasicBlock::instr_iterator I) {
940 return Insts.erase(I);
943 MachineInstr *MachineBasicBlock::remove_instr(MachineInstr *MI) {
944 unbundleSingleMI(MI);
945 MI->clearFlag(MachineInstr::BundledPred);
946 MI->clearFlag(MachineInstr::BundledSucc);
947 return Insts.remove(MI);
950 MachineBasicBlock::instr_iterator
951 MachineBasicBlock::insert(instr_iterator I, MachineInstr *MI) {
952 assert(!MI->isBundledWithPred() && !MI->isBundledWithSucc() &&
953 "Cannot insert instruction with bundle flags");
954 // Set the bundle flags when inserting inside a bundle.
955 if (I != instr_end() && I->isBundledWithPred()) {
956 MI->setFlag(MachineInstr::BundledPred);
957 MI->setFlag(MachineInstr::BundledSucc);
959 return Insts.insert(I, MI);
962 /// This method unlinks 'this' from the containing function, and returns it, but
963 /// does not delete it.
964 MachineBasicBlock *MachineBasicBlock::removeFromParent() {
965 assert(getParent() && "Not embedded in a function!");
966 getParent()->remove(this);
970 /// This method unlinks 'this' from the containing function, and deletes it.
971 void MachineBasicBlock::eraseFromParent() {
972 assert(getParent() && "Not embedded in a function!");
973 getParent()->erase(this);
976 /// Given a machine basic block that branched to 'Old', change the code and CFG
977 /// so that it branches to 'New' instead.
978 void MachineBasicBlock::ReplaceUsesOfBlockWith(MachineBasicBlock *Old,
979 MachineBasicBlock *New) {
980 assert(Old != New && "Cannot replace self with self!");
982 MachineBasicBlock::instr_iterator I = instr_end();
983 while (I != instr_begin()) {
985 if (!I->isTerminator()) break;
987 // Scan the operands of this machine instruction, replacing any uses of Old
989 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i)
990 if (I->getOperand(i).isMBB() &&
991 I->getOperand(i).getMBB() == Old)
992 I->getOperand(i).setMBB(New);
995 // Update the successor information.
996 replaceSuccessor(Old, New);
999 /// Various pieces of code can cause excess edges in the CFG to be inserted. If
1000 /// we have proven that MBB can only branch to DestA and DestB, remove any other
1001 /// MBB successors from the CFG. DestA and DestB can be null.
1003 /// Besides DestA and DestB, retain other edges leading to LandingPads
1004 /// (currently there can be only one; we don't check or require that here).
1005 /// Note it is possible that DestA and/or DestB are LandingPads.
1006 bool MachineBasicBlock::CorrectExtraCFGEdges(MachineBasicBlock *DestA,
1007 MachineBasicBlock *DestB,
1009 // The values of DestA and DestB frequently come from a call to the
1010 // 'TargetInstrInfo::AnalyzeBranch' method. We take our meaning of the initial
1011 // values from there.
1013 // 1. If both DestA and DestB are null, then the block ends with no branches
1014 // (it falls through to its successor).
1015 // 2. If DestA is set, DestB is null, and isCond is false, then the block ends
1016 // with only an unconditional branch.
1017 // 3. If DestA is set, DestB is null, and isCond is true, then the block ends
1018 // with a conditional branch that falls through to a successor (DestB).
1019 // 4. If DestA and DestB is set and isCond is true, then the block ends with a
1020 // conditional branch followed by an unconditional branch. DestA is the
1021 // 'true' destination and DestB is the 'false' destination.
1023 bool Changed = false;
1025 MachineFunction::iterator FallThru =
1026 std::next(MachineFunction::iterator(this));
1028 if (!DestA && !DestB) {
1029 // Block falls through to successor.
1032 } else if (DestA && !DestB) {
1034 // Block ends in conditional jump that falls through to successor.
1037 assert(DestA && DestB && isCond &&
1038 "CFG in a bad state. Cannot correct CFG edges");
1041 // Remove superfluous edges. I.e., those which aren't destinations of this
1042 // basic block, duplicate edges, or landing pads.
1043 SmallPtrSet<const MachineBasicBlock*, 8> SeenMBBs;
1044 MachineBasicBlock::succ_iterator SI = succ_begin();
1045 while (SI != succ_end()) {
1046 const MachineBasicBlock *MBB = *SI;
1047 if (!SeenMBBs.insert(MBB).second ||
1048 (MBB != DestA && MBB != DestB && !MBB->isEHPad())) {
1049 // This is a superfluous edge, remove it.
1050 SI = removeSuccessor(SI);
1060 /// Find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE
1061 /// instructions. Return UnknownLoc if there is none.
1063 MachineBasicBlock::findDebugLoc(instr_iterator MBBI) {
1065 instr_iterator E = instr_end();
1069 // Skip debug declarations, we don't want a DebugLoc from them.
1070 while (MBBI != E && MBBI->isDebugValue())
1073 DL = MBBI->getDebugLoc();
1077 /// Return weight of the edge from this block to MBB.
1078 uint32_t MachineBasicBlock::getSuccWeight(const_succ_iterator Succ) const {
1079 if (Weights.empty())
1082 return *getWeightIterator(Succ);
1085 /// Set successor weight of a given iterator.
1086 void MachineBasicBlock::setSuccWeight(succ_iterator I, uint32_t weight) {
1087 if (Weights.empty())
1089 *getWeightIterator(I) = weight;
1092 /// Return wight iterator corresonding to the I successor iterator.
1093 MachineBasicBlock::weight_iterator MachineBasicBlock::
1094 getWeightIterator(MachineBasicBlock::succ_iterator I) {
1095 assert(Weights.size() == Successors.size() && "Async weight list!");
1096 size_t index = std::distance(Successors.begin(), I);
1097 assert(index < Weights.size() && "Not a current successor!");
1098 return Weights.begin() + index;
1101 /// Return wight iterator corresonding to the I successor iterator.
1102 MachineBasicBlock::const_weight_iterator MachineBasicBlock::
1103 getWeightIterator(MachineBasicBlock::const_succ_iterator I) const {
1104 assert(Weights.size() == Successors.size() && "Async weight list!");
1105 const size_t index = std::distance(Successors.begin(), I);
1106 assert(index < Weights.size() && "Not a current successor!");
1107 return Weights.begin() + index;
1110 /// Return whether (physical) register "Reg" has been <def>ined and not <kill>ed
1111 /// as of just before "MI".
1113 /// Search is localised to a neighborhood of
1114 /// Neighborhood instructions before (searching for defs or kills) and N
1115 /// instructions after (searching just for defs) MI.
1116 MachineBasicBlock::LivenessQueryResult
1117 MachineBasicBlock::computeRegisterLiveness(const TargetRegisterInfo *TRI,
1118 unsigned Reg, const_iterator Before,
1119 unsigned Neighborhood) const {
1120 unsigned N = Neighborhood;
1122 // Start by searching backwards from Before, looking for kills, reads or defs.
1123 const_iterator I(Before);
1124 // If this is the first insn in the block, don't search backwards.
1129 MachineOperandIteratorBase::PhysRegInfo Analysis =
1130 ConstMIOperands(I).analyzePhysReg(Reg, TRI);
1132 if (Analysis.Defines)
1133 // Outputs happen after inputs so they take precedence if both are
1135 return Analysis.DefinesDead ? LQR_Dead : LQR_Live;
1137 if (Analysis.Kills || Analysis.Clobbers)
1138 // Register killed, so isn't live.
1141 else if (Analysis.ReadsOverlap)
1142 // Defined or read without a previous kill - live.
1143 return Analysis.Reads ? LQR_Live : LQR_OverlappingLive;
1145 } while (I != begin() && --N > 0);
1148 // Did we get to the start of the block?
1150 // If so, the register's state is definitely defined by the live-in state.
1151 for (MCRegAliasIterator RAI(Reg, TRI, /*IncludeSelf=*/true);
1152 RAI.isValid(); ++RAI) {
1154 return (*RAI == Reg) ? LQR_Live : LQR_OverlappingLive;
1162 // Try searching forwards from Before, looking for reads or defs.
1163 I = const_iterator(Before);
1164 // If this is the last insn in the block, don't search forwards.
1166 for (++I; I != end() && N > 0; ++I, --N) {
1167 MachineOperandIteratorBase::PhysRegInfo Analysis =
1168 ConstMIOperands(I).analyzePhysReg(Reg, TRI);
1170 if (Analysis.ReadsOverlap)
1171 // Used, therefore must have been live.
1172 return (Analysis.Reads) ?
1173 LQR_Live : LQR_OverlappingLive;
1175 else if (Analysis.Clobbers || Analysis.Defines)
1176 // Defined (but not read) therefore cannot have been live.
1181 // At this point we have no idea of the liveness of the register.