1 //===-- llvm/CodeGen/MachineBasicBlock.cpp ----------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Collect the sequence of machine instructions for a basic block.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/MachineBasicBlock.h"
15 #include "llvm/ADT/SmallPtrSet.h"
16 #include "llvm/ADT/SmallString.h"
17 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
18 #include "llvm/CodeGen/LiveVariables.h"
19 #include "llvm/CodeGen/MachineDominators.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineLoopInfo.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/SlotIndexes.h"
25 #include "llvm/IR/BasicBlock.h"
26 #include "llvm/IR/DataLayout.h"
27 #include "llvm/IR/ModuleSlotTracker.h"
28 #include "llvm/MC/MCAsmInfo.h"
29 #include "llvm/MC/MCContext.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/raw_ostream.h"
32 #include "llvm/Target/TargetInstrInfo.h"
33 #include "llvm/Target/TargetMachine.h"
34 #include "llvm/Target/TargetRegisterInfo.h"
35 #include "llvm/Target/TargetSubtargetInfo.h"
39 #define DEBUG_TYPE "codegen"
41 MachineBasicBlock::MachineBasicBlock(MachineFunction &MF, const BasicBlock *B)
42 : BB(B), Number(-1), xParent(&MF) {
46 MachineBasicBlock::~MachineBasicBlock() {
49 /// Return the MCSymbol for this basic block.
50 MCSymbol *MachineBasicBlock::getSymbol() const {
51 if (!CachedMCSymbol) {
52 const MachineFunction *MF = getParent();
53 MCContext &Ctx = MF->getContext();
54 const char *Prefix = Ctx.getAsmInfo()->getPrivateLabelPrefix();
55 CachedMCSymbol = Ctx.getOrCreateSymbol(Twine(Prefix) + "BB" +
56 Twine(MF->getFunctionNumber()) +
57 "_" + Twine(getNumber()));
60 return CachedMCSymbol;
64 raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineBasicBlock &MBB) {
69 /// When an MBB is added to an MF, we need to update the parent pointer of the
70 /// MBB, the MBB numbering, and any instructions in the MBB to be on the right
71 /// operand list for registers.
73 /// MBBs start out as #-1. When a MBB is added to a MachineFunction, it
74 /// gets the next available unique MBB number. If it is removed from a
75 /// MachineFunction, it goes back to being #-1.
76 void ilist_traits<MachineBasicBlock>::addNodeToList(MachineBasicBlock *N) {
77 MachineFunction &MF = *N->getParent();
78 N->Number = MF.addToMBBNumbering(N);
80 // Make sure the instructions have their operands in the reginfo lists.
81 MachineRegisterInfo &RegInfo = MF.getRegInfo();
82 for (MachineBasicBlock::instr_iterator
83 I = N->instr_begin(), E = N->instr_end(); I != E; ++I)
84 I->AddRegOperandsToUseLists(RegInfo);
87 void ilist_traits<MachineBasicBlock>::removeNodeFromList(MachineBasicBlock *N) {
88 N->getParent()->removeFromMBBNumbering(N->Number);
92 /// When we add an instruction to a basic block list, we update its parent
93 /// pointer and add its operands from reg use/def lists if appropriate.
94 void ilist_traits<MachineInstr>::addNodeToList(MachineInstr *N) {
95 assert(!N->getParent() && "machine instruction already in a basic block");
98 // Add the instruction's register operands to their corresponding
100 MachineFunction *MF = Parent->getParent();
101 N->AddRegOperandsToUseLists(MF->getRegInfo());
104 /// When we remove an instruction from a basic block list, we update its parent
105 /// pointer and remove its operands from reg use/def lists if appropriate.
106 void ilist_traits<MachineInstr>::removeNodeFromList(MachineInstr *N) {
107 assert(N->getParent() && "machine instruction not in a basic block");
109 // Remove from the use/def lists.
110 if (MachineFunction *MF = N->getParent()->getParent())
111 N->RemoveRegOperandsFromUseLists(MF->getRegInfo());
113 N->setParent(nullptr);
116 /// When moving a range of instructions from one MBB list to another, we need to
117 /// update the parent pointers and the use/def lists.
118 void ilist_traits<MachineInstr>::
119 transferNodesFromList(ilist_traits<MachineInstr> &FromList,
120 ilist_iterator<MachineInstr> First,
121 ilist_iterator<MachineInstr> Last) {
122 assert(Parent->getParent() == FromList.Parent->getParent() &&
123 "MachineInstr parent mismatch!");
125 // Splice within the same MBB -> no change.
126 if (Parent == FromList.Parent) return;
128 // If splicing between two blocks within the same function, just update the
130 for (; First != Last; ++First)
131 First->setParent(Parent);
134 void ilist_traits<MachineInstr>::deleteNode(MachineInstr* MI) {
135 assert(!MI->getParent() && "MI is still in a block!");
136 Parent->getParent()->DeleteMachineInstr(MI);
139 MachineBasicBlock::iterator MachineBasicBlock::getFirstNonPHI() {
140 instr_iterator I = instr_begin(), E = instr_end();
141 while (I != E && I->isPHI())
143 assert((I == E || !I->isInsideBundle()) &&
144 "First non-phi MI cannot be inside a bundle!");
148 MachineBasicBlock::iterator
149 MachineBasicBlock::SkipPHIsAndLabels(MachineBasicBlock::iterator I) {
151 while (I != E && (I->isPHI() || I->isPosition() || I->isDebugValue()))
153 // FIXME: This needs to change if we wish to bundle labels / dbg_values
154 // inside the bundle.
155 assert((I == E || !I->isInsideBundle()) &&
156 "First non-phi / non-label instruction is inside a bundle!");
160 MachineBasicBlock::iterator MachineBasicBlock::getFirstTerminator() {
161 iterator B = begin(), E = end(), I = E;
162 while (I != B && ((--I)->isTerminator() || I->isDebugValue()))
164 while (I != E && !I->isTerminator())
169 MachineBasicBlock::instr_iterator MachineBasicBlock::getFirstInstrTerminator() {
170 instr_iterator B = instr_begin(), E = instr_end(), I = E;
171 while (I != B && ((--I)->isTerminator() || I->isDebugValue()))
173 while (I != E && !I->isTerminator())
178 MachineBasicBlock::iterator MachineBasicBlock::getFirstNonDebugInstr() {
179 // Skip over begin-of-block dbg_value instructions.
180 iterator I = begin(), E = end();
181 while (I != E && I->isDebugValue())
186 MachineBasicBlock::iterator MachineBasicBlock::getLastNonDebugInstr() {
187 // Skip over end-of-block dbg_value instructions.
188 instr_iterator B = instr_begin(), I = instr_end();
191 // Return instruction that starts a bundle.
192 if (I->isDebugValue() || I->isInsideBundle())
196 // The block is all debug values.
200 const MachineBasicBlock *MachineBasicBlock::getLandingPadSuccessor() const {
201 // A block with a landing pad successor only has one other successor.
204 for (const_succ_iterator I = succ_begin(), E = succ_end(); I != E; ++I)
210 bool MachineBasicBlock::hasEHPadSuccessor() const {
211 for (const_succ_iterator I = succ_begin(), E = succ_end(); I != E; ++I)
217 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
218 void MachineBasicBlock::dump() const {
223 StringRef MachineBasicBlock::getName() const {
224 if (const BasicBlock *LBB = getBasicBlock())
225 return LBB->getName();
230 /// Return a hopefully unique identifier for this block.
231 std::string MachineBasicBlock::getFullName() const {
234 Name = (getParent()->getName() + ":").str();
236 Name += getBasicBlock()->getName();
238 Name += ("BB" + Twine(getNumber())).str();
242 void MachineBasicBlock::print(raw_ostream &OS, SlotIndexes *Indexes) const {
243 const MachineFunction *MF = getParent();
245 OS << "Can't print out MachineBasicBlock because parent MachineFunction"
249 const Function *F = MF->getFunction();
250 const Module *M = F ? F->getParent() : nullptr;
251 ModuleSlotTracker MST(M);
252 print(OS, MST, Indexes);
255 void MachineBasicBlock::print(raw_ostream &OS, ModuleSlotTracker &MST,
256 SlotIndexes *Indexes) const {
257 const MachineFunction *MF = getParent();
259 OS << "Can't print out MachineBasicBlock because parent MachineFunction"
265 OS << Indexes->getMBBStartIdx(this) << '\t';
267 OS << "BB#" << getNumber() << ": ";
269 const char *Comma = "";
270 if (const BasicBlock *LBB = getBasicBlock()) {
271 OS << Comma << "derived from LLVM BB ";
272 LBB->printAsOperand(OS, /*PrintType=*/false, MST);
275 if (isEHPad()) { OS << Comma << "EH LANDING PAD"; Comma = ", "; }
276 if (hasAddressTaken()) { OS << Comma << "ADDRESS TAKEN"; Comma = ", "; }
278 OS << Comma << "Align " << Alignment << " (" << (1u << Alignment)
283 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
284 if (!livein_empty()) {
285 if (Indexes) OS << '\t';
287 for (const auto &LI : make_range(livein_begin(), livein_end())) {
288 OS << ' ' << PrintReg(LI.PhysReg, TRI);
289 if (LI.LaneMask != ~0u)
290 OS << ':' << PrintLaneMask(LI.LaneMask);
294 // Print the preds of this block according to the CFG.
296 if (Indexes) OS << '\t';
297 OS << " Predecessors according to CFG:";
298 for (const_pred_iterator PI = pred_begin(), E = pred_end(); PI != E; ++PI)
299 OS << " BB#" << (*PI)->getNumber();
303 for (const_instr_iterator I = instr_begin(); I != instr_end(); ++I) {
305 if (Indexes->hasIndex(&*I))
306 OS << Indexes->getInstructionIndex(&*I);
310 if (I->isInsideBundle())
315 // Print the successors of this block according to the CFG.
317 if (Indexes) OS << '\t';
318 OS << " Successors according to CFG:";
319 for (const_succ_iterator SI = succ_begin(), E = succ_end(); SI != E; ++SI) {
320 OS << " BB#" << (*SI)->getNumber();
321 if (!Weights.empty())
322 OS << '(' << *getWeightIterator(SI) << ')';
328 void MachineBasicBlock::printAsOperand(raw_ostream &OS,
329 bool /*PrintType*/) const {
330 OS << "BB#" << getNumber();
333 void MachineBasicBlock::removeLiveIn(MCPhysReg Reg, LaneBitmask LaneMask) {
334 LiveInVector::iterator I = std::find_if(
335 LiveIns.begin(), LiveIns.end(),
336 [Reg] (const RegisterMaskPair &LI) { return LI.PhysReg == Reg; });
337 if (I == LiveIns.end())
340 I->LaneMask &= ~LaneMask;
341 if (I->LaneMask == 0)
345 bool MachineBasicBlock::isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask) const {
346 livein_iterator I = std::find_if(
347 LiveIns.begin(), LiveIns.end(),
348 [Reg] (const RegisterMaskPair &LI) { return LI.PhysReg == Reg; });
349 return I != livein_end() && (I->LaneMask & LaneMask) != 0;
352 void MachineBasicBlock::sortUniqueLiveIns() {
353 std::sort(LiveIns.begin(), LiveIns.end(),
354 [](const RegisterMaskPair &LI0, const RegisterMaskPair &LI1) {
355 return LI0.PhysReg < LI1.PhysReg;
357 // Liveins are sorted by physreg now we can merge their lanemasks.
358 LiveInVector::const_iterator I = LiveIns.begin();
359 LiveInVector::const_iterator J;
360 LiveInVector::iterator Out = LiveIns.begin();
361 for (; I != LiveIns.end(); ++Out, I = J) {
362 unsigned PhysReg = I->PhysReg;
363 LaneBitmask LaneMask = I->LaneMask;
364 for (J = std::next(I); J != LiveIns.end() && J->PhysReg == PhysReg; ++J)
365 LaneMask |= J->LaneMask;
366 Out->PhysReg = PhysReg;
367 Out->LaneMask = LaneMask;
369 LiveIns.erase(Out, LiveIns.end());
373 MachineBasicBlock::addLiveIn(MCPhysReg PhysReg, const TargetRegisterClass *RC) {
374 assert(getParent() && "MBB must be inserted in function");
375 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg) && "Expected physreg");
376 assert(RC && "Register class is required");
377 assert((isEHPad() || this == &getParent()->front()) &&
378 "Only the entry block and landing pads can have physreg live ins");
380 bool LiveIn = isLiveIn(PhysReg);
381 iterator I = SkipPHIsAndLabels(begin()), E = end();
382 MachineRegisterInfo &MRI = getParent()->getRegInfo();
383 const TargetInstrInfo &TII = *getParent()->getSubtarget().getInstrInfo();
385 // Look for an existing copy.
387 for (;I != E && I->isCopy(); ++I)
388 if (I->getOperand(1).getReg() == PhysReg) {
389 unsigned VirtReg = I->getOperand(0).getReg();
390 if (!MRI.constrainRegClass(VirtReg, RC))
391 llvm_unreachable("Incompatible live-in register class.");
395 // No luck, create a virtual register.
396 unsigned VirtReg = MRI.createVirtualRegister(RC);
397 BuildMI(*this, I, DebugLoc(), TII.get(TargetOpcode::COPY), VirtReg)
398 .addReg(PhysReg, RegState::Kill);
404 void MachineBasicBlock::moveBefore(MachineBasicBlock *NewAfter) {
405 getParent()->splice(NewAfter->getIterator(), getIterator());
408 void MachineBasicBlock::moveAfter(MachineBasicBlock *NewBefore) {
409 getParent()->splice(++NewBefore->getIterator(), getIterator());
412 void MachineBasicBlock::updateTerminator() {
413 const TargetInstrInfo *TII = getParent()->getSubtarget().getInstrInfo();
414 // A block with no successors has no concerns with fall-through edges.
415 if (this->succ_empty()) return;
417 MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
418 SmallVector<MachineOperand, 4> Cond;
419 DebugLoc DL; // FIXME: this is nowhere
420 bool B = TII->AnalyzeBranch(*this, TBB, FBB, Cond);
422 assert(!B && "UpdateTerminators requires analyzable predecessors!");
425 // The block has an unconditional branch. If its successor is now
426 // its layout successor, delete the branch.
427 if (isLayoutSuccessor(TBB))
428 TII->RemoveBranch(*this);
430 // The block has an unconditional fallthrough. If its successor is not
431 // its layout successor, insert a branch. First we have to locate the
432 // only non-landing-pad successor, as that is the fallthrough block.
433 for (succ_iterator SI = succ_begin(), SE = succ_end(); SI != SE; ++SI) {
434 if ((*SI)->isEHPad())
436 assert(!TBB && "Found more than one non-landing-pad successor!");
440 // If there is no non-landing-pad successor, the block has no
441 // fall-through edges to be concerned with.
445 // Finally update the unconditional successor to be reached via a branch
446 // if it would not be reached by fallthrough.
447 if (!isLayoutSuccessor(TBB))
448 TII->InsertBranch(*this, TBB, nullptr, Cond, DL);
452 // The block has a non-fallthrough conditional branch. If one of its
453 // successors is its layout successor, rewrite it to a fallthrough
454 // conditional branch.
455 if (isLayoutSuccessor(TBB)) {
456 if (TII->ReverseBranchCondition(Cond))
458 TII->RemoveBranch(*this);
459 TII->InsertBranch(*this, FBB, nullptr, Cond, DL);
460 } else if (isLayoutSuccessor(FBB)) {
461 TII->RemoveBranch(*this);
462 TII->InsertBranch(*this, TBB, nullptr, Cond, DL);
465 // Walk through the successors and find the successor which is not
466 // a landing pad and is not the conditional branch destination (in TBB)
467 // as the fallthrough successor.
468 MachineBasicBlock *FallthroughBB = nullptr;
469 for (succ_iterator SI = succ_begin(), SE = succ_end(); SI != SE; ++SI) {
470 if ((*SI)->isEHPad() || *SI == TBB)
472 assert(!FallthroughBB && "Found more than one fallthrough successor.");
475 if (!FallthroughBB && canFallThrough()) {
476 // We fallthrough to the same basic block as the conditional jump
477 // targets. Remove the conditional jump, leaving unconditional
479 // FIXME: This does not seem like a reasonable pattern to support, but
480 // it has been seen in the wild coming out of degenerate ARM test cases.
481 TII->RemoveBranch(*this);
483 // Finally update the unconditional successor to be reached via a branch
484 // if it would not be reached by fallthrough.
485 if (!isLayoutSuccessor(TBB))
486 TII->InsertBranch(*this, TBB, nullptr, Cond, DL);
490 // The block has a fallthrough conditional branch.
491 if (isLayoutSuccessor(TBB)) {
492 if (TII->ReverseBranchCondition(Cond)) {
493 // We can't reverse the condition, add an unconditional branch.
495 TII->InsertBranch(*this, FallthroughBB, nullptr, Cond, DL);
498 TII->RemoveBranch(*this);
499 TII->InsertBranch(*this, FallthroughBB, nullptr, Cond, DL);
500 } else if (!isLayoutSuccessor(FallthroughBB)) {
501 TII->RemoveBranch(*this);
502 TII->InsertBranch(*this, TBB, FallthroughBB, Cond, DL);
508 void MachineBasicBlock::addSuccessor(MachineBasicBlock *Succ, uint32_t Weight) {
509 // Weight list is either empty (if successor list isn't empty, this means
510 // disabled optimization) or has the same size as successor list.
511 if (!(Weights.empty() && !Successors.empty()))
512 Weights.push_back(Weight);
513 Successors.push_back(Succ);
514 Succ->addPredecessor(this);
517 void MachineBasicBlock::addSuccessorWithoutWeight(MachineBasicBlock *Succ) {
518 // We need to make sure weight list is either empty or has the same size of
519 // successor list. When this function is called, we can safely delete all
520 // weight in the list.
522 Successors.push_back(Succ);
523 Succ->addPredecessor(this);
526 void MachineBasicBlock::removeSuccessor(MachineBasicBlock *Succ) {
527 Succ->removePredecessor(this);
528 succ_iterator I = std::find(Successors.begin(), Successors.end(), Succ);
529 assert(I != Successors.end() && "Not a current successor!");
531 // If Weight list is empty it means we don't use it (disabled optimization).
532 if (!Weights.empty()) {
533 weight_iterator WI = getWeightIterator(I);
540 MachineBasicBlock::succ_iterator
541 MachineBasicBlock::removeSuccessor(succ_iterator I) {
542 assert(I != Successors.end() && "Not a current successor!");
544 // If Weight list is empty it means we don't use it (disabled optimization).
545 if (!Weights.empty()) {
546 weight_iterator WI = getWeightIterator(I);
550 (*I)->removePredecessor(this);
551 return Successors.erase(I);
554 void MachineBasicBlock::replaceSuccessor(MachineBasicBlock *Old,
555 MachineBasicBlock *New) {
559 succ_iterator E = succ_end();
560 succ_iterator NewI = E;
561 succ_iterator OldI = E;
562 for (succ_iterator I = succ_begin(); I != E; ++I) {
574 assert(OldI != E && "Old is not a successor of this block");
575 Old->removePredecessor(this);
577 // If New isn't already a successor, let it take Old's place.
579 New->addPredecessor(this);
584 // New is already a successor.
585 // Update its weight instead of adding a duplicate edge.
586 if (!Weights.empty()) {
587 weight_iterator OldWI = getWeightIterator(OldI);
588 *getWeightIterator(NewI) += *OldWI;
589 Weights.erase(OldWI);
591 Successors.erase(OldI);
594 void MachineBasicBlock::addPredecessor(MachineBasicBlock *Pred) {
595 Predecessors.push_back(Pred);
598 void MachineBasicBlock::removePredecessor(MachineBasicBlock *Pred) {
599 pred_iterator I = std::find(Predecessors.begin(), Predecessors.end(), Pred);
600 assert(I != Predecessors.end() && "Pred is not a predecessor of this block!");
601 Predecessors.erase(I);
604 void MachineBasicBlock::transferSuccessors(MachineBasicBlock *FromMBB) {
608 while (!FromMBB->succ_empty()) {
609 MachineBasicBlock *Succ = *FromMBB->succ_begin();
612 // If Weight list is empty it means we don't use it (disabled optimization).
613 if (!FromMBB->Weights.empty())
614 Weight = *FromMBB->Weights.begin();
616 addSuccessor(Succ, Weight);
617 FromMBB->removeSuccessor(Succ);
622 MachineBasicBlock::transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB) {
626 while (!FromMBB->succ_empty()) {
627 MachineBasicBlock *Succ = *FromMBB->succ_begin();
629 if (!FromMBB->Weights.empty())
630 Weight = *FromMBB->Weights.begin();
631 addSuccessor(Succ, Weight);
632 FromMBB->removeSuccessor(Succ);
634 // Fix up any PHI nodes in the successor.
635 for (MachineBasicBlock::instr_iterator MI = Succ->instr_begin(),
636 ME = Succ->instr_end(); MI != ME && MI->isPHI(); ++MI)
637 for (unsigned i = 2, e = MI->getNumOperands()+1; i != e; i += 2) {
638 MachineOperand &MO = MI->getOperand(i);
639 if (MO.getMBB() == FromMBB)
645 bool MachineBasicBlock::isPredecessor(const MachineBasicBlock *MBB) const {
646 return std::find(pred_begin(), pred_end(), MBB) != pred_end();
649 bool MachineBasicBlock::isSuccessor(const MachineBasicBlock *MBB) const {
650 return std::find(succ_begin(), succ_end(), MBB) != succ_end();
653 bool MachineBasicBlock::isLayoutSuccessor(const MachineBasicBlock *MBB) const {
654 MachineFunction::const_iterator I(this);
655 return std::next(I) == MachineFunction::const_iterator(MBB);
658 bool MachineBasicBlock::canFallThrough() {
659 MachineFunction::iterator Fallthrough = getIterator();
661 // If FallthroughBlock is off the end of the function, it can't fall through.
662 if (Fallthrough == getParent()->end())
665 // If FallthroughBlock isn't a successor, no fallthrough is possible.
666 if (!isSuccessor(&*Fallthrough))
669 // Analyze the branches, if any, at the end of the block.
670 MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
671 SmallVector<MachineOperand, 4> Cond;
672 const TargetInstrInfo *TII = getParent()->getSubtarget().getInstrInfo();
673 if (TII->AnalyzeBranch(*this, TBB, FBB, Cond)) {
674 // If we couldn't analyze the branch, examine the last instruction.
675 // If the block doesn't end in a known control barrier, assume fallthrough
676 // is possible. The isPredicated check is needed because this code can be
677 // called during IfConversion, where an instruction which is normally a
678 // Barrier is predicated and thus no longer an actual control barrier.
679 return empty() || !back().isBarrier() || TII->isPredicated(&back());
682 // If there is no branch, control always falls through.
683 if (!TBB) return true;
685 // If there is some explicit branch to the fallthrough block, it can obviously
686 // reach, even though the branch should get folded to fall through implicitly.
687 if (MachineFunction::iterator(TBB) == Fallthrough ||
688 MachineFunction::iterator(FBB) == Fallthrough)
691 // If it's an unconditional branch to some block not the fall through, it
692 // doesn't fall through.
693 if (Cond.empty()) return false;
695 // Otherwise, if it is conditional and has no explicit false block, it falls
697 return FBB == nullptr;
701 MachineBasicBlock::SplitCriticalEdge(MachineBasicBlock *Succ, Pass *P) {
702 // Splitting the critical edge to a landing pad block is non-trivial. Don't do
703 // it in this generic function.
707 MachineFunction *MF = getParent();
708 DebugLoc DL; // FIXME: this is nowhere
710 // Performance might be harmed on HW that implements branching using exec mask
711 // where both sides of the branches are always executed.
712 if (MF->getTarget().requiresStructuredCFG())
715 // We may need to update this's terminator, but we can't do that if
716 // AnalyzeBranch fails. If this uses a jump table, we won't touch it.
717 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
718 MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
719 SmallVector<MachineOperand, 4> Cond;
720 if (TII->AnalyzeBranch(*this, TBB, FBB, Cond))
723 // Avoid bugpoint weirdness: A block may end with a conditional branch but
724 // jumps to the same MBB is either case. We have duplicate CFG edges in that
725 // case that we can't handle. Since this never happens in properly optimized
726 // code, just skip those edges.
727 if (TBB && TBB == FBB) {
728 DEBUG(dbgs() << "Won't split critical edge after degenerate BB#"
729 << getNumber() << '\n');
733 MachineBasicBlock *NMBB = MF->CreateMachineBasicBlock();
734 MF->insert(std::next(MachineFunction::iterator(this)), NMBB);
735 DEBUG(dbgs() << "Splitting critical edge:"
736 " BB#" << getNumber()
737 << " -- BB#" << NMBB->getNumber()
738 << " -- BB#" << Succ->getNumber() << '\n');
740 LiveIntervals *LIS = P->getAnalysisIfAvailable<LiveIntervals>();
741 SlotIndexes *Indexes = P->getAnalysisIfAvailable<SlotIndexes>();
743 LIS->insertMBBInMaps(NMBB);
745 Indexes->insertMBBInMaps(NMBB);
747 // On some targets like Mips, branches may kill virtual registers. Make sure
748 // that LiveVariables is properly updated after updateTerminator replaces the
750 LiveVariables *LV = P->getAnalysisIfAvailable<LiveVariables>();
752 // Collect a list of virtual registers killed by the terminators.
753 SmallVector<unsigned, 4> KilledRegs;
755 for (instr_iterator I = getFirstInstrTerminator(), E = instr_end();
757 MachineInstr *MI = &*I;
758 for (MachineInstr::mop_iterator OI = MI->operands_begin(),
759 OE = MI->operands_end(); OI != OE; ++OI) {
760 if (!OI->isReg() || OI->getReg() == 0 ||
761 !OI->isUse() || !OI->isKill() || OI->isUndef())
763 unsigned Reg = OI->getReg();
764 if (TargetRegisterInfo::isPhysicalRegister(Reg) ||
765 LV->getVarInfo(Reg).removeKill(MI)) {
766 KilledRegs.push_back(Reg);
767 DEBUG(dbgs() << "Removing terminator kill: " << *MI);
768 OI->setIsKill(false);
773 SmallVector<unsigned, 4> UsedRegs;
775 for (instr_iterator I = getFirstInstrTerminator(), E = instr_end();
777 MachineInstr *MI = &*I;
779 for (MachineInstr::mop_iterator OI = MI->operands_begin(),
780 OE = MI->operands_end(); OI != OE; ++OI) {
781 if (!OI->isReg() || OI->getReg() == 0)
784 unsigned Reg = OI->getReg();
785 if (std::find(UsedRegs.begin(), UsedRegs.end(), Reg) == UsedRegs.end())
786 UsedRegs.push_back(Reg);
791 ReplaceUsesOfBlockWith(Succ, NMBB);
793 // If updateTerminator() removes instructions, we need to remove them from
795 SmallVector<MachineInstr*, 4> Terminators;
797 for (instr_iterator I = getFirstInstrTerminator(), E = instr_end();
799 Terminators.push_back(&*I);
805 SmallVector<MachineInstr*, 4> NewTerminators;
806 for (instr_iterator I = getFirstInstrTerminator(), E = instr_end();
808 NewTerminators.push_back(&*I);
810 for (SmallVectorImpl<MachineInstr*>::iterator I = Terminators.begin(),
811 E = Terminators.end(); I != E; ++I) {
812 if (std::find(NewTerminators.begin(), NewTerminators.end(), *I) ==
813 NewTerminators.end())
814 Indexes->removeMachineInstrFromMaps(*I);
818 // Insert unconditional "jump Succ" instruction in NMBB if necessary.
819 NMBB->addSuccessor(Succ);
820 if (!NMBB->isLayoutSuccessor(Succ)) {
822 TII->InsertBranch(*NMBB, Succ, nullptr, Cond, DL);
825 for (instr_iterator I = NMBB->instr_begin(), E = NMBB->instr_end();
827 // Some instructions may have been moved to NMBB by updateTerminator(),
828 // so we first remove any instruction that already has an index.
829 if (Indexes->hasIndex(&*I))
830 Indexes->removeMachineInstrFromMaps(&*I);
831 Indexes->insertMachineInstrInMaps(&*I);
836 // Fix PHI nodes in Succ so they refer to NMBB instead of this
837 for (MachineBasicBlock::instr_iterator
838 i = Succ->instr_begin(),e = Succ->instr_end();
839 i != e && i->isPHI(); ++i)
840 for (unsigned ni = 1, ne = i->getNumOperands(); ni != ne; ni += 2)
841 if (i->getOperand(ni+1).getMBB() == this)
842 i->getOperand(ni+1).setMBB(NMBB);
844 // Inherit live-ins from the successor
845 for (const auto &LI : Succ->liveins())
848 // Update LiveVariables.
849 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
851 // Restore kills of virtual registers that were killed by the terminators.
852 while (!KilledRegs.empty()) {
853 unsigned Reg = KilledRegs.pop_back_val();
854 for (instr_iterator I = instr_end(), E = instr_begin(); I != E;) {
855 if (!(--I)->addRegisterKilled(Reg, TRI, /* addIfNotFound= */ false))
857 if (TargetRegisterInfo::isVirtualRegister(Reg))
858 LV->getVarInfo(Reg).Kills.push_back(&*I);
859 DEBUG(dbgs() << "Restored terminator kill: " << *I);
863 // Update relevant live-through information.
864 LV->addNewBlock(NMBB, this, Succ);
868 // After splitting the edge and updating SlotIndexes, live intervals may be
869 // in one of two situations, depending on whether this block was the last in
870 // the function. If the original block was the last in the function, all
871 // live intervals will end prior to the beginning of the new split block. If
872 // the original block was not at the end of the function, all live intervals
873 // will extend to the end of the new split block.
876 std::next(MachineFunction::iterator(NMBB)) == getParent()->end();
878 SlotIndex StartIndex = Indexes->getMBBEndIdx(this);
879 SlotIndex PrevIndex = StartIndex.getPrevSlot();
880 SlotIndex EndIndex = Indexes->getMBBEndIdx(NMBB);
882 // Find the registers used from NMBB in PHIs in Succ.
883 SmallSet<unsigned, 8> PHISrcRegs;
884 for (MachineBasicBlock::instr_iterator
885 I = Succ->instr_begin(), E = Succ->instr_end();
886 I != E && I->isPHI(); ++I) {
887 for (unsigned ni = 1, ne = I->getNumOperands(); ni != ne; ni += 2) {
888 if (I->getOperand(ni+1).getMBB() == NMBB) {
889 MachineOperand &MO = I->getOperand(ni);
890 unsigned Reg = MO.getReg();
891 PHISrcRegs.insert(Reg);
895 LiveInterval &LI = LIS->getInterval(Reg);
896 VNInfo *VNI = LI.getVNInfoAt(PrevIndex);
898 "PHI sources should be live out of their predecessors.");
899 LI.addSegment(LiveInterval::Segment(StartIndex, EndIndex, VNI));
904 MachineRegisterInfo *MRI = &getParent()->getRegInfo();
905 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
906 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
907 if (PHISrcRegs.count(Reg) || !LIS->hasInterval(Reg))
910 LiveInterval &LI = LIS->getInterval(Reg);
911 if (!LI.liveAt(PrevIndex))
914 bool isLiveOut = LI.liveAt(LIS->getMBBStartIdx(Succ));
915 if (isLiveOut && isLastMBB) {
916 VNInfo *VNI = LI.getVNInfoAt(PrevIndex);
917 assert(VNI && "LiveInterval should have VNInfo where it is live.");
918 LI.addSegment(LiveInterval::Segment(StartIndex, EndIndex, VNI));
919 } else if (!isLiveOut && !isLastMBB) {
920 LI.removeSegment(StartIndex, EndIndex);
924 // Update all intervals for registers whose uses may have been modified by
925 // updateTerminator().
926 LIS->repairIntervalsInRange(this, getFirstTerminator(), end(), UsedRegs);
929 if (MachineDominatorTree *MDT =
930 P->getAnalysisIfAvailable<MachineDominatorTree>())
931 MDT->recordSplitCriticalEdge(this, Succ, NMBB);
933 if (MachineLoopInfo *MLI = P->getAnalysisIfAvailable<MachineLoopInfo>())
934 if (MachineLoop *TIL = MLI->getLoopFor(this)) {
935 // If one or the other blocks were not in a loop, the new block is not
936 // either, and thus LI doesn't need to be updated.
937 if (MachineLoop *DestLoop = MLI->getLoopFor(Succ)) {
938 if (TIL == DestLoop) {
939 // Both in the same loop, the NMBB joins loop.
940 DestLoop->addBasicBlockToLoop(NMBB, MLI->getBase());
941 } else if (TIL->contains(DestLoop)) {
942 // Edge from an outer loop to an inner loop. Add to the outer loop.
943 TIL->addBasicBlockToLoop(NMBB, MLI->getBase());
944 } else if (DestLoop->contains(TIL)) {
945 // Edge from an inner loop to an outer loop. Add to the outer loop.
946 DestLoop->addBasicBlockToLoop(NMBB, MLI->getBase());
948 // Edge from two loops with no containment relation. Because these
949 // are natural loops, we know that the destination block must be the
950 // header of its loop (adding a branch into a loop elsewhere would
951 // create an irreducible loop).
952 assert(DestLoop->getHeader() == Succ &&
953 "Should not create irreducible loops!");
954 if (MachineLoop *P = DestLoop->getParentLoop())
955 P->addBasicBlockToLoop(NMBB, MLI->getBase());
963 /// Prepare MI to be removed from its bundle. This fixes bundle flags on MI's
964 /// neighboring instructions so the bundle won't be broken by removing MI.
965 static void unbundleSingleMI(MachineInstr *MI) {
966 // Removing the first instruction in a bundle.
967 if (MI->isBundledWithSucc() && !MI->isBundledWithPred())
968 MI->unbundleFromSucc();
969 // Removing the last instruction in a bundle.
970 if (MI->isBundledWithPred() && !MI->isBundledWithSucc())
971 MI->unbundleFromPred();
972 // If MI is not bundled, or if it is internal to a bundle, the neighbor flags
976 MachineBasicBlock::instr_iterator
977 MachineBasicBlock::erase(MachineBasicBlock::instr_iterator I) {
978 unbundleSingleMI(&*I);
979 return Insts.erase(I);
982 MachineInstr *MachineBasicBlock::remove_instr(MachineInstr *MI) {
983 unbundleSingleMI(MI);
984 MI->clearFlag(MachineInstr::BundledPred);
985 MI->clearFlag(MachineInstr::BundledSucc);
986 return Insts.remove(MI);
989 MachineBasicBlock::instr_iterator
990 MachineBasicBlock::insert(instr_iterator I, MachineInstr *MI) {
991 assert(!MI->isBundledWithPred() && !MI->isBundledWithSucc() &&
992 "Cannot insert instruction with bundle flags");
993 // Set the bundle flags when inserting inside a bundle.
994 if (I != instr_end() && I->isBundledWithPred()) {
995 MI->setFlag(MachineInstr::BundledPred);
996 MI->setFlag(MachineInstr::BundledSucc);
998 return Insts.insert(I, MI);
1001 /// This method unlinks 'this' from the containing function, and returns it, but
1002 /// does not delete it.
1003 MachineBasicBlock *MachineBasicBlock::removeFromParent() {
1004 assert(getParent() && "Not embedded in a function!");
1005 getParent()->remove(this);
1009 /// This method unlinks 'this' from the containing function, and deletes it.
1010 void MachineBasicBlock::eraseFromParent() {
1011 assert(getParent() && "Not embedded in a function!");
1012 getParent()->erase(this);
1015 /// Given a machine basic block that branched to 'Old', change the code and CFG
1016 /// so that it branches to 'New' instead.
1017 void MachineBasicBlock::ReplaceUsesOfBlockWith(MachineBasicBlock *Old,
1018 MachineBasicBlock *New) {
1019 assert(Old != New && "Cannot replace self with self!");
1021 MachineBasicBlock::instr_iterator I = instr_end();
1022 while (I != instr_begin()) {
1024 if (!I->isTerminator()) break;
1026 // Scan the operands of this machine instruction, replacing any uses of Old
1028 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i)
1029 if (I->getOperand(i).isMBB() &&
1030 I->getOperand(i).getMBB() == Old)
1031 I->getOperand(i).setMBB(New);
1034 // Update the successor information.
1035 replaceSuccessor(Old, New);
1038 /// Various pieces of code can cause excess edges in the CFG to be inserted. If
1039 /// we have proven that MBB can only branch to DestA and DestB, remove any other
1040 /// MBB successors from the CFG. DestA and DestB can be null.
1042 /// Besides DestA and DestB, retain other edges leading to LandingPads
1043 /// (currently there can be only one; we don't check or require that here).
1044 /// Note it is possible that DestA and/or DestB are LandingPads.
1045 bool MachineBasicBlock::CorrectExtraCFGEdges(MachineBasicBlock *DestA,
1046 MachineBasicBlock *DestB,
1048 // The values of DestA and DestB frequently come from a call to the
1049 // 'TargetInstrInfo::AnalyzeBranch' method. We take our meaning of the initial
1050 // values from there.
1052 // 1. If both DestA and DestB are null, then the block ends with no branches
1053 // (it falls through to its successor).
1054 // 2. If DestA is set, DestB is null, and IsCond is false, then the block ends
1055 // with only an unconditional branch.
1056 // 3. If DestA is set, DestB is null, and IsCond is true, then the block ends
1057 // with a conditional branch that falls through to a successor (DestB).
1058 // 4. If DestA and DestB is set and IsCond is true, then the block ends with a
1059 // conditional branch followed by an unconditional branch. DestA is the
1060 // 'true' destination and DestB is the 'false' destination.
1062 bool Changed = false;
1064 MachineFunction::iterator FallThru = std::next(getIterator());
1066 if (!DestA && !DestB) {
1067 // Block falls through to successor.
1070 } else if (DestA && !DestB) {
1072 // Block ends in conditional jump that falls through to successor.
1075 assert(DestA && DestB && IsCond &&
1076 "CFG in a bad state. Cannot correct CFG edges");
1079 // Remove superfluous edges. I.e., those which aren't destinations of this
1080 // basic block, duplicate edges, or landing pads.
1081 SmallPtrSet<const MachineBasicBlock*, 8> SeenMBBs;
1082 MachineBasicBlock::succ_iterator SI = succ_begin();
1083 while (SI != succ_end()) {
1084 const MachineBasicBlock *MBB = *SI;
1085 if (!SeenMBBs.insert(MBB).second ||
1086 (MBB != DestA && MBB != DestB && !MBB->isEHPad())) {
1087 // This is a superfluous edge, remove it.
1088 SI = removeSuccessor(SI);
1098 /// Find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE
1099 /// instructions. Return UnknownLoc if there is none.
1101 MachineBasicBlock::findDebugLoc(instr_iterator MBBI) {
1103 instr_iterator E = instr_end();
1107 // Skip debug declarations, we don't want a DebugLoc from them.
1108 while (MBBI != E && MBBI->isDebugValue())
1111 DL = MBBI->getDebugLoc();
1115 /// Return weight of the edge from this block to MBB.
1116 uint32_t MachineBasicBlock::getSuccWeight(const_succ_iterator Succ) const {
1117 if (Weights.empty())
1120 return *getWeightIterator(Succ);
1123 /// Set successor weight of a given iterator.
1124 void MachineBasicBlock::setSuccWeight(succ_iterator I, uint32_t Weight) {
1125 if (Weights.empty())
1127 *getWeightIterator(I) = Weight;
1130 /// Return wight iterator corresonding to the I successor iterator.
1131 MachineBasicBlock::weight_iterator MachineBasicBlock::
1132 getWeightIterator(MachineBasicBlock::succ_iterator I) {
1133 assert(Weights.size() == Successors.size() && "Async weight list!");
1134 size_t index = std::distance(Successors.begin(), I);
1135 assert(index < Weights.size() && "Not a current successor!");
1136 return Weights.begin() + index;
1139 /// Return wight iterator corresonding to the I successor iterator.
1140 MachineBasicBlock::const_weight_iterator MachineBasicBlock::
1141 getWeightIterator(MachineBasicBlock::const_succ_iterator I) const {
1142 assert(Weights.size() == Successors.size() && "Async weight list!");
1143 const size_t index = std::distance(Successors.begin(), I);
1144 assert(index < Weights.size() && "Not a current successor!");
1145 return Weights.begin() + index;
1148 /// Return whether (physical) register "Reg" has been <def>ined and not <kill>ed
1149 /// as of just before "MI".
1151 /// Search is localised to a neighborhood of
1152 /// Neighborhood instructions before (searching for defs or kills) and N
1153 /// instructions after (searching just for defs) MI.
1154 MachineBasicBlock::LivenessQueryResult
1155 MachineBasicBlock::computeRegisterLiveness(const TargetRegisterInfo *TRI,
1156 unsigned Reg, const_iterator Before,
1157 unsigned Neighborhood) const {
1158 unsigned N = Neighborhood;
1160 // Start by searching backwards from Before, looking for kills, reads or defs.
1161 const_iterator I(Before);
1162 // If this is the first insn in the block, don't search backwards.
1167 MachineOperandIteratorBase::PhysRegInfo Analysis =
1168 ConstMIOperands(I).analyzePhysReg(Reg, TRI);
1170 if (Analysis.Defines)
1171 // Outputs happen after inputs so they take precedence if both are
1173 return Analysis.DefinesDead ? LQR_Dead : LQR_Live;
1175 if (Analysis.Kills || Analysis.Clobbers)
1176 // Register killed, so isn't live.
1179 else if (Analysis.ReadsOverlap)
1180 // Defined or read without a previous kill - live.
1181 return Analysis.Reads ? LQR_Live : LQR_OverlappingLive;
1183 } while (I != begin() && --N > 0);
1186 // Did we get to the start of the block?
1188 // If so, the register's state is definitely defined by the live-in state.
1189 for (MCRegAliasIterator RAI(Reg, TRI, /*IncludeSelf=*/true);
1190 RAI.isValid(); ++RAI) {
1192 return (*RAI == Reg) ? LQR_Live : LQR_OverlappingLive;
1200 // Try searching forwards from Before, looking for reads or defs.
1201 I = const_iterator(Before);
1202 // If this is the last insn in the block, don't search forwards.
1204 for (++I; I != end() && N > 0; ++I, --N) {
1205 MachineOperandIteratorBase::PhysRegInfo Analysis =
1206 ConstMIOperands(I).analyzePhysReg(Reg, TRI);
1208 if (Analysis.ReadsOverlap)
1209 // Used, therefore must have been live.
1210 return (Analysis.Reads) ?
1211 LQR_Live : LQR_OverlappingLive;
1213 else if (Analysis.Clobbers || Analysis.Defines)
1214 // Defined (but not read) therefore cannot have been live.
1219 // At this point we have no idea of the liveness of the register.