1 //===-- llvm/CodeGen/MachineBasicBlock.cpp ----------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Collect the sequence of machine instructions for a basic block.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/MachineBasicBlock.h"
15 #include "llvm/ADT/SmallPtrSet.h"
16 #include "llvm/ADT/SmallString.h"
17 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
18 #include "llvm/CodeGen/LiveVariables.h"
19 #include "llvm/CodeGen/MachineDominators.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineLoopInfo.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/SlotIndexes.h"
25 #include "llvm/IR/BasicBlock.h"
26 #include "llvm/IR/DataLayout.h"
27 #include "llvm/IR/ModuleSlotTracker.h"
28 #include "llvm/MC/MCAsmInfo.h"
29 #include "llvm/MC/MCContext.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/raw_ostream.h"
32 #include "llvm/Target/TargetInstrInfo.h"
33 #include "llvm/Target/TargetMachine.h"
34 #include "llvm/Target/TargetRegisterInfo.h"
35 #include "llvm/Target/TargetSubtargetInfo.h"
39 #define DEBUG_TYPE "codegen"
41 MachineBasicBlock::MachineBasicBlock(MachineFunction &MF, const BasicBlock *B)
42 : BB(B), Number(-1), xParent(&MF) {
46 MachineBasicBlock::~MachineBasicBlock() {
49 /// Return the MCSymbol for this basic block.
50 MCSymbol *MachineBasicBlock::getSymbol() const {
51 if (!CachedMCSymbol) {
52 const MachineFunction *MF = getParent();
53 MCContext &Ctx = MF->getContext();
54 const char *Prefix = Ctx.getAsmInfo()->getPrivateLabelPrefix();
55 CachedMCSymbol = Ctx.getOrCreateSymbol(Twine(Prefix) + "BB" +
56 Twine(MF->getFunctionNumber()) +
57 "_" + Twine(getNumber()));
60 return CachedMCSymbol;
64 raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineBasicBlock &MBB) {
69 /// When an MBB is added to an MF, we need to update the parent pointer of the
70 /// MBB, the MBB numbering, and any instructions in the MBB to be on the right
71 /// operand list for registers.
73 /// MBBs start out as #-1. When a MBB is added to a MachineFunction, it
74 /// gets the next available unique MBB number. If it is removed from a
75 /// MachineFunction, it goes back to being #-1.
76 void ilist_traits<MachineBasicBlock>::addNodeToList(MachineBasicBlock *N) {
77 MachineFunction &MF = *N->getParent();
78 N->Number = MF.addToMBBNumbering(N);
80 // Make sure the instructions have their operands in the reginfo lists.
81 MachineRegisterInfo &RegInfo = MF.getRegInfo();
82 for (MachineBasicBlock::instr_iterator
83 I = N->instr_begin(), E = N->instr_end(); I != E; ++I)
84 I->AddRegOperandsToUseLists(RegInfo);
87 void ilist_traits<MachineBasicBlock>::removeNodeFromList(MachineBasicBlock *N) {
88 N->getParent()->removeFromMBBNumbering(N->Number);
92 /// When we add an instruction to a basic block list, we update its parent
93 /// pointer and add its operands from reg use/def lists if appropriate.
94 void ilist_traits<MachineInstr>::addNodeToList(MachineInstr *N) {
95 assert(!N->getParent() && "machine instruction already in a basic block");
98 // Add the instruction's register operands to their corresponding
100 MachineFunction *MF = Parent->getParent();
101 N->AddRegOperandsToUseLists(MF->getRegInfo());
104 /// When we remove an instruction from a basic block list, we update its parent
105 /// pointer and remove its operands from reg use/def lists if appropriate.
106 void ilist_traits<MachineInstr>::removeNodeFromList(MachineInstr *N) {
107 assert(N->getParent() && "machine instruction not in a basic block");
109 // Remove from the use/def lists.
110 if (MachineFunction *MF = N->getParent()->getParent())
111 N->RemoveRegOperandsFromUseLists(MF->getRegInfo());
113 N->setParent(nullptr);
116 /// When moving a range of instructions from one MBB list to another, we need to
117 /// update the parent pointers and the use/def lists.
118 void ilist_traits<MachineInstr>::
119 transferNodesFromList(ilist_traits<MachineInstr> &FromList,
120 ilist_iterator<MachineInstr> First,
121 ilist_iterator<MachineInstr> Last) {
122 assert(Parent->getParent() == FromList.Parent->getParent() &&
123 "MachineInstr parent mismatch!");
125 // Splice within the same MBB -> no change.
126 if (Parent == FromList.Parent) return;
128 // If splicing between two blocks within the same function, just update the
130 for (; First != Last; ++First)
131 First->setParent(Parent);
134 void ilist_traits<MachineInstr>::deleteNode(MachineInstr* MI) {
135 assert(!MI->getParent() && "MI is still in a block!");
136 Parent->getParent()->DeleteMachineInstr(MI);
139 MachineBasicBlock::iterator MachineBasicBlock::getFirstNonPHI() {
140 instr_iterator I = instr_begin(), E = instr_end();
141 while (I != E && I->isPHI())
143 assert((I == E || !I->isInsideBundle()) &&
144 "First non-phi MI cannot be inside a bundle!");
148 MachineBasicBlock::iterator
149 MachineBasicBlock::SkipPHIsAndLabels(MachineBasicBlock::iterator I) {
151 while (I != E && (I->isPHI() || I->isPosition() || I->isDebugValue()))
153 // FIXME: This needs to change if we wish to bundle labels / dbg_values
154 // inside the bundle.
155 assert((I == E || !I->isInsideBundle()) &&
156 "First non-phi / non-label instruction is inside a bundle!");
160 MachineBasicBlock::iterator MachineBasicBlock::getFirstTerminator() {
161 iterator B = begin(), E = end(), I = E;
162 while (I != B && ((--I)->isTerminator() || I->isDebugValue()))
164 while (I != E && !I->isTerminator())
169 MachineBasicBlock::instr_iterator MachineBasicBlock::getFirstInstrTerminator() {
170 instr_iterator B = instr_begin(), E = instr_end(), I = E;
171 while (I != B && ((--I)->isTerminator() || I->isDebugValue()))
173 while (I != E && !I->isTerminator())
178 MachineBasicBlock::iterator MachineBasicBlock::getFirstNonDebugInstr() {
179 // Skip over begin-of-block dbg_value instructions.
180 iterator I = begin(), E = end();
181 while (I != E && I->isDebugValue())
186 MachineBasicBlock::iterator MachineBasicBlock::getLastNonDebugInstr() {
187 // Skip over end-of-block dbg_value instructions.
188 instr_iterator B = instr_begin(), I = instr_end();
191 // Return instruction that starts a bundle.
192 if (I->isDebugValue() || I->isInsideBundle())
196 // The block is all debug values.
200 const MachineBasicBlock *MachineBasicBlock::getLandingPadSuccessor() const {
201 // A block with a landing pad successor only has one other successor.
204 for (const_succ_iterator I = succ_begin(), E = succ_end(); I != E; ++I)
210 bool MachineBasicBlock::hasEHPadSuccessor() const {
211 for (const_succ_iterator I = succ_begin(), E = succ_end(); I != E; ++I)
217 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
218 void MachineBasicBlock::dump() const {
223 StringRef MachineBasicBlock::getName() const {
224 if (const BasicBlock *LBB = getBasicBlock())
225 return LBB->getName();
230 /// Return a hopefully unique identifier for this block.
231 std::string MachineBasicBlock::getFullName() const {
234 Name = (getParent()->getName() + ":").str();
236 Name += getBasicBlock()->getName();
238 Name += ("BB" + Twine(getNumber())).str();
242 void MachineBasicBlock::print(raw_ostream &OS, SlotIndexes *Indexes) const {
243 const MachineFunction *MF = getParent();
245 OS << "Can't print out MachineBasicBlock because parent MachineFunction"
249 const Function *F = MF->getFunction();
250 const Module *M = F ? F->getParent() : nullptr;
251 ModuleSlotTracker MST(M);
252 print(OS, MST, Indexes);
255 void MachineBasicBlock::print(raw_ostream &OS, ModuleSlotTracker &MST,
256 SlotIndexes *Indexes) const {
257 const MachineFunction *MF = getParent();
259 OS << "Can't print out MachineBasicBlock because parent MachineFunction"
265 OS << Indexes->getMBBStartIdx(this) << '\t';
267 OS << "BB#" << getNumber() << ": ";
269 const char *Comma = "";
270 if (const BasicBlock *LBB = getBasicBlock()) {
271 OS << Comma << "derived from LLVM BB ";
272 LBB->printAsOperand(OS, /*PrintType=*/false, MST);
275 if (isEHPad()) { OS << Comma << "EH LANDING PAD"; Comma = ", "; }
276 if (hasAddressTaken()) { OS << Comma << "ADDRESS TAKEN"; Comma = ", "; }
278 OS << Comma << "Align " << Alignment << " (" << (1u << Alignment)
283 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
284 if (!livein_empty()) {
285 if (Indexes) OS << '\t';
287 for (const auto &LI : make_range(livein_begin(), livein_end())) {
288 OS << ' ' << PrintReg(LI.PhysReg, TRI);
289 if (LI.LaneMask != ~0u)
290 OS << ':' << PrintLaneMask(LI.LaneMask);
294 // Print the preds of this block according to the CFG.
296 if (Indexes) OS << '\t';
297 OS << " Predecessors according to CFG:";
298 for (const_pred_iterator PI = pred_begin(), E = pred_end(); PI != E; ++PI)
299 OS << " BB#" << (*PI)->getNumber();
303 for (const_instr_iterator I = instr_begin(); I != instr_end(); ++I) {
305 if (Indexes->hasIndex(&*I))
306 OS << Indexes->getInstructionIndex(&*I);
310 if (I->isInsideBundle())
315 // Print the successors of this block according to the CFG.
317 if (Indexes) OS << '\t';
318 OS << " Successors according to CFG:";
319 for (const_succ_iterator SI = succ_begin(), E = succ_end(); SI != E; ++SI) {
320 OS << " BB#" << (*SI)->getNumber();
321 if (!Weights.empty())
322 OS << '(' << *getWeightIterator(SI) << ')';
328 void MachineBasicBlock::printAsOperand(raw_ostream &OS,
329 bool /*PrintType*/) const {
330 OS << "BB#" << getNumber();
333 void MachineBasicBlock::removeLiveIn(MCPhysReg Reg, LaneBitmask LaneMask) {
334 LiveInVector::iterator I = std::find_if(
335 LiveIns.begin(), LiveIns.end(),
336 [Reg] (const RegisterMaskPair &LI) { return LI.PhysReg == Reg; });
337 if (I == LiveIns.end())
340 I->LaneMask &= ~LaneMask;
341 if (I->LaneMask == 0)
345 bool MachineBasicBlock::isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask) const {
346 livein_iterator I = std::find_if(
347 LiveIns.begin(), LiveIns.end(),
348 [Reg] (const RegisterMaskPair &LI) { return LI.PhysReg == Reg; });
349 return I != livein_end() && (I->LaneMask & LaneMask) != 0;
352 void MachineBasicBlock::sortUniqueLiveIns() {
353 std::sort(LiveIns.begin(), LiveIns.end(),
354 [](const RegisterMaskPair &LI0, const RegisterMaskPair &LI1) {
355 return LI0.PhysReg < LI1.PhysReg;
357 // Liveins are sorted by physreg now we can merge their lanemasks.
358 LiveInVector::const_iterator I = LiveIns.begin();
359 LiveInVector::const_iterator J;
360 LiveInVector::iterator Out = LiveIns.begin();
361 for (; I != LiveIns.end(); ++Out, I = J) {
362 unsigned PhysReg = I->PhysReg;
363 LaneBitmask LaneMask = I->LaneMask;
364 for (J = std::next(I); J != LiveIns.end() && J->PhysReg == PhysReg; ++J)
365 LaneMask |= J->LaneMask;
366 Out->PhysReg = PhysReg;
367 Out->LaneMask = LaneMask;
369 LiveIns.erase(Out, LiveIns.end());
373 MachineBasicBlock::addLiveIn(MCPhysReg PhysReg, const TargetRegisterClass *RC) {
374 assert(getParent() && "MBB must be inserted in function");
375 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg) && "Expected physreg");
376 assert(RC && "Register class is required");
377 assert((isEHPad() || this == &getParent()->front()) &&
378 "Only the entry block and landing pads can have physreg live ins");
380 bool LiveIn = isLiveIn(PhysReg);
381 iterator I = SkipPHIsAndLabels(begin()), E = end();
382 MachineRegisterInfo &MRI = getParent()->getRegInfo();
383 const TargetInstrInfo &TII = *getParent()->getSubtarget().getInstrInfo();
385 // Look for an existing copy.
387 for (;I != E && I->isCopy(); ++I)
388 if (I->getOperand(1).getReg() == PhysReg) {
389 unsigned VirtReg = I->getOperand(0).getReg();
390 if (!MRI.constrainRegClass(VirtReg, RC))
391 llvm_unreachable("Incompatible live-in register class.");
395 // No luck, create a virtual register.
396 unsigned VirtReg = MRI.createVirtualRegister(RC);
397 BuildMI(*this, I, DebugLoc(), TII.get(TargetOpcode::COPY), VirtReg)
398 .addReg(PhysReg, RegState::Kill);
404 void MachineBasicBlock::moveBefore(MachineBasicBlock *NewAfter) {
405 getParent()->splice(NewAfter->getIterator(), getIterator());
408 void MachineBasicBlock::moveAfter(MachineBasicBlock *NewBefore) {
409 getParent()->splice(++NewBefore->getIterator(), getIterator());
412 void MachineBasicBlock::updateTerminator() {
413 const TargetInstrInfo *TII = getParent()->getSubtarget().getInstrInfo();
414 // A block with no successors has no concerns with fall-through edges.
415 if (this->succ_empty()) return;
417 MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
418 SmallVector<MachineOperand, 4> Cond;
419 DebugLoc DL; // FIXME: this is nowhere
420 bool B = TII->AnalyzeBranch(*this, TBB, FBB, Cond);
422 assert(!B && "UpdateTerminators requires analyzable predecessors!");
425 // The block has an unconditional branch. If its successor is now
426 // its layout successor, delete the branch.
427 if (isLayoutSuccessor(TBB))
428 TII->RemoveBranch(*this);
430 // The block has an unconditional fallthrough. If its successor is not
431 // its layout successor, insert a branch. First we have to locate the
432 // only non-landing-pad successor, as that is the fallthrough block.
433 for (succ_iterator SI = succ_begin(), SE = succ_end(); SI != SE; ++SI) {
434 if ((*SI)->isEHPad())
436 assert(!TBB && "Found more than one non-landing-pad successor!");
440 // If there is no non-landing-pad successor, the block has no
441 // fall-through edges to be concerned with.
445 // Finally update the unconditional successor to be reached via a branch
446 // if it would not be reached by fallthrough.
447 if (!isLayoutSuccessor(TBB))
448 TII->InsertBranch(*this, TBB, nullptr, Cond, DL);
452 // The block has a non-fallthrough conditional branch. If one of its
453 // successors is its layout successor, rewrite it to a fallthrough
454 // conditional branch.
455 if (isLayoutSuccessor(TBB)) {
456 if (TII->ReverseBranchCondition(Cond))
458 TII->RemoveBranch(*this);
459 TII->InsertBranch(*this, FBB, nullptr, Cond, DL);
460 } else if (isLayoutSuccessor(FBB)) {
461 TII->RemoveBranch(*this);
462 TII->InsertBranch(*this, TBB, nullptr, Cond, DL);
465 // Walk through the successors and find the successor which is not
466 // a landing pad and is not the conditional branch destination (in TBB)
467 // as the fallthrough successor.
468 MachineBasicBlock *FallthroughBB = nullptr;
469 for (succ_iterator SI = succ_begin(), SE = succ_end(); SI != SE; ++SI) {
470 if ((*SI)->isEHPad() || *SI == TBB)
472 assert(!FallthroughBB && "Found more than one fallthrough successor.");
475 if (!FallthroughBB && canFallThrough()) {
476 // We fallthrough to the same basic block as the conditional jump
477 // targets. Remove the conditional jump, leaving unconditional
479 // FIXME: This does not seem like a reasonable pattern to support, but
480 // it has been seen in the wild coming out of degenerate ARM test cases.
481 TII->RemoveBranch(*this);
483 // Finally update the unconditional successor to be reached via a branch
484 // if it would not be reached by fallthrough.
485 if (!isLayoutSuccessor(TBB))
486 TII->InsertBranch(*this, TBB, nullptr, Cond, DL);
490 // The block has a fallthrough conditional branch.
491 if (isLayoutSuccessor(TBB)) {
492 if (TII->ReverseBranchCondition(Cond)) {
493 // We can't reverse the condition, add an unconditional branch.
495 TII->InsertBranch(*this, FallthroughBB, nullptr, Cond, DL);
498 TII->RemoveBranch(*this);
499 TII->InsertBranch(*this, FallthroughBB, nullptr, Cond, DL);
500 } else if (!isLayoutSuccessor(FallthroughBB)) {
501 TII->RemoveBranch(*this);
502 TII->InsertBranch(*this, TBB, FallthroughBB, Cond, DL);
508 void MachineBasicBlock::addSuccessor(MachineBasicBlock *Succ, uint32_t Weight) {
510 // If we see non-zero value for the first time it means we actually use Weight
511 // list, so we fill all Weights with 0's.
512 if (Weight != 0 && Weights.empty())
513 Weights.resize(Successors.size());
515 if (Weight != 0 || !Weights.empty())
516 Weights.push_back(Weight);
518 Successors.push_back(Succ);
519 Succ->addPredecessor(this);
522 void MachineBasicBlock::removeSuccessor(MachineBasicBlock *Succ) {
523 Succ->removePredecessor(this);
524 succ_iterator I = std::find(Successors.begin(), Successors.end(), Succ);
525 assert(I != Successors.end() && "Not a current successor!");
527 // If Weight list is empty it means we don't use it (disabled optimization).
528 if (!Weights.empty()) {
529 weight_iterator WI = getWeightIterator(I);
536 MachineBasicBlock::succ_iterator
537 MachineBasicBlock::removeSuccessor(succ_iterator I) {
538 assert(I != Successors.end() && "Not a current successor!");
540 // If Weight list is empty it means we don't use it (disabled optimization).
541 if (!Weights.empty()) {
542 weight_iterator WI = getWeightIterator(I);
546 (*I)->removePredecessor(this);
547 return Successors.erase(I);
550 void MachineBasicBlock::replaceSuccessor(MachineBasicBlock *Old,
551 MachineBasicBlock *New) {
555 succ_iterator E = succ_end();
556 succ_iterator NewI = E;
557 succ_iterator OldI = E;
558 for (succ_iterator I = succ_begin(); I != E; ++I) {
570 assert(OldI != E && "Old is not a successor of this block");
571 Old->removePredecessor(this);
573 // If New isn't already a successor, let it take Old's place.
575 New->addPredecessor(this);
580 // New is already a successor.
581 // Update its weight instead of adding a duplicate edge.
582 if (!Weights.empty()) {
583 weight_iterator OldWI = getWeightIterator(OldI);
584 *getWeightIterator(NewI) += *OldWI;
585 Weights.erase(OldWI);
587 Successors.erase(OldI);
590 void MachineBasicBlock::addPredecessor(MachineBasicBlock *Pred) {
591 Predecessors.push_back(Pred);
594 void MachineBasicBlock::removePredecessor(MachineBasicBlock *Pred) {
595 pred_iterator I = std::find(Predecessors.begin(), Predecessors.end(), Pred);
596 assert(I != Predecessors.end() && "Pred is not a predecessor of this block!");
597 Predecessors.erase(I);
600 void MachineBasicBlock::transferSuccessors(MachineBasicBlock *FromMBB) {
604 while (!FromMBB->succ_empty()) {
605 MachineBasicBlock *Succ = *FromMBB->succ_begin();
608 // If Weight list is empty it means we don't use it (disabled optimization).
609 if (!FromMBB->Weights.empty())
610 Weight = *FromMBB->Weights.begin();
612 addSuccessor(Succ, Weight);
613 FromMBB->removeSuccessor(Succ);
618 MachineBasicBlock::transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB) {
622 while (!FromMBB->succ_empty()) {
623 MachineBasicBlock *Succ = *FromMBB->succ_begin();
625 if (!FromMBB->Weights.empty())
626 Weight = *FromMBB->Weights.begin();
627 addSuccessor(Succ, Weight);
628 FromMBB->removeSuccessor(Succ);
630 // Fix up any PHI nodes in the successor.
631 for (MachineBasicBlock::instr_iterator MI = Succ->instr_begin(),
632 ME = Succ->instr_end(); MI != ME && MI->isPHI(); ++MI)
633 for (unsigned i = 2, e = MI->getNumOperands()+1; i != e; i += 2) {
634 MachineOperand &MO = MI->getOperand(i);
635 if (MO.getMBB() == FromMBB)
641 bool MachineBasicBlock::isPredecessor(const MachineBasicBlock *MBB) const {
642 return std::find(pred_begin(), pred_end(), MBB) != pred_end();
645 bool MachineBasicBlock::isSuccessor(const MachineBasicBlock *MBB) const {
646 return std::find(succ_begin(), succ_end(), MBB) != succ_end();
649 bool MachineBasicBlock::isLayoutSuccessor(const MachineBasicBlock *MBB) const {
650 MachineFunction::const_iterator I(this);
651 return std::next(I) == MachineFunction::const_iterator(MBB);
654 bool MachineBasicBlock::canFallThrough() {
655 MachineFunction::iterator Fallthrough = getIterator();
657 // If FallthroughBlock is off the end of the function, it can't fall through.
658 if (Fallthrough == getParent()->end())
661 // If FallthroughBlock isn't a successor, no fallthrough is possible.
662 if (!isSuccessor(&*Fallthrough))
665 // Analyze the branches, if any, at the end of the block.
666 MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
667 SmallVector<MachineOperand, 4> Cond;
668 const TargetInstrInfo *TII = getParent()->getSubtarget().getInstrInfo();
669 if (TII->AnalyzeBranch(*this, TBB, FBB, Cond)) {
670 // If we couldn't analyze the branch, examine the last instruction.
671 // If the block doesn't end in a known control barrier, assume fallthrough
672 // is possible. The isPredicated check is needed because this code can be
673 // called during IfConversion, where an instruction which is normally a
674 // Barrier is predicated and thus no longer an actual control barrier.
675 return empty() || !back().isBarrier() || TII->isPredicated(&back());
678 // If there is no branch, control always falls through.
679 if (!TBB) return true;
681 // If there is some explicit branch to the fallthrough block, it can obviously
682 // reach, even though the branch should get folded to fall through implicitly.
683 if (MachineFunction::iterator(TBB) == Fallthrough ||
684 MachineFunction::iterator(FBB) == Fallthrough)
687 // If it's an unconditional branch to some block not the fall through, it
688 // doesn't fall through.
689 if (Cond.empty()) return false;
691 // Otherwise, if it is conditional and has no explicit false block, it falls
693 return FBB == nullptr;
697 MachineBasicBlock::SplitCriticalEdge(MachineBasicBlock *Succ, Pass *P) {
698 // Splitting the critical edge to a landing pad block is non-trivial. Don't do
699 // it in this generic function.
703 MachineFunction *MF = getParent();
704 DebugLoc DL; // FIXME: this is nowhere
706 // Performance might be harmed on HW that implements branching using exec mask
707 // where both sides of the branches are always executed.
708 if (MF->getTarget().requiresStructuredCFG())
711 // We may need to update this's terminator, but we can't do that if
712 // AnalyzeBranch fails. If this uses a jump table, we won't touch it.
713 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
714 MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
715 SmallVector<MachineOperand, 4> Cond;
716 if (TII->AnalyzeBranch(*this, TBB, FBB, Cond))
719 // Avoid bugpoint weirdness: A block may end with a conditional branch but
720 // jumps to the same MBB is either case. We have duplicate CFG edges in that
721 // case that we can't handle. Since this never happens in properly optimized
722 // code, just skip those edges.
723 if (TBB && TBB == FBB) {
724 DEBUG(dbgs() << "Won't split critical edge after degenerate BB#"
725 << getNumber() << '\n');
729 MachineBasicBlock *NMBB = MF->CreateMachineBasicBlock();
730 MF->insert(std::next(MachineFunction::iterator(this)), NMBB);
731 DEBUG(dbgs() << "Splitting critical edge:"
732 " BB#" << getNumber()
733 << " -- BB#" << NMBB->getNumber()
734 << " -- BB#" << Succ->getNumber() << '\n');
736 LiveIntervals *LIS = P->getAnalysisIfAvailable<LiveIntervals>();
737 SlotIndexes *Indexes = P->getAnalysisIfAvailable<SlotIndexes>();
739 LIS->insertMBBInMaps(NMBB);
741 Indexes->insertMBBInMaps(NMBB);
743 // On some targets like Mips, branches may kill virtual registers. Make sure
744 // that LiveVariables is properly updated after updateTerminator replaces the
746 LiveVariables *LV = P->getAnalysisIfAvailable<LiveVariables>();
748 // Collect a list of virtual registers killed by the terminators.
749 SmallVector<unsigned, 4> KilledRegs;
751 for (instr_iterator I = getFirstInstrTerminator(), E = instr_end();
753 MachineInstr *MI = &*I;
754 for (MachineInstr::mop_iterator OI = MI->operands_begin(),
755 OE = MI->operands_end(); OI != OE; ++OI) {
756 if (!OI->isReg() || OI->getReg() == 0 ||
757 !OI->isUse() || !OI->isKill() || OI->isUndef())
759 unsigned Reg = OI->getReg();
760 if (TargetRegisterInfo::isPhysicalRegister(Reg) ||
761 LV->getVarInfo(Reg).removeKill(MI)) {
762 KilledRegs.push_back(Reg);
763 DEBUG(dbgs() << "Removing terminator kill: " << *MI);
764 OI->setIsKill(false);
769 SmallVector<unsigned, 4> UsedRegs;
771 for (instr_iterator I = getFirstInstrTerminator(), E = instr_end();
773 MachineInstr *MI = &*I;
775 for (MachineInstr::mop_iterator OI = MI->operands_begin(),
776 OE = MI->operands_end(); OI != OE; ++OI) {
777 if (!OI->isReg() || OI->getReg() == 0)
780 unsigned Reg = OI->getReg();
781 if (std::find(UsedRegs.begin(), UsedRegs.end(), Reg) == UsedRegs.end())
782 UsedRegs.push_back(Reg);
787 ReplaceUsesOfBlockWith(Succ, NMBB);
789 // If updateTerminator() removes instructions, we need to remove them from
791 SmallVector<MachineInstr*, 4> Terminators;
793 for (instr_iterator I = getFirstInstrTerminator(), E = instr_end();
795 Terminators.push_back(&*I);
801 SmallVector<MachineInstr*, 4> NewTerminators;
802 for (instr_iterator I = getFirstInstrTerminator(), E = instr_end();
804 NewTerminators.push_back(&*I);
806 for (SmallVectorImpl<MachineInstr*>::iterator I = Terminators.begin(),
807 E = Terminators.end(); I != E; ++I) {
808 if (std::find(NewTerminators.begin(), NewTerminators.end(), *I) ==
809 NewTerminators.end())
810 Indexes->removeMachineInstrFromMaps(*I);
814 // Insert unconditional "jump Succ" instruction in NMBB if necessary.
815 NMBB->addSuccessor(Succ);
816 if (!NMBB->isLayoutSuccessor(Succ)) {
818 TII->InsertBranch(*NMBB, Succ, nullptr, Cond, DL);
821 for (instr_iterator I = NMBB->instr_begin(), E = NMBB->instr_end();
823 // Some instructions may have been moved to NMBB by updateTerminator(),
824 // so we first remove any instruction that already has an index.
825 if (Indexes->hasIndex(&*I))
826 Indexes->removeMachineInstrFromMaps(&*I);
827 Indexes->insertMachineInstrInMaps(&*I);
832 // Fix PHI nodes in Succ so they refer to NMBB instead of this
833 for (MachineBasicBlock::instr_iterator
834 i = Succ->instr_begin(),e = Succ->instr_end();
835 i != e && i->isPHI(); ++i)
836 for (unsigned ni = 1, ne = i->getNumOperands(); ni != ne; ni += 2)
837 if (i->getOperand(ni+1).getMBB() == this)
838 i->getOperand(ni+1).setMBB(NMBB);
840 // Inherit live-ins from the successor
841 for (const auto &LI : Succ->liveins())
844 // Update LiveVariables.
845 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
847 // Restore kills of virtual registers that were killed by the terminators.
848 while (!KilledRegs.empty()) {
849 unsigned Reg = KilledRegs.pop_back_val();
850 for (instr_iterator I = instr_end(), E = instr_begin(); I != E;) {
851 if (!(--I)->addRegisterKilled(Reg, TRI, /* addIfNotFound= */ false))
853 if (TargetRegisterInfo::isVirtualRegister(Reg))
854 LV->getVarInfo(Reg).Kills.push_back(&*I);
855 DEBUG(dbgs() << "Restored terminator kill: " << *I);
859 // Update relevant live-through information.
860 LV->addNewBlock(NMBB, this, Succ);
864 // After splitting the edge and updating SlotIndexes, live intervals may be
865 // in one of two situations, depending on whether this block was the last in
866 // the function. If the original block was the last in the function, all
867 // live intervals will end prior to the beginning of the new split block. If
868 // the original block was not at the end of the function, all live intervals
869 // will extend to the end of the new split block.
872 std::next(MachineFunction::iterator(NMBB)) == getParent()->end();
874 SlotIndex StartIndex = Indexes->getMBBEndIdx(this);
875 SlotIndex PrevIndex = StartIndex.getPrevSlot();
876 SlotIndex EndIndex = Indexes->getMBBEndIdx(NMBB);
878 // Find the registers used from NMBB in PHIs in Succ.
879 SmallSet<unsigned, 8> PHISrcRegs;
880 for (MachineBasicBlock::instr_iterator
881 I = Succ->instr_begin(), E = Succ->instr_end();
882 I != E && I->isPHI(); ++I) {
883 for (unsigned ni = 1, ne = I->getNumOperands(); ni != ne; ni += 2) {
884 if (I->getOperand(ni+1).getMBB() == NMBB) {
885 MachineOperand &MO = I->getOperand(ni);
886 unsigned Reg = MO.getReg();
887 PHISrcRegs.insert(Reg);
891 LiveInterval &LI = LIS->getInterval(Reg);
892 VNInfo *VNI = LI.getVNInfoAt(PrevIndex);
894 "PHI sources should be live out of their predecessors.");
895 LI.addSegment(LiveInterval::Segment(StartIndex, EndIndex, VNI));
900 MachineRegisterInfo *MRI = &getParent()->getRegInfo();
901 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
902 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
903 if (PHISrcRegs.count(Reg) || !LIS->hasInterval(Reg))
906 LiveInterval &LI = LIS->getInterval(Reg);
907 if (!LI.liveAt(PrevIndex))
910 bool isLiveOut = LI.liveAt(LIS->getMBBStartIdx(Succ));
911 if (isLiveOut && isLastMBB) {
912 VNInfo *VNI = LI.getVNInfoAt(PrevIndex);
913 assert(VNI && "LiveInterval should have VNInfo where it is live.");
914 LI.addSegment(LiveInterval::Segment(StartIndex, EndIndex, VNI));
915 } else if (!isLiveOut && !isLastMBB) {
916 LI.removeSegment(StartIndex, EndIndex);
920 // Update all intervals for registers whose uses may have been modified by
921 // updateTerminator().
922 LIS->repairIntervalsInRange(this, getFirstTerminator(), end(), UsedRegs);
925 if (MachineDominatorTree *MDT =
926 P->getAnalysisIfAvailable<MachineDominatorTree>())
927 MDT->recordSplitCriticalEdge(this, Succ, NMBB);
929 if (MachineLoopInfo *MLI = P->getAnalysisIfAvailable<MachineLoopInfo>())
930 if (MachineLoop *TIL = MLI->getLoopFor(this)) {
931 // If one or the other blocks were not in a loop, the new block is not
932 // either, and thus LI doesn't need to be updated.
933 if (MachineLoop *DestLoop = MLI->getLoopFor(Succ)) {
934 if (TIL == DestLoop) {
935 // Both in the same loop, the NMBB joins loop.
936 DestLoop->addBasicBlockToLoop(NMBB, MLI->getBase());
937 } else if (TIL->contains(DestLoop)) {
938 // Edge from an outer loop to an inner loop. Add to the outer loop.
939 TIL->addBasicBlockToLoop(NMBB, MLI->getBase());
940 } else if (DestLoop->contains(TIL)) {
941 // Edge from an inner loop to an outer loop. Add to the outer loop.
942 DestLoop->addBasicBlockToLoop(NMBB, MLI->getBase());
944 // Edge from two loops with no containment relation. Because these
945 // are natural loops, we know that the destination block must be the
946 // header of its loop (adding a branch into a loop elsewhere would
947 // create an irreducible loop).
948 assert(DestLoop->getHeader() == Succ &&
949 "Should not create irreducible loops!");
950 if (MachineLoop *P = DestLoop->getParentLoop())
951 P->addBasicBlockToLoop(NMBB, MLI->getBase());
959 /// Prepare MI to be removed from its bundle. This fixes bundle flags on MI's
960 /// neighboring instructions so the bundle won't be broken by removing MI.
961 static void unbundleSingleMI(MachineInstr *MI) {
962 // Removing the first instruction in a bundle.
963 if (MI->isBundledWithSucc() && !MI->isBundledWithPred())
964 MI->unbundleFromSucc();
965 // Removing the last instruction in a bundle.
966 if (MI->isBundledWithPred() && !MI->isBundledWithSucc())
967 MI->unbundleFromPred();
968 // If MI is not bundled, or if it is internal to a bundle, the neighbor flags
972 MachineBasicBlock::instr_iterator
973 MachineBasicBlock::erase(MachineBasicBlock::instr_iterator I) {
974 unbundleSingleMI(&*I);
975 return Insts.erase(I);
978 MachineInstr *MachineBasicBlock::remove_instr(MachineInstr *MI) {
979 unbundleSingleMI(MI);
980 MI->clearFlag(MachineInstr::BundledPred);
981 MI->clearFlag(MachineInstr::BundledSucc);
982 return Insts.remove(MI);
985 MachineBasicBlock::instr_iterator
986 MachineBasicBlock::insert(instr_iterator I, MachineInstr *MI) {
987 assert(!MI->isBundledWithPred() && !MI->isBundledWithSucc() &&
988 "Cannot insert instruction with bundle flags");
989 // Set the bundle flags when inserting inside a bundle.
990 if (I != instr_end() && I->isBundledWithPred()) {
991 MI->setFlag(MachineInstr::BundledPred);
992 MI->setFlag(MachineInstr::BundledSucc);
994 return Insts.insert(I, MI);
997 /// This method unlinks 'this' from the containing function, and returns it, but
998 /// does not delete it.
999 MachineBasicBlock *MachineBasicBlock::removeFromParent() {
1000 assert(getParent() && "Not embedded in a function!");
1001 getParent()->remove(this);
1005 /// This method unlinks 'this' from the containing function, and deletes it.
1006 void MachineBasicBlock::eraseFromParent() {
1007 assert(getParent() && "Not embedded in a function!");
1008 getParent()->erase(this);
1011 /// Given a machine basic block that branched to 'Old', change the code and CFG
1012 /// so that it branches to 'New' instead.
1013 void MachineBasicBlock::ReplaceUsesOfBlockWith(MachineBasicBlock *Old,
1014 MachineBasicBlock *New) {
1015 assert(Old != New && "Cannot replace self with self!");
1017 MachineBasicBlock::instr_iterator I = instr_end();
1018 while (I != instr_begin()) {
1020 if (!I->isTerminator()) break;
1022 // Scan the operands of this machine instruction, replacing any uses of Old
1024 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i)
1025 if (I->getOperand(i).isMBB() &&
1026 I->getOperand(i).getMBB() == Old)
1027 I->getOperand(i).setMBB(New);
1030 // Update the successor information.
1031 replaceSuccessor(Old, New);
1034 /// Various pieces of code can cause excess edges in the CFG to be inserted. If
1035 /// we have proven that MBB can only branch to DestA and DestB, remove any other
1036 /// MBB successors from the CFG. DestA and DestB can be null.
1038 /// Besides DestA and DestB, retain other edges leading to LandingPads
1039 /// (currently there can be only one; we don't check or require that here).
1040 /// Note it is possible that DestA and/or DestB are LandingPads.
1041 bool MachineBasicBlock::CorrectExtraCFGEdges(MachineBasicBlock *DestA,
1042 MachineBasicBlock *DestB,
1044 // The values of DestA and DestB frequently come from a call to the
1045 // 'TargetInstrInfo::AnalyzeBranch' method. We take our meaning of the initial
1046 // values from there.
1048 // 1. If both DestA and DestB are null, then the block ends with no branches
1049 // (it falls through to its successor).
1050 // 2. If DestA is set, DestB is null, and IsCond is false, then the block ends
1051 // with only an unconditional branch.
1052 // 3. If DestA is set, DestB is null, and IsCond is true, then the block ends
1053 // with a conditional branch that falls through to a successor (DestB).
1054 // 4. If DestA and DestB is set and IsCond is true, then the block ends with a
1055 // conditional branch followed by an unconditional branch. DestA is the
1056 // 'true' destination and DestB is the 'false' destination.
1058 bool Changed = false;
1060 MachineFunction::iterator FallThru = std::next(getIterator());
1062 if (!DestA && !DestB) {
1063 // Block falls through to successor.
1066 } else if (DestA && !DestB) {
1068 // Block ends in conditional jump that falls through to successor.
1071 assert(DestA && DestB && IsCond &&
1072 "CFG in a bad state. Cannot correct CFG edges");
1075 // Remove superfluous edges. I.e., those which aren't destinations of this
1076 // basic block, duplicate edges, or landing pads.
1077 SmallPtrSet<const MachineBasicBlock*, 8> SeenMBBs;
1078 MachineBasicBlock::succ_iterator SI = succ_begin();
1079 while (SI != succ_end()) {
1080 const MachineBasicBlock *MBB = *SI;
1081 if (!SeenMBBs.insert(MBB).second ||
1082 (MBB != DestA && MBB != DestB && !MBB->isEHPad())) {
1083 // This is a superfluous edge, remove it.
1084 SI = removeSuccessor(SI);
1094 /// Find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE
1095 /// instructions. Return UnknownLoc if there is none.
1097 MachineBasicBlock::findDebugLoc(instr_iterator MBBI) {
1099 instr_iterator E = instr_end();
1103 // Skip debug declarations, we don't want a DebugLoc from them.
1104 while (MBBI != E && MBBI->isDebugValue())
1107 DL = MBBI->getDebugLoc();
1111 /// Return weight of the edge from this block to MBB.
1112 uint32_t MachineBasicBlock::getSuccWeight(const_succ_iterator Succ) const {
1113 if (Weights.empty())
1116 return *getWeightIterator(Succ);
1119 /// Set successor weight of a given iterator.
1120 void MachineBasicBlock::setSuccWeight(succ_iterator I, uint32_t Weight) {
1121 if (Weights.empty())
1123 *getWeightIterator(I) = Weight;
1126 /// Return wight iterator corresonding to the I successor iterator.
1127 MachineBasicBlock::weight_iterator MachineBasicBlock::
1128 getWeightIterator(MachineBasicBlock::succ_iterator I) {
1129 assert(Weights.size() == Successors.size() && "Async weight list!");
1130 size_t index = std::distance(Successors.begin(), I);
1131 assert(index < Weights.size() && "Not a current successor!");
1132 return Weights.begin() + index;
1135 /// Return wight iterator corresonding to the I successor iterator.
1136 MachineBasicBlock::const_weight_iterator MachineBasicBlock::
1137 getWeightIterator(MachineBasicBlock::const_succ_iterator I) const {
1138 assert(Weights.size() == Successors.size() && "Async weight list!");
1139 const size_t index = std::distance(Successors.begin(), I);
1140 assert(index < Weights.size() && "Not a current successor!");
1141 return Weights.begin() + index;
1144 /// Return whether (physical) register "Reg" has been <def>ined and not <kill>ed
1145 /// as of just before "MI".
1147 /// Search is localised to a neighborhood of
1148 /// Neighborhood instructions before (searching for defs or kills) and N
1149 /// instructions after (searching just for defs) MI.
1150 MachineBasicBlock::LivenessQueryResult
1151 MachineBasicBlock::computeRegisterLiveness(const TargetRegisterInfo *TRI,
1152 unsigned Reg, const_iterator Before,
1153 unsigned Neighborhood) const {
1154 unsigned N = Neighborhood;
1156 // Start by searching backwards from Before, looking for kills, reads or defs.
1157 const_iterator I(Before);
1158 // If this is the first insn in the block, don't search backwards.
1163 MachineOperandIteratorBase::PhysRegInfo Analysis =
1164 ConstMIOperands(I).analyzePhysReg(Reg, TRI);
1166 if (Analysis.Defines)
1167 // Outputs happen after inputs so they take precedence if both are
1169 return Analysis.DefinesDead ? LQR_Dead : LQR_Live;
1171 if (Analysis.Kills || Analysis.Clobbers)
1172 // Register killed, so isn't live.
1175 else if (Analysis.ReadsOverlap)
1176 // Defined or read without a previous kill - live.
1177 return Analysis.Reads ? LQR_Live : LQR_OverlappingLive;
1179 } while (I != begin() && --N > 0);
1182 // Did we get to the start of the block?
1184 // If so, the register's state is definitely defined by the live-in state.
1185 for (MCRegAliasIterator RAI(Reg, TRI, /*IncludeSelf=*/true);
1186 RAI.isValid(); ++RAI) {
1188 return (*RAI == Reg) ? LQR_Live : LQR_OverlappingLive;
1196 // Try searching forwards from Before, looking for reads or defs.
1197 I = const_iterator(Before);
1198 // If this is the last insn in the block, don't search forwards.
1200 for (++I; I != end() && N > 0; ++I, --N) {
1201 MachineOperandIteratorBase::PhysRegInfo Analysis =
1202 ConstMIOperands(I).analyzePhysReg(Reg, TRI);
1204 if (Analysis.ReadsOverlap)
1205 // Used, therefore must have been live.
1206 return (Analysis.Reads) ?
1207 LQR_Live : LQR_OverlappingLive;
1209 else if (Analysis.Clobbers || Analysis.Defines)
1210 // Defined (but not read) therefore cannot have been live.
1215 // At this point we have no idea of the liveness of the register.