1 //===- MIRPrinter.cpp - MIR serialization format printer ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the class that prints out the LLVM IR and machine
11 // functions using the MIR serialization format.
13 //===----------------------------------------------------------------------===//
15 #include "MIRPrinter.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/CodeGen/MachineConstantPool.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineMemOperand.h"
21 #include "llvm/CodeGen/MachineModuleInfo.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/MIRYamlMapping.h"
24 #include "llvm/IR/BasicBlock.h"
25 #include "llvm/IR/Constants.h"
26 #include "llvm/IR/Instructions.h"
27 #include "llvm/IR/IRPrintingPasses.h"
28 #include "llvm/IR/Module.h"
29 #include "llvm/IR/ModuleSlotTracker.h"
30 #include "llvm/Support/MemoryBuffer.h"
31 #include "llvm/Support/raw_ostream.h"
32 #include "llvm/Support/YAMLTraits.h"
33 #include "llvm/Target/TargetInstrInfo.h"
34 #include "llvm/Target/TargetSubtargetInfo.h"
40 /// This structure describes how to print out stack object references.
41 struct FrameIndexOperand {
46 FrameIndexOperand(StringRef Name, unsigned ID, bool IsFixed)
47 : Name(Name.str()), ID(ID), IsFixed(IsFixed) {}
49 /// Return an ordinary stack object reference.
50 static FrameIndexOperand create(StringRef Name, unsigned ID) {
51 return FrameIndexOperand(Name, ID, /*IsFixed=*/false);
54 /// Return a fixed stack object reference.
55 static FrameIndexOperand createFixed(unsigned ID) {
56 return FrameIndexOperand("", ID, /*IsFixed=*/true);
60 } // end anonymous namespace
64 /// This class prints out the machine functions using the MIR serialization
68 DenseMap<const uint32_t *, unsigned> RegisterMaskIds;
69 /// Maps from stack object indices to operand indices which will be used when
70 /// printing frame index machine operands.
71 DenseMap<int, FrameIndexOperand> StackObjectOperandMapping;
74 MIRPrinter(raw_ostream &OS) : OS(OS) {}
76 void print(const MachineFunction &MF);
78 void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo,
79 const TargetRegisterInfo *TRI);
80 void convert(ModuleSlotTracker &MST, yaml::MachineFrameInfo &YamlMFI,
81 const MachineFrameInfo &MFI);
82 void convert(yaml::MachineFunction &MF,
83 const MachineConstantPool &ConstantPool);
84 void convert(ModuleSlotTracker &MST, yaml::MachineJumpTable &YamlJTI,
85 const MachineJumpTableInfo &JTI);
86 void convertStackObjects(yaml::MachineFunction &MF,
87 const MachineFrameInfo &MFI, MachineModuleInfo &MMI,
88 ModuleSlotTracker &MST,
89 const TargetRegisterInfo *TRI);
92 void initRegisterMaskIds(const MachineFunction &MF);
95 /// This class prints out the machine instructions using the MIR serialization
99 ModuleSlotTracker &MST;
100 const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds;
101 const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping;
104 MIPrinter(raw_ostream &OS, ModuleSlotTracker &MST,
105 const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds,
106 const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping)
107 : OS(OS), MST(MST), RegisterMaskIds(RegisterMaskIds),
108 StackObjectOperandMapping(StackObjectOperandMapping) {}
110 void print(const MachineBasicBlock &MBB);
112 void print(const MachineInstr &MI);
113 void printMBBReference(const MachineBasicBlock &MBB);
114 void printIRBlockReference(const BasicBlock &BB);
115 void printIRValueReference(const Value &V);
116 void printStackObjectReference(int FrameIndex);
117 void printOffset(int64_t Offset);
118 void printTargetFlags(const MachineOperand &Op);
119 void print(const MachineOperand &Op, const TargetRegisterInfo *TRI,
120 unsigned I, bool ShouldPrintRegisterTies, bool IsDef = false);
121 void print(const MachineMemOperand &Op);
123 void print(const MCCFIInstruction &CFI, const TargetRegisterInfo *TRI);
126 } // end namespace llvm
131 /// This struct serializes the LLVM IR module.
132 template <> struct BlockScalarTraits<Module> {
133 static void output(const Module &Mod, void *Ctxt, raw_ostream &OS) {
134 Mod.print(OS, nullptr);
136 static StringRef input(StringRef Str, void *Ctxt, Module &Mod) {
137 llvm_unreachable("LLVM Module is supposed to be parsed separately");
142 } // end namespace yaml
143 } // end namespace llvm
145 static void printReg(unsigned Reg, raw_ostream &OS,
146 const TargetRegisterInfo *TRI) {
147 // TODO: Print Stack Slots.
150 else if (TargetRegisterInfo::isVirtualRegister(Reg))
151 OS << '%' << TargetRegisterInfo::virtReg2Index(Reg);
152 else if (Reg < TRI->getNumRegs())
153 OS << '%' << StringRef(TRI->getName(Reg)).lower();
155 llvm_unreachable("Can't print this kind of register yet");
158 static void printReg(unsigned Reg, yaml::StringValue &Dest,
159 const TargetRegisterInfo *TRI) {
160 raw_string_ostream OS(Dest.Value);
161 printReg(Reg, OS, TRI);
164 void MIRPrinter::print(const MachineFunction &MF) {
165 initRegisterMaskIds(MF);
167 yaml::MachineFunction YamlMF;
168 YamlMF.Name = MF.getName();
169 YamlMF.Alignment = MF.getAlignment();
170 YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
171 YamlMF.HasInlineAsm = MF.hasInlineAsm();
172 convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
173 ModuleSlotTracker MST(MF.getFunction()->getParent());
174 MST.incorporateFunction(*MF.getFunction());
175 convert(MST, YamlMF.FrameInfo, *MF.getFrameInfo());
176 convertStackObjects(YamlMF, *MF.getFrameInfo(), MF.getMMI(), MST,
177 MF.getSubtarget().getRegisterInfo());
178 if (const auto *ConstantPool = MF.getConstantPool())
179 convert(YamlMF, *ConstantPool);
180 if (const auto *JumpTableInfo = MF.getJumpTableInfo())
181 convert(MST, YamlMF.JumpTableInfo, *JumpTableInfo);
182 raw_string_ostream StrOS(YamlMF.Body.Value.Value);
183 bool IsNewlineNeeded = false;
184 for (const auto &MBB : MF) {
187 MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
189 IsNewlineNeeded = true;
192 yaml::Output Out(OS);
196 void MIRPrinter::convert(yaml::MachineFunction &MF,
197 const MachineRegisterInfo &RegInfo,
198 const TargetRegisterInfo *TRI) {
199 MF.IsSSA = RegInfo.isSSA();
200 MF.TracksRegLiveness = RegInfo.tracksLiveness();
201 MF.TracksSubRegLiveness = RegInfo.subRegLivenessEnabled();
203 // Print the virtual register definitions.
204 for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) {
205 unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
206 yaml::VirtualRegisterDefinition VReg;
209 StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower();
210 unsigned PreferredReg = RegInfo.getSimpleHint(Reg);
212 printReg(PreferredReg, VReg.PreferredRegister, TRI);
213 MF.VirtualRegisters.push_back(VReg);
216 // Print the live ins.
217 for (auto I = RegInfo.livein_begin(), E = RegInfo.livein_end(); I != E; ++I) {
218 yaml::MachineFunctionLiveIn LiveIn;
219 printReg(I->first, LiveIn.Register, TRI);
221 printReg(I->second, LiveIn.VirtualRegister, TRI);
222 MF.LiveIns.push_back(LiveIn);
224 // The used physical register mask is printed as an inverted callee saved
226 const BitVector &UsedPhysRegMask = RegInfo.getUsedPhysRegsMask();
227 if (UsedPhysRegMask.none())
229 std::vector<yaml::FlowStringValue> CalleeSavedRegisters;
230 for (unsigned I = 0, E = UsedPhysRegMask.size(); I != E; ++I) {
231 if (!UsedPhysRegMask[I]) {
232 yaml::FlowStringValue Reg;
233 printReg(I, Reg, TRI);
234 CalleeSavedRegisters.push_back(Reg);
237 MF.CalleeSavedRegisters = CalleeSavedRegisters;
240 void MIRPrinter::convert(ModuleSlotTracker &MST,
241 yaml::MachineFrameInfo &YamlMFI,
242 const MachineFrameInfo &MFI) {
243 YamlMFI.IsFrameAddressTaken = MFI.isFrameAddressTaken();
244 YamlMFI.IsReturnAddressTaken = MFI.isReturnAddressTaken();
245 YamlMFI.HasStackMap = MFI.hasStackMap();
246 YamlMFI.HasPatchPoint = MFI.hasPatchPoint();
247 YamlMFI.StackSize = MFI.getStackSize();
248 YamlMFI.OffsetAdjustment = MFI.getOffsetAdjustment();
249 YamlMFI.MaxAlignment = MFI.getMaxAlignment();
250 YamlMFI.AdjustsStack = MFI.adjustsStack();
251 YamlMFI.HasCalls = MFI.hasCalls();
252 YamlMFI.MaxCallFrameSize = MFI.getMaxCallFrameSize();
253 YamlMFI.HasOpaqueSPAdjustment = MFI.hasOpaqueSPAdjustment();
254 YamlMFI.HasVAStart = MFI.hasVAStart();
255 YamlMFI.HasMustTailInVarArgFunc = MFI.hasMustTailInVarArgFunc();
256 if (MFI.getSavePoint()) {
257 raw_string_ostream StrOS(YamlMFI.SavePoint.Value);
258 MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
259 .printMBBReference(*MFI.getSavePoint());
261 if (MFI.getRestorePoint()) {
262 raw_string_ostream StrOS(YamlMFI.RestorePoint.Value);
263 MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
264 .printMBBReference(*MFI.getRestorePoint());
268 void MIRPrinter::convertStackObjects(yaml::MachineFunction &MF,
269 const MachineFrameInfo &MFI,
270 MachineModuleInfo &MMI,
271 ModuleSlotTracker &MST,
272 const TargetRegisterInfo *TRI) {
273 // Process fixed stack objects.
275 for (int I = MFI.getObjectIndexBegin(); I < 0; ++I) {
276 if (MFI.isDeadObjectIndex(I))
279 yaml::FixedMachineStackObject YamlObject;
281 YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
282 ? yaml::FixedMachineStackObject::SpillSlot
283 : yaml::FixedMachineStackObject::DefaultType;
284 YamlObject.Offset = MFI.getObjectOffset(I);
285 YamlObject.Size = MFI.getObjectSize(I);
286 YamlObject.Alignment = MFI.getObjectAlignment(I);
287 YamlObject.IsImmutable = MFI.isImmutableObjectIndex(I);
288 YamlObject.IsAliased = MFI.isAliasedObjectIndex(I);
289 MF.FixedStackObjects.push_back(YamlObject);
290 StackObjectOperandMapping.insert(
291 std::make_pair(I, FrameIndexOperand::createFixed(ID++)));
294 // Process ordinary stack objects.
296 for (int I = 0, E = MFI.getObjectIndexEnd(); I < E; ++I) {
297 if (MFI.isDeadObjectIndex(I))
300 yaml::MachineStackObject YamlObject;
302 if (const auto *Alloca = MFI.getObjectAllocation(I))
303 YamlObject.Name.Value =
304 Alloca->hasName() ? Alloca->getName() : "<unnamed alloca>";
305 YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
306 ? yaml::MachineStackObject::SpillSlot
307 : MFI.isVariableSizedObjectIndex(I)
308 ? yaml::MachineStackObject::VariableSized
309 : yaml::MachineStackObject::DefaultType;
310 YamlObject.Offset = MFI.getObjectOffset(I);
311 YamlObject.Size = MFI.getObjectSize(I);
312 YamlObject.Alignment = MFI.getObjectAlignment(I);
314 MF.StackObjects.push_back(YamlObject);
315 StackObjectOperandMapping.insert(std::make_pair(
316 I, FrameIndexOperand::create(YamlObject.Name.Value, ID++)));
319 for (const auto &CSInfo : MFI.getCalleeSavedInfo()) {
320 yaml::StringValue Reg;
321 printReg(CSInfo.getReg(), Reg, TRI);
322 auto StackObjectInfo = StackObjectOperandMapping.find(CSInfo.getFrameIdx());
323 assert(StackObjectInfo != StackObjectOperandMapping.end() &&
324 "Invalid stack object index");
325 const FrameIndexOperand &StackObject = StackObjectInfo->second;
326 if (StackObject.IsFixed)
327 MF.FixedStackObjects[StackObject.ID].CalleeSavedRegister = Reg;
329 MF.StackObjects[StackObject.ID].CalleeSavedRegister = Reg;
331 for (unsigned I = 0, E = MFI.getLocalFrameObjectCount(); I < E; ++I) {
332 auto LocalObject = MFI.getLocalFrameObjectMap(I);
333 auto StackObjectInfo = StackObjectOperandMapping.find(LocalObject.first);
334 assert(StackObjectInfo != StackObjectOperandMapping.end() &&
335 "Invalid stack object index");
336 const FrameIndexOperand &StackObject = StackObjectInfo->second;
337 assert(!StackObject.IsFixed && "Expected a locally mapped stack object");
338 MF.StackObjects[StackObject.ID].LocalOffset = LocalObject.second;
341 // Print the stack object references in the frame information class after
342 // converting the stack objects.
343 if (MFI.hasStackProtectorIndex()) {
344 raw_string_ostream StrOS(MF.FrameInfo.StackProtector.Value);
345 MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
346 .printStackObjectReference(MFI.getStackProtectorIndex());
349 // Print the debug variable information.
350 for (MachineModuleInfo::VariableDbgInfo &DebugVar :
351 MMI.getVariableDbgInfo()) {
352 auto StackObjectInfo = StackObjectOperandMapping.find(DebugVar.Slot);
353 assert(StackObjectInfo != StackObjectOperandMapping.end() &&
354 "Invalid stack object index");
355 const FrameIndexOperand &StackObject = StackObjectInfo->second;
356 assert(!StackObject.IsFixed && "Expected a non-fixed stack object");
357 auto &Object = MF.StackObjects[StackObject.ID];
359 raw_string_ostream StrOS(Object.DebugVar.Value);
360 DebugVar.Var->printAsOperand(StrOS, MST);
363 raw_string_ostream StrOS(Object.DebugExpr.Value);
364 DebugVar.Expr->printAsOperand(StrOS, MST);
367 raw_string_ostream StrOS(Object.DebugLoc.Value);
368 DebugVar.Loc->printAsOperand(StrOS, MST);
373 void MIRPrinter::convert(yaml::MachineFunction &MF,
374 const MachineConstantPool &ConstantPool) {
376 for (const MachineConstantPoolEntry &Constant : ConstantPool.getConstants()) {
377 // TODO: Serialize target specific constant pool entries.
378 if (Constant.isMachineConstantPoolEntry())
379 llvm_unreachable("Can't print target specific constant pool entries yet");
381 yaml::MachineConstantPoolValue YamlConstant;
383 raw_string_ostream StrOS(Str);
384 Constant.Val.ConstVal->printAsOperand(StrOS);
385 YamlConstant.ID = ID++;
386 YamlConstant.Value = StrOS.str();
387 YamlConstant.Alignment = Constant.getAlignment();
388 MF.Constants.push_back(YamlConstant);
392 void MIRPrinter::convert(ModuleSlotTracker &MST,
393 yaml::MachineJumpTable &YamlJTI,
394 const MachineJumpTableInfo &JTI) {
395 YamlJTI.Kind = JTI.getEntryKind();
397 for (const auto &Table : JTI.getJumpTables()) {
399 yaml::MachineJumpTable::Entry Entry;
401 for (const auto *MBB : Table.MBBs) {
402 raw_string_ostream StrOS(Str);
403 MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
404 .printMBBReference(*MBB);
405 Entry.Blocks.push_back(StrOS.str());
408 YamlJTI.Entries.push_back(Entry);
412 void MIRPrinter::initRegisterMaskIds(const MachineFunction &MF) {
413 const auto *TRI = MF.getSubtarget().getRegisterInfo();
415 for (const uint32_t *Mask : TRI->getRegMasks())
416 RegisterMaskIds.insert(std::make_pair(Mask, I++));
419 void MIPrinter::print(const MachineBasicBlock &MBB) {
420 assert(MBB.getNumber() >= 0 && "Invalid MBB number");
421 OS << "bb." << MBB.getNumber();
422 bool HasAttributes = false;
423 if (const auto *BB = MBB.getBasicBlock()) {
425 OS << "." << BB->getName();
427 HasAttributes = true;
429 int Slot = MST.getLocalSlot(BB);
431 OS << "<ir-block badref>";
433 OS << (Twine("%ir-block.") + Twine(Slot)).str();
436 if (MBB.hasAddressTaken()) {
437 OS << (HasAttributes ? ", " : " (");
438 OS << "address-taken";
439 HasAttributes = true;
441 if (MBB.isLandingPad()) {
442 OS << (HasAttributes ? ", " : " (");
444 HasAttributes = true;
446 if (MBB.getAlignment()) {
447 OS << (HasAttributes ? ", " : " (");
448 OS << "align " << MBB.getAlignment();
449 HasAttributes = true;
455 bool HasLineAttributes = false;
456 // Print the successors
457 if (!MBB.succ_empty()) {
458 OS.indent(2) << "successors: ";
459 for (auto I = MBB.succ_begin(), E = MBB.succ_end(); I != E; ++I) {
460 if (I != MBB.succ_begin())
462 printMBBReference(**I);
463 if (MBB.hasSuccessorWeights())
464 OS << '(' << MBB.getSuccWeight(I) << ')';
467 HasLineAttributes = true;
470 // Print the live in registers.
471 const auto *TRI = MBB.getParent()->getSubtarget().getRegisterInfo();
472 assert(TRI && "Expected target register info");
473 if (!MBB.livein_empty()) {
474 OS.indent(2) << "liveins: ";
475 for (auto I = MBB.livein_begin(), E = MBB.livein_end(); I != E; ++I) {
476 if (I != MBB.livein_begin())
478 printReg(*I, OS, TRI);
481 HasLineAttributes = true;
484 if (HasLineAttributes)
486 bool IsInBundle = false;
487 for (auto I = MBB.instr_begin(), E = MBB.instr_end(); I != E; ++I) {
488 const MachineInstr &MI = *I;
489 if (IsInBundle && !MI.isInsideBundle()) {
490 OS.indent(2) << "}\n";
493 OS.indent(IsInBundle ? 4 : 2);
495 if (!IsInBundle && MI.getFlag(MachineInstr::BundledSucc)) {
502 OS.indent(2) << "}\n";
505 /// Return true when an instruction has tied register that can't be determined
506 /// by the instruction's descriptor.
507 static bool hasComplexRegisterTies(const MachineInstr &MI) {
508 const MCInstrDesc &MCID = MI.getDesc();
509 for (unsigned I = 0, E = MI.getNumOperands(); I < E; ++I) {
510 const auto &Operand = MI.getOperand(I);
511 if (!Operand.isReg() || Operand.isDef())
512 // Ignore the defined registers as MCID marks only the uses as tied.
514 int ExpectedTiedIdx = MCID.getOperandConstraint(I, MCOI::TIED_TO);
515 int TiedIdx = Operand.isTied() ? int(MI.findTiedOperandIdx(I)) : -1;
516 if (ExpectedTiedIdx != TiedIdx)
522 void MIPrinter::print(const MachineInstr &MI) {
523 const auto &SubTarget = MI.getParent()->getParent()->getSubtarget();
524 const auto *TRI = SubTarget.getRegisterInfo();
525 assert(TRI && "Expected target register info");
526 const auto *TII = SubTarget.getInstrInfo();
527 assert(TII && "Expected target instruction info");
528 if (MI.isCFIInstruction())
529 assert(MI.getNumOperands() == 1 && "Expected 1 operand in CFI instruction");
531 bool ShouldPrintRegisterTies = hasComplexRegisterTies(MI);
532 unsigned I = 0, E = MI.getNumOperands();
533 for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() &&
534 !MI.getOperand(I).isImplicit();
538 print(MI.getOperand(I), TRI, I, ShouldPrintRegisterTies, /*IsDef=*/true);
543 if (MI.getFlag(MachineInstr::FrameSetup))
544 OS << "frame-setup ";
545 OS << TII->getName(MI.getOpcode());
549 bool NeedComma = false;
553 print(MI.getOperand(I), TRI, I, ShouldPrintRegisterTies);
557 if (MI.getDebugLoc()) {
560 OS << " debug-location ";
561 MI.getDebugLoc()->printAsOperand(OS, MST);
564 if (!MI.memoperands_empty()) {
566 bool NeedComma = false;
567 for (const auto *Op : MI.memoperands()) {
576 void MIPrinter::printMBBReference(const MachineBasicBlock &MBB) {
577 OS << "%bb." << MBB.getNumber();
578 if (const auto *BB = MBB.getBasicBlock()) {
580 OS << '.' << BB->getName();
584 static void printIRSlotNumber(raw_ostream &OS, int Slot) {
591 void MIPrinter::printIRBlockReference(const BasicBlock &BB) {
594 printLLVMNameWithoutPrefix(OS, BB.getName());
597 const Function *F = BB.getParent();
599 if (F == MST.getCurrentFunction()) {
600 Slot = MST.getLocalSlot(&BB);
602 ModuleSlotTracker CustomMST(F->getParent(),
603 /*ShouldInitializeAllMetadata=*/false);
604 CustomMST.incorporateFunction(*F);
605 Slot = CustomMST.getLocalSlot(&BB);
607 printIRSlotNumber(OS, Slot);
610 void MIPrinter::printIRValueReference(const Value &V) {
611 if (isa<GlobalValue>(V)) {
612 V.printAsOperand(OS, /*PrintType=*/false, MST);
617 printLLVMNameWithoutPrefix(OS, V.getName());
620 if (isa<Constant>(V)) {
621 // Machine memory operands can load/store to/from constant value pointers.
622 // TODO: Serialize the constant values.
623 OS << "<unserializable ir value>";
626 printIRSlotNumber(OS, MST.getLocalSlot(&V));
629 void MIPrinter::printStackObjectReference(int FrameIndex) {
630 auto ObjectInfo = StackObjectOperandMapping.find(FrameIndex);
631 assert(ObjectInfo != StackObjectOperandMapping.end() &&
632 "Invalid frame index");
633 const FrameIndexOperand &Operand = ObjectInfo->second;
634 if (Operand.IsFixed) {
635 OS << "%fixed-stack." << Operand.ID;
638 OS << "%stack." << Operand.ID;
639 if (!Operand.Name.empty())
640 OS << '.' << Operand.Name;
643 void MIPrinter::printOffset(int64_t Offset) {
647 OS << " - " << -Offset;
650 OS << " + " << Offset;
653 static const char *getTargetFlagName(const TargetInstrInfo *TII, unsigned TF) {
654 auto Flags = TII->getSerializableDirectMachineOperandTargetFlags();
655 for (const auto &I : Flags) {
663 void MIPrinter::printTargetFlags(const MachineOperand &Op) {
664 if (!Op.getTargetFlags())
667 Op.getParent()->getParent()->getParent()->getSubtarget().getInstrInfo();
668 assert(TII && "expected instruction info");
669 auto Flags = TII->decomposeMachineOperandsTargetFlags(Op.getTargetFlags());
670 OS << "target-flags(";
671 const bool HasDirectFlags = Flags.first;
672 const bool HasBitmaskFlags = Flags.second;
673 if (!HasDirectFlags && !HasBitmaskFlags) {
677 if (HasDirectFlags) {
678 if (const auto *Name = getTargetFlagName(TII, Flags.first))
681 OS << "<unknown target flag>";
683 if (!HasBitmaskFlags) {
687 bool IsCommaNeeded = HasDirectFlags;
688 unsigned BitMask = Flags.second;
689 auto BitMasks = TII->getSerializableBitmaskMachineOperandTargetFlags();
690 for (const auto &Mask : BitMasks) {
691 // Check if the flag's bitmask has the bits of the current mask set.
692 if ((BitMask & Mask.first) == Mask.first) {
695 IsCommaNeeded = true;
697 // Clear the bits which were serialized from the flag's bitmask.
698 BitMask &= ~(Mask.first);
702 // When the resulting flag's bitmask isn't zero, we know that we didn't
703 // serialize all of the bit flags.
706 OS << "<unknown bitmask target flag>";
711 static const char *getTargetIndexName(const MachineFunction &MF, int Index) {
712 const auto *TII = MF.getSubtarget().getInstrInfo();
713 assert(TII && "expected instruction info");
714 auto Indices = TII->getSerializableTargetIndices();
715 for (const auto &I : Indices) {
716 if (I.first == Index) {
723 void MIPrinter::print(const MachineOperand &Op, const TargetRegisterInfo *TRI,
724 unsigned I, bool ShouldPrintRegisterTies, bool IsDef) {
725 printTargetFlags(Op);
726 switch (Op.getType()) {
727 case MachineOperand::MO_Register:
729 OS << (Op.isDef() ? "implicit-def " : "implicit ");
730 else if (!IsDef && Op.isDef())
731 // Print the 'def' flag only when the operand is defined after '='.
733 if (Op.isInternalRead())
741 if (Op.isEarlyClobber())
742 OS << "early-clobber ";
745 printReg(Op.getReg(), OS, TRI);
746 // Print the sub register.
747 if (Op.getSubReg() != 0)
748 OS << ':' << TRI->getSubRegIndexName(Op.getSubReg());
749 if (ShouldPrintRegisterTies && Op.isTied() && !Op.isDef())
750 OS << "(tied-def " << Op.getParent()->findTiedOperandIdx(I) << ")";
752 case MachineOperand::MO_Immediate:
755 case MachineOperand::MO_CImmediate:
756 Op.getCImm()->printAsOperand(OS, /*PrintType=*/true, MST);
758 case MachineOperand::MO_FPImmediate:
759 Op.getFPImm()->printAsOperand(OS, /*PrintType=*/true, MST);
761 case MachineOperand::MO_MachineBasicBlock:
762 printMBBReference(*Op.getMBB());
764 case MachineOperand::MO_FrameIndex:
765 printStackObjectReference(Op.getIndex());
767 case MachineOperand::MO_ConstantPoolIndex:
768 OS << "%const." << Op.getIndex();
769 printOffset(Op.getOffset());
771 case MachineOperand::MO_TargetIndex: {
772 OS << "target-index(";
773 if (const auto *Name = getTargetIndexName(
774 *Op.getParent()->getParent()->getParent(), Op.getIndex()))
779 printOffset(Op.getOffset());
782 case MachineOperand::MO_JumpTableIndex:
783 OS << "%jump-table." << Op.getIndex();
785 case MachineOperand::MO_ExternalSymbol:
787 printLLVMNameWithoutPrefix(OS, Op.getSymbolName());
788 printOffset(Op.getOffset());
790 case MachineOperand::MO_GlobalAddress:
791 Op.getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
792 printOffset(Op.getOffset());
794 case MachineOperand::MO_BlockAddress:
795 OS << "blockaddress(";
796 Op.getBlockAddress()->getFunction()->printAsOperand(OS, /*PrintType=*/false,
799 printIRBlockReference(*Op.getBlockAddress()->getBasicBlock());
801 printOffset(Op.getOffset());
803 case MachineOperand::MO_RegisterMask: {
804 auto RegMaskInfo = RegisterMaskIds.find(Op.getRegMask());
805 if (RegMaskInfo != RegisterMaskIds.end())
806 OS << StringRef(TRI->getRegMaskNames()[RegMaskInfo->second]).lower();
808 llvm_unreachable("Can't print this machine register mask yet.");
811 case MachineOperand::MO_RegisterLiveOut: {
812 const uint32_t *RegMask = Op.getRegLiveOut();
814 bool IsCommaNeeded = false;
815 for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) {
816 if (RegMask[Reg / 32] & (1U << (Reg % 32))) {
819 printReg(Reg, OS, TRI);
820 IsCommaNeeded = true;
826 case MachineOperand::MO_Metadata:
827 Op.getMetadata()->printAsOperand(OS, MST);
829 case MachineOperand::MO_CFIIndex: {
830 const auto &MMI = Op.getParent()->getParent()->getParent()->getMMI();
831 print(MMI.getFrameInstructions()[Op.getCFIIndex()], TRI);
835 // TODO: Print the other machine operands.
836 llvm_unreachable("Can't print this machine operand at the moment");
840 void MIPrinter::print(const MachineMemOperand &Op) {
842 // TODO: Print operand's target specific flags.
845 if (Op.isNonTemporal())
846 OS << "non-temporal ";
847 if (Op.isInvariant())
852 assert(Op.isStore() && "Non load machine operand must be a store");
855 OS << Op.getSize() << (Op.isLoad() ? " from " : " into ");
856 if (const Value *Val = Op.getValue()) {
857 printIRValueReference(*Val);
859 const PseudoSourceValue *PVal = Op.getPseudoValue();
860 assert(PVal && "Expected a pseudo source value");
861 switch (PVal->kind()) {
862 case PseudoSourceValue::Stack:
865 case PseudoSourceValue::GOT:
868 case PseudoSourceValue::JumpTable:
871 case PseudoSourceValue::ConstantPool:
872 OS << "constant-pool";
874 case PseudoSourceValue::FixedStack:
875 printStackObjectReference(
876 cast<FixedStackPseudoSourceValue>(PVal)->getFrameIndex());
878 case PseudoSourceValue::GlobalValueCallEntry:
880 cast<GlobalValuePseudoSourceValue>(PVal)->getValue()->printAsOperand(
881 OS, /*PrintType=*/false, MST);
883 case PseudoSourceValue::ExternalSymbolCallEntry:
884 OS << "call-entry $";
885 printLLVMNameWithoutPrefix(
886 OS, cast<ExternalSymbolPseudoSourceValue>(PVal)->getSymbol());
890 printOffset(Op.getOffset());
891 if (Op.getBaseAlignment() != Op.getSize())
892 OS << ", align " << Op.getBaseAlignment();
893 auto AAInfo = Op.getAAInfo();
896 AAInfo.TBAA->printAsOperand(OS, MST);
899 OS << ", !alias.scope ";
900 AAInfo.Scope->printAsOperand(OS, MST);
902 if (AAInfo.NoAlias) {
904 AAInfo.NoAlias->printAsOperand(OS, MST);
906 if (Op.getRanges()) {
908 Op.getRanges()->printAsOperand(OS, MST);
913 static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS,
914 const TargetRegisterInfo *TRI) {
915 int Reg = TRI->getLLVMRegNum(DwarfReg, true);
920 printReg(Reg, OS, TRI);
923 void MIPrinter::print(const MCCFIInstruction &CFI,
924 const TargetRegisterInfo *TRI) {
925 switch (CFI.getOperation()) {
926 case MCCFIInstruction::OpSameValue:
927 OS << ".cfi_same_value ";
930 printCFIRegister(CFI.getRegister(), OS, TRI);
932 case MCCFIInstruction::OpOffset:
933 OS << ".cfi_offset ";
936 printCFIRegister(CFI.getRegister(), OS, TRI);
937 OS << ", " << CFI.getOffset();
939 case MCCFIInstruction::OpDefCfaRegister:
940 OS << ".cfi_def_cfa_register ";
943 printCFIRegister(CFI.getRegister(), OS, TRI);
945 case MCCFIInstruction::OpDefCfaOffset:
946 OS << ".cfi_def_cfa_offset ";
949 OS << CFI.getOffset();
951 case MCCFIInstruction::OpDefCfa:
952 OS << ".cfi_def_cfa ";
955 printCFIRegister(CFI.getRegister(), OS, TRI);
956 OS << ", " << CFI.getOffset();
959 // TODO: Print the other CFI Operations.
960 OS << "<unserializable cfi operation>";
965 void llvm::printMIR(raw_ostream &OS, const Module &M) {
966 yaml::Output Out(OS);
967 Out << const_cast<Module &>(M);
970 void llvm::printMIR(raw_ostream &OS, const MachineFunction &MF) {
971 MIRPrinter Printer(OS);