1 //===-- LowerSubregs.cpp - Subregister Lowering instruction pass ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #define DEBUG_TYPE "lowersubregs"
11 #include "llvm/CodeGen/Passes.h"
12 #include "llvm/Function.h"
13 #include "llvm/CodeGen/MachineFunctionPass.h"
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "llvm/CodeGen/MachineRegisterInfo.h"
16 #include "llvm/Target/TargetRegisterInfo.h"
17 #include "llvm/Target/TargetInstrInfo.h"
18 #include "llvm/Target/TargetMachine.h"
19 #include "llvm/Support/Debug.h"
20 #include "llvm/Support/Compiler.h"
24 struct VISIBILITY_HIDDEN LowerSubregsInstructionPass
25 : public MachineFunctionPass {
26 static char ID; // Pass identification, replacement for typeid
27 LowerSubregsInstructionPass() : MachineFunctionPass((intptr_t)&ID) {}
29 const char *getPassName() const {
30 return "Subregister lowering instruction pass";
33 void getAnalysisUsage(AnalysisUsage &AU) const {
37 /// runOnMachineFunction - pass entry point
38 bool runOnMachineFunction(MachineFunction&);
40 bool LowerExtract(MachineInstr *MI);
41 bool LowerInsert(MachineInstr *MI);
42 bool LowerSubregToReg(MachineInstr *MI);
45 char LowerSubregsInstructionPass::ID = 0;
48 FunctionPass *llvm::createLowerSubregsPass() {
49 return new LowerSubregsInstructionPass();
52 bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
53 MachineBasicBlock *MBB = MI->getParent();
54 MachineFunction &MF = *MBB->getParent();
55 const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo();
56 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
58 assert(MI->getOperand(0).isRegister() && MI->getOperand(0).isDef() &&
59 MI->getOperand(1).isRegister() && MI->getOperand(1).isUse() &&
60 MI->getOperand(2).isImmediate() && "Malformed extract_subreg");
62 unsigned DstReg = MI->getOperand(0).getReg();
63 unsigned SuperReg = MI->getOperand(1).getReg();
64 unsigned SubIdx = MI->getOperand(2).getImm();
65 unsigned SrcReg = TRI.getSubReg(SuperReg, SubIdx);
67 assert(TargetRegisterInfo::isPhysicalRegister(SuperReg) &&
68 "Extract supperg source must be a physical register");
69 assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
70 "Insert destination must be in a physical register");
72 DOUT << "subreg: CONVERTING: " << *MI;
74 if (SrcReg != DstReg) {
75 const TargetRegisterClass *TRC = TRI.getPhysicalRegisterRegClass(DstReg);
76 assert(TRC == TRI.getPhysicalRegisterRegClass(SrcReg) &&
77 "Extract subreg and Dst must be of same register class");
78 TII.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC, TRC);
81 MachineBasicBlock::iterator dMI = MI;
82 DOUT << "subreg: " << *(--dMI);
91 bool LowerSubregsInstructionPass::LowerSubregToReg(MachineInstr *MI) {
92 MachineBasicBlock *MBB = MI->getParent();
93 MachineFunction &MF = *MBB->getParent();
94 const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo();
95 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
96 assert((MI->getOperand(0).isRegister() && MI->getOperand(0).isDef()) &&
97 MI->getOperand(1).isImmediate() &&
98 (MI->getOperand(2).isRegister() && MI->getOperand(2).isUse()) &&
99 MI->getOperand(3).isImmediate() && "Invalid subreg_to_reg");
101 unsigned DstReg = MI->getOperand(0).getReg();
102 unsigned InsReg = MI->getOperand(2).getReg();
103 unsigned SubIdx = MI->getOperand(3).getImm();
105 assert(SubIdx != 0 && "Invalid index for insert_subreg");
106 unsigned DstSubReg = TRI.getSubReg(DstReg, SubIdx);
108 assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
109 "Insert destination must be in a physical register");
110 assert(TargetRegisterInfo::isPhysicalRegister(InsReg) &&
111 "Inserted value must be in a physical register");
113 DOUT << "subreg: CONVERTING: " << *MI;
115 // Insert sub-register copy
116 const TargetRegisterClass *TRC0 = TRI.getPhysicalRegisterRegClass(DstSubReg);
117 const TargetRegisterClass *TRC1 = TRI.getPhysicalRegisterRegClass(InsReg);
118 TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1);
121 MachineBasicBlock::iterator dMI = MI;
122 DOUT << "subreg: " << *(--dMI);
130 bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
131 MachineBasicBlock *MBB = MI->getParent();
132 MachineFunction &MF = *MBB->getParent();
133 const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo();
134 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
135 assert((MI->getOperand(0).isRegister() && MI->getOperand(0).isDef()) &&
136 (MI->getOperand(1).isRegister() && MI->getOperand(1).isUse()) &&
137 (MI->getOperand(2).isRegister() && MI->getOperand(2).isUse()) &&
138 MI->getOperand(3).isImmediate() && "Invalid insert_subreg");
140 unsigned DstReg = MI->getOperand(0).getReg();
141 unsigned SrcReg = MI->getOperand(1).getReg();
142 unsigned InsReg = MI->getOperand(2).getReg();
143 unsigned SubIdx = MI->getOperand(3).getImm();
145 assert(DstReg == SrcReg && "insert_subreg not a two-address instruction?");
146 assert(SubIdx != 0 && "Invalid index for insert_subreg");
147 unsigned DstSubReg = TRI.getSubReg(DstReg, SubIdx);
149 assert(TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
150 "Insert superreg source must be in a physical register");
151 assert(TargetRegisterInfo::isPhysicalRegister(InsReg) &&
152 "Inserted value must be in a physical register");
154 DOUT << "subreg: CONVERTING: " << *MI;
156 // Insert sub-register copy
157 const TargetRegisterClass *TRC0 = TRI.getPhysicalRegisterRegClass(DstSubReg);
158 const TargetRegisterClass *TRC1 = TRI.getPhysicalRegisterRegClass(InsReg);
159 TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1);
162 MachineBasicBlock::iterator dMI = MI;
163 DOUT << "subreg: " << *(--dMI);
171 /// runOnMachineFunction - Reduce subregister inserts and extracts to register
174 bool LowerSubregsInstructionPass::runOnMachineFunction(MachineFunction &MF) {
175 DOUT << "Machine Function\n";
177 bool MadeChange = false;
179 DOUT << "********** LOWERING SUBREG INSTRS **********\n";
180 DOUT << "********** Function: " << MF.getFunction()->getName() << '\n';
182 for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
183 mbbi != mbbe; ++mbbi) {
184 for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
186 MachineInstr *MI = mi++;
188 if (MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
189 MadeChange |= LowerExtract(MI);
190 } else if (MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG) {
191 MadeChange |= LowerInsert(MI);
192 } else if (MI->getOpcode() == TargetInstrInfo::SUBREG_TO_REG) {
193 MadeChange |= LowerSubregToReg(MI);