1 //===-- LowerSubregs.cpp - Subregister Lowering instruction pass ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a MachineFunction pass which runs after register
11 // allocation that turns subreg insert/extract instructions into register
12 // copies, as needed. This ensures correct codegen even if the coalescer
13 // isn't able to remove all subreg instructions.
15 //===----------------------------------------------------------------------===//
17 #define DEBUG_TYPE "lowersubregs"
18 #include "llvm/CodeGen/Passes.h"
19 #include "llvm/Function.h"
20 #include "llvm/CodeGen/MachineFunctionPass.h"
21 #include "llvm/CodeGen/MachineInstr.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/Target/TargetRegisterInfo.h"
25 #include "llvm/Target/TargetInstrInfo.h"
26 #include "llvm/Target/TargetMachine.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/raw_ostream.h"
32 struct LowerSubregsInstructionPass : public MachineFunctionPass {
34 const TargetRegisterInfo *TRI;
35 const TargetInstrInfo *TII;
38 static char ID; // Pass identification, replacement for typeid
39 LowerSubregsInstructionPass() : MachineFunctionPass(&ID) {}
41 const char *getPassName() const {
42 return "Subregister lowering instruction pass";
45 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
47 AU.addPreservedID(MachineLoopInfoID);
48 AU.addPreservedID(MachineDominatorsID);
49 MachineFunctionPass::getAnalysisUsage(AU);
52 /// runOnMachineFunction - pass entry point
53 bool runOnMachineFunction(MachineFunction&);
56 bool LowerExtract(MachineInstr *MI);
57 bool LowerInsert(MachineInstr *MI);
58 bool LowerSubregToReg(MachineInstr *MI);
59 bool LowerCopy(MachineInstr *MI);
61 void TransferDeadFlag(MachineInstr *MI, unsigned DstReg,
62 const TargetRegisterInfo *TRI);
63 void TransferKillFlag(MachineInstr *MI, unsigned SrcReg,
64 const TargetRegisterInfo *TRI,
65 bool AddIfNotFound = false);
66 void TransferImplicitDefs(MachineInstr *MI);
69 char LowerSubregsInstructionPass::ID = 0;
72 FunctionPass *llvm::createLowerSubregsPass() {
73 return new LowerSubregsInstructionPass();
76 /// TransferDeadFlag - MI is a pseudo-instruction with DstReg dead,
77 /// and the lowered replacement instructions immediately precede it.
78 /// Mark the replacement instructions with the dead flag.
80 LowerSubregsInstructionPass::TransferDeadFlag(MachineInstr *MI,
82 const TargetRegisterInfo *TRI) {
83 for (MachineBasicBlock::iterator MII =
84 prior(MachineBasicBlock::iterator(MI)); ; --MII) {
85 if (MII->addRegisterDead(DstReg, TRI))
87 assert(MII != MI->getParent()->begin() &&
88 "copyPhysReg output doesn't reference destination register!");
92 /// TransferKillFlag - MI is a pseudo-instruction with SrcReg killed,
93 /// and the lowered replacement instructions immediately precede it.
94 /// Mark the replacement instructions with the kill flag.
96 LowerSubregsInstructionPass::TransferKillFlag(MachineInstr *MI,
98 const TargetRegisterInfo *TRI,
100 for (MachineBasicBlock::iterator MII =
101 prior(MachineBasicBlock::iterator(MI)); ; --MII) {
102 if (MII->addRegisterKilled(SrcReg, TRI, AddIfNotFound))
104 assert(MII != MI->getParent()->begin() &&
105 "copyPhysReg output doesn't reference source register!");
109 /// TransferImplicitDefs - MI is a pseudo-instruction, and the lowered
110 /// replacement instructions immediately precede it. Copy any implicit-def
111 /// operands from MI to the replacement instruction.
113 LowerSubregsInstructionPass::TransferImplicitDefs(MachineInstr *MI) {
114 MachineBasicBlock::iterator CopyMI = MI;
117 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
118 MachineOperand &MO = MI->getOperand(i);
119 if (!MO.isReg() || !MO.isImplicit() || MO.isUse())
121 CopyMI->addOperand(MachineOperand::CreateReg(MO.getReg(), true, true));
125 bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
126 MachineBasicBlock *MBB = MI->getParent();
128 assert(MI->getOperand(0).isReg() && MI->getOperand(0).isDef() &&
129 MI->getOperand(1).isReg() && MI->getOperand(1).isUse() &&
130 MI->getOperand(2).isImm() && "Malformed extract_subreg");
132 unsigned DstReg = MI->getOperand(0).getReg();
133 unsigned SuperReg = MI->getOperand(1).getReg();
134 unsigned SubIdx = MI->getOperand(2).getImm();
135 unsigned SrcReg = TRI->getSubReg(SuperReg, SubIdx);
137 assert(TargetRegisterInfo::isPhysicalRegister(SuperReg) &&
138 "Extract supperg source must be a physical register");
139 assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
140 "Extract destination must be in a physical register");
141 assert(SrcReg && "invalid subregister index for register");
143 DEBUG(dbgs() << "subreg: CONVERTING: " << *MI);
145 if (SrcReg == DstReg) {
146 // No need to insert an identity copy instruction.
147 if (MI->getOperand(1).isKill()) {
148 // We must make sure the super-register gets killed. Replace the
149 // instruction with KILL.
150 MI->setDesc(TII->get(TargetOpcode::KILL));
151 MI->RemoveOperand(2); // SubIdx
152 DEBUG(dbgs() << "subreg: replace by: " << *MI);
156 DEBUG(dbgs() << "subreg: eliminated!");
158 TII->copyPhysReg(*MBB, MI, MI->getDebugLoc(), DstReg, SrcReg, false);
159 // Transfer the kill/dead flags, if needed.
160 if (MI->getOperand(0).isDead())
161 TransferDeadFlag(MI, DstReg, TRI);
162 if (MI->getOperand(1).isKill())
163 TransferKillFlag(MI, SuperReg, TRI, true);
164 TransferImplicitDefs(MI);
166 MachineBasicBlock::iterator dMI = MI;
167 dbgs() << "subreg: " << *(--dMI);
171 DEBUG(dbgs() << '\n');
176 bool LowerSubregsInstructionPass::LowerSubregToReg(MachineInstr *MI) {
177 MachineBasicBlock *MBB = MI->getParent();
178 assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
179 MI->getOperand(1).isImm() &&
180 (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
181 MI->getOperand(3).isImm() && "Invalid subreg_to_reg");
183 unsigned DstReg = MI->getOperand(0).getReg();
184 unsigned InsReg = MI->getOperand(2).getReg();
185 assert(!MI->getOperand(2).getSubReg() && "SubIdx on physreg?");
186 unsigned SubIdx = MI->getOperand(3).getImm();
188 assert(SubIdx != 0 && "Invalid index for insert_subreg");
189 unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx);
191 assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
192 "Insert destination must be in a physical register");
193 assert(TargetRegisterInfo::isPhysicalRegister(InsReg) &&
194 "Inserted value must be in a physical register");
196 DEBUG(dbgs() << "subreg: CONVERTING: " << *MI);
198 if (DstSubReg == InsReg) {
199 // No need to insert an identify copy instruction.
200 // Watch out for case like this:
201 // %RAX<def> = SUBREG_TO_REG 0, %EAX<kill>, 3
202 // We must leave %RAX live.
203 if (DstReg != InsReg) {
204 MI->setDesc(TII->get(TargetOpcode::KILL));
205 MI->RemoveOperand(3); // SubIdx
206 MI->RemoveOperand(1); // Imm
207 DEBUG(dbgs() << "subreg: replace by: " << *MI);
210 DEBUG(dbgs() << "subreg: eliminated!");
212 TII->copyPhysReg(*MBB, MI, MI->getDebugLoc(), DstSubReg, InsReg,
213 MI->getOperand(2).isKill());
214 // Transfer the kill/dead flags, if needed.
215 if (MI->getOperand(0).isDead())
216 TransferDeadFlag(MI, DstSubReg, TRI);
218 MachineBasicBlock::iterator dMI = MI;
219 dbgs() << "subreg: " << *(--dMI);
223 DEBUG(dbgs() << '\n');
228 bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
229 MachineBasicBlock *MBB = MI->getParent();
230 assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
231 (MI->getOperand(1).isReg() && MI->getOperand(1).isUse()) &&
232 (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
233 MI->getOperand(3).isImm() && "Invalid insert_subreg");
235 unsigned DstReg = MI->getOperand(0).getReg();
237 unsigned SrcReg = MI->getOperand(1).getReg();
239 unsigned InsReg = MI->getOperand(2).getReg();
240 unsigned SubIdx = MI->getOperand(3).getImm();
242 assert(DstReg == SrcReg && "insert_subreg not a two-address instruction?");
243 assert(SubIdx != 0 && "Invalid index for insert_subreg");
244 unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx);
245 assert(DstSubReg && "invalid subregister index for register");
246 assert(TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
247 "Insert superreg source must be in a physical register");
248 assert(TargetRegisterInfo::isPhysicalRegister(InsReg) &&
249 "Inserted value must be in a physical register");
251 DEBUG(dbgs() << "subreg: CONVERTING: " << *MI);
253 if (DstSubReg == InsReg) {
254 // No need to insert an identity copy instruction. If the SrcReg was
255 // <undef>, we need to make sure it is alive by inserting a KILL
256 if (MI->getOperand(1).isUndef() && !MI->getOperand(0).isDead()) {
257 MachineInstrBuilder MIB = BuildMI(*MBB, MI, MI->getDebugLoc(),
258 TII->get(TargetOpcode::KILL), DstReg);
259 if (MI->getOperand(2).isUndef())
260 MIB.addReg(InsReg, RegState::Undef);
262 MIB.addReg(InsReg, RegState::Kill);
264 DEBUG(dbgs() << "subreg: eliminated!\n");
269 // Insert sub-register copy
270 if (MI->getOperand(2).isUndef())
271 // If the source register being inserted is undef, then this becomes a
273 BuildMI(*MBB, MI, MI->getDebugLoc(),
274 TII->get(TargetOpcode::KILL), DstSubReg);
276 TII->copyPhysReg(*MBB, MI, MI->getDebugLoc(), DstSubReg, InsReg, false);
278 MachineBasicBlock::iterator CopyMI = MI;
281 // INSERT_SUBREG is a two-address instruction so it implicitly kills SrcReg.
282 if (!MI->getOperand(1).isUndef())
283 CopyMI->addOperand(MachineOperand::CreateReg(DstReg, false, true, true));
285 // Transfer the kill/dead flags, if needed.
286 if (MI->getOperand(0).isDead()) {
287 TransferDeadFlag(MI, DstSubReg, TRI);
289 // Make sure the full DstReg is live after this replacement.
290 CopyMI->addOperand(MachineOperand::CreateReg(DstReg, true, true));
293 // Make sure the inserted register gets killed
294 if (MI->getOperand(2).isKill() && !MI->getOperand(2).isUndef())
295 TransferKillFlag(MI, InsReg, TRI);
299 MachineBasicBlock::iterator dMI = MI;
300 dbgs() << "subreg: " << *(--dMI) << "\n";
307 bool LowerSubregsInstructionPass::LowerCopy(MachineInstr *MI) {
308 MachineOperand &DstMO = MI->getOperand(0);
309 MachineOperand &SrcMO = MI->getOperand(1);
311 if (SrcMO.getReg() == DstMO.getReg()) {
312 DEBUG(dbgs() << "identity copy: " << *MI);
313 // No need to insert an identity copy instruction, but replace with a KILL
314 // if liveness is changed.
315 if (DstMO.isDead() || SrcMO.isUndef() || MI->getNumOperands() > 2) {
316 // We must make sure the super-register gets killed. Replace the
317 // instruction with KILL.
318 MI->setDesc(TII->get(TargetOpcode::KILL));
319 DEBUG(dbgs() << "replaced by: " << *MI);
322 // Vanilla identity copy.
323 MI->eraseFromParent();
327 DEBUG(dbgs() << "real copy: " << *MI);
328 TII->copyPhysReg(*MI->getParent(), MI, MI->getDebugLoc(),
329 DstMO.getReg(), SrcMO.getReg(), SrcMO.isKill());
332 TransferDeadFlag(MI, DstMO.getReg(), TRI);
333 if (MI->getNumOperands() > 2)
334 TransferImplicitDefs(MI);
336 MachineBasicBlock::iterator dMI = MI;
337 dbgs() << "replaced by: " << *(--dMI);
339 MI->eraseFromParent();
343 /// runOnMachineFunction - Reduce subregister inserts and extracts to register
346 bool LowerSubregsInstructionPass::runOnMachineFunction(MachineFunction &MF) {
347 DEBUG(dbgs() << "Machine Function\n"
348 << "********** LOWERING SUBREG INSTRS **********\n"
349 << "********** Function: "
350 << MF.getFunction()->getName() << '\n');
351 TRI = MF.getTarget().getRegisterInfo();
352 TII = MF.getTarget().getInstrInfo();
354 bool MadeChange = false;
356 for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
357 mbbi != mbbe; ++mbbi) {
358 for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
360 MachineBasicBlock::iterator nmi = llvm::next(mi);
361 MachineInstr *MI = mi;
362 if (MI->isExtractSubreg()) {
363 MadeChange |= LowerExtract(MI);
364 } else if (MI->isInsertSubreg()) {
365 MadeChange |= LowerInsert(MI);
366 } else if (MI->isSubregToReg()) {
367 MadeChange |= LowerSubregToReg(MI);
368 } else if (MI->isCopy()) {
369 MadeChange |= LowerCopy(MI);