1 //===-- LowerSubregs.cpp - Subregister Lowering instruction pass ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Christopher Lamb and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #define DEBUG_TYPE "lowersubregs"
11 #include "llvm/CodeGen/Passes.h"
12 #include "llvm/Function.h"
13 #include "llvm/CodeGen/MachineFunctionPass.h"
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "llvm/CodeGen/SSARegMap.h"
16 #include "llvm/Target/MRegisterInfo.h"
17 #include "llvm/Target/TargetInstrInfo.h"
18 #include "llvm/Target/TargetMachine.h"
19 #include "llvm/Support/Debug.h"
20 #include "llvm/Support/Compiler.h"
24 struct VISIBILITY_HIDDEN LowerSubregsInstructionPass
25 : public MachineFunctionPass {
26 static char ID; // Pass identification, replacement for typeid
27 LowerSubregsInstructionPass() : MachineFunctionPass((intptr_t)&ID) {}
29 const char *getPassName() const {
30 return "Subregister lowering instruction pass";
33 /// runOnMachineFunction - pass entry point
34 bool runOnMachineFunction(MachineFunction&);
37 char LowerSubregsInstructionPass::ID = 0;
40 FunctionPass *llvm::createLowerSubregsPass() {
41 return new LowerSubregsInstructionPass();
44 // Returns the Register Class of a physical register
45 static const TargetRegisterClass *getPhysicalRegisterRegClass(
46 const MRegisterInfo &MRI,
48 assert(MRegisterInfo::isPhysicalRegister(reg) &&
49 "reg must be a physical register");
50 // Pick the register class of the right type that contains this physreg.
51 for (MRegisterInfo::regclass_iterator I = MRI.regclass_begin(),
52 E = MRI.regclass_end(); I != E; ++I)
53 if ((*I)->contains(reg))
55 assert(false && "Couldn't find the register class");
59 static bool isSubRegOf(const MRegisterInfo &MRI,
62 const TargetRegisterDesc &RD = MRI[SubReg];
63 for (const unsigned *reg = RD.SuperRegs; *reg != 0; ++reg)
71 /// runOnMachineFunction - Reduce subregister inserts and extracts to register
74 bool LowerSubregsInstructionPass::runOnMachineFunction(MachineFunction &MF) {
75 DOUT << "Machine Function\n";
76 const TargetMachine &TM = MF.getTarget();
77 const MRegisterInfo &MRI = *TM.getRegisterInfo();
79 bool MadeChange = false;
81 DOUT << "********** LOWERING SUBREG INSTRS **********\n";
82 DOUT << "********** Function: " << MF.getFunction()->getName() << '\n';
84 for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
85 mbbi != mbbe; ++mbbi) {
86 for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
89 if (mi->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
90 assert(mi->getOperand(0).isRegister() && mi->getOperand(0).isDef() &&
91 mi->getOperand(1).isRegister() && mi->getOperand(1).isUse() &&
92 mi->getOperand(2).isImm() && "Malformed extract_subreg");
94 unsigned SuperReg = mi->getOperand(1).getReg();
95 unsigned SubIdx = mi->getOperand(2).getImm();
97 assert(MRegisterInfo::isPhysicalRegister(SuperReg) &&
98 "Extract supperg source must be a physical register");
99 unsigned SrcReg = MRI.getSubReg(SuperReg, SubIdx);
100 unsigned DstReg = mi->getOperand(0).getReg();
102 DOUT << "subreg: CONVERTING: " << *mi;
104 if (SrcReg != DstReg) {
105 const TargetRegisterClass *TRC = 0;
106 if (MRegisterInfo::isPhysicalRegister(DstReg)) {
107 TRC = getPhysicalRegisterRegClass(MRI, DstReg);
109 TRC = MF.getSSARegMap()->getRegClass(DstReg);
111 assert(TRC == getPhysicalRegisterRegClass(MRI, SrcReg) &&
112 "Extract subreg and Dst must be of same register class");
114 MRI.copyRegToReg(*mbbi, mi, DstReg, SrcReg, TRC);
115 MachineBasicBlock::iterator dmi = mi;
116 DOUT << "subreg: " << *(--dmi);
123 } else if (mi->getOpcode() == TargetInstrInfo::INSERT_SUBREG) {
130 // If only have 3 operands, then the source superreg is undef
131 // and we can supress the copy from the undef value
132 if (mi->getNumOperands() == 3) {
133 assert((mi->getOperand(0).isRegister() && mi->getOperand(0).isDef()) &&
134 (mi->getOperand(1).isRegister() && mi->getOperand(1).isUse()) &&
135 mi->getOperand(2).isImm() && "Invalid extract_subreg");
136 DstReg = mi->getOperand(0).getReg();
138 InsReg = mi->getOperand(1).getReg();
139 SubIdx = mi->getOperand(2).getImm();
140 } else if (mi->getNumOperands() == 4) {
141 assert((mi->getOperand(0).isRegister() && mi->getOperand(0).isDef()) &&
142 (mi->getOperand(1).isRegister() && mi->getOperand(1).isUse()) &&
143 (mi->getOperand(2).isRegister() && mi->getOperand(2).isUse()) &&
144 mi->getOperand(3).isImm() && "Invalid extract_subreg");
145 DstReg = mi->getOperand(0).getReg();
146 SrcReg = mi->getOperand(1).getReg();
147 InsReg = mi->getOperand(2).getReg();
148 SubIdx = mi->getOperand(3).getImm();
150 assert(0 && "Malformed extract_subreg");
152 assert(SubIdx != 0 && "Invalid index for extract_subreg");
153 unsigned DstSubReg = MRI.getSubReg(DstReg, SubIdx);
155 assert(MRegisterInfo::isPhysicalRegister(SrcReg) &&
156 "Insert superreg source must be in a physical register");
157 assert(MRegisterInfo::isPhysicalRegister(DstReg) &&
158 "Insert destination must be in a physical register");
159 assert(MRegisterInfo::isPhysicalRegister(InsReg) &&
160 "Inserted value must be in a physical register");
162 DOUT << "subreg: CONVERTING: " << *mi;
164 // If the inserted register is already allocated into a subregister
165 // of the destination, we copy the subreg into the source
166 // However, this is only safe if the insert instruction is the kill
167 // of the source register
168 bool revCopyOrder = isSubRegOf(MRI, InsReg, DstReg);
170 if (mi->getOperand(1).isKill()) {
171 DstSubReg = MRI.getSubReg(SrcReg, SubIdx);
172 // Insert sub-register copy
173 const TargetRegisterClass *TRC1 = 0;
174 if (MRegisterInfo::isPhysicalRegister(InsReg)) {
175 TRC1 = getPhysicalRegisterRegClass(MRI, InsReg);
177 TRC1 = MF.getSSARegMap()->getRegClass(InsReg);
180 MRI.copyRegToReg(*mbbi, mi, DstSubReg, InsReg, TRC1);
181 MachineBasicBlock::iterator dmi = mi;
182 DOUT << "subreg: " << *(--dmi);
184 assert(0 && "Don't know how to convert this insert");
188 if (SrcReg != DstReg) {
189 // Insert super-register copy
190 const TargetRegisterClass *TRC0 = 0;
191 if (MRegisterInfo::isPhysicalRegister(DstReg)) {
192 TRC0 = getPhysicalRegisterRegClass(MRI, DstReg);
194 TRC0 = MF.getSSARegMap()->getRegClass(DstReg);
196 assert(TRC0 == getPhysicalRegisterRegClass(MRI, SrcReg) &&
197 "Insert superreg and Dst must be of same register class");
199 MRI.copyRegToReg(*mbbi, mi, DstReg, SrcReg, TRC0);
200 MachineBasicBlock::iterator dmi = mi;
201 DOUT << "subreg: " << *(--dmi);
204 if (!revCopyOrder && InsReg != DstSubReg) {
205 // Insert sub-register copy
206 const TargetRegisterClass *TRC1 = 0;
207 if (MRegisterInfo::isPhysicalRegister(InsReg)) {
208 TRC1 = getPhysicalRegisterRegClass(MRI, InsReg);
210 TRC1 = MF.getSSARegMap()->getRegClass(InsReg);
213 MRI.copyRegToReg(*mbbi, mi, DstSubReg, InsReg, TRC1);
214 MachineBasicBlock::iterator dmi = mi;
215 DOUT << "subreg: " << *(--dmi);