1 //===-- LiveVariables.cpp - Live Variable Analysis for Machine Code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveVariable analysis pass. For each machine
11 // instruction in the function, this pass calculates the set of registers that
12 // are immediately dead after the instruction (i.e., the instruction calculates
13 // the value, but it is never used) and the set of registers that are used by
14 // the instruction, but are never used after the instruction (i.e., they are
17 // This class computes live variables using are sparse implementation based on
18 // the machine code SSA form. This class computes live variable information for
19 // each virtual and _register allocatable_ physical register in a function. It
20 // uses the dominance properties of SSA form to efficiently compute live
21 // variables for virtual registers, and assumes that physical registers are only
22 // live within a single basic block (allowing it to do a single local analysis
23 // to resolve physical register lifetimes in each basic block). If a physical
24 // register is not register allocatable, it is not tracked. This is useful for
25 // things like the stack pointer and condition codes.
27 //===----------------------------------------------------------------------===//
29 #include "llvm/CodeGen/LiveVariables.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/Target/MRegisterInfo.h"
33 #include "llvm/Target/TargetInstrInfo.h"
34 #include "llvm/Target/TargetMachine.h"
35 #include "llvm/ADT/DepthFirstIterator.h"
36 #include "llvm/ADT/SmallPtrSet.h"
37 #include "llvm/ADT/STLExtras.h"
38 #include "llvm/Config/alloca.h"
42 char LiveVariables::ID = 0;
43 static RegisterPass<LiveVariables> X("livevars", "Live Variable Analysis");
45 void LiveVariables::VarInfo::dump() const {
46 cerr << " Alive in blocks: ";
47 for (unsigned i = 0, e = AliveBlocks.size(); i != e; ++i)
48 if (AliveBlocks[i]) cerr << i << ", ";
49 cerr << " Used in blocks: ";
50 for (unsigned i = 0, e = UsedBlocks.size(); i != e; ++i)
51 if (UsedBlocks[i]) cerr << i << ", ";
52 cerr << "\n Killed by:";
54 cerr << " No instructions.\n";
56 for (unsigned i = 0, e = Kills.size(); i != e; ++i)
57 cerr << "\n #" << i << ": " << *Kills[i];
62 LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) {
63 assert(MRegisterInfo::isVirtualRegister(RegIdx) &&
64 "getVarInfo: not a virtual register!");
65 RegIdx -= MRegisterInfo::FirstVirtualRegister;
66 if (RegIdx >= VirtRegInfo.size()) {
67 if (RegIdx >= 2*VirtRegInfo.size())
68 VirtRegInfo.resize(RegIdx*2);
70 VirtRegInfo.resize(2*VirtRegInfo.size());
72 VarInfo &VI = VirtRegInfo[RegIdx];
73 VI.AliveBlocks.resize(MF->getNumBlockIDs());
74 VI.UsedBlocks.resize(MF->getNumBlockIDs());
78 bool LiveVariables::KillsRegister(MachineInstr *MI, unsigned Reg) const {
79 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
80 MachineOperand &MO = MI->getOperand(i);
81 if (MO.isRegister() && MO.isKill()) {
82 if ((MO.getReg() == Reg) ||
83 (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
84 MRegisterInfo::isPhysicalRegister(Reg) &&
85 RegInfo->isSubRegister(MO.getReg(), Reg)))
92 bool LiveVariables::RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const {
93 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
94 MachineOperand &MO = MI->getOperand(i);
95 if (MO.isRegister() && MO.isDead()) {
96 if ((MO.getReg() == Reg) ||
97 (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
98 MRegisterInfo::isPhysicalRegister(Reg) &&
99 RegInfo->isSubRegister(MO.getReg(), Reg)))
106 bool LiveVariables::ModifiesRegister(MachineInstr *MI, unsigned Reg) const {
107 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
108 MachineOperand &MO = MI->getOperand(i);
109 if (MO.isRegister() && MO.isDef() && MO.getReg() == Reg)
115 void LiveVariables::MarkVirtRegAliveInBlock(VarInfo& VRInfo,
116 MachineBasicBlock *DefBlock,
117 MachineBasicBlock *MBB,
118 std::vector<MachineBasicBlock*> &WorkList) {
119 unsigned BBNum = MBB->getNumber();
121 // Check to see if this basic block is one of the killing blocks. If so,
123 for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
124 if (VRInfo.Kills[i]->getParent() == MBB) {
125 VRInfo.Kills.erase(VRInfo.Kills.begin()+i); // Erase entry
129 if (MBB == DefBlock) return; // Terminate recursion
131 if (VRInfo.AliveBlocks[BBNum])
132 return; // We already know the block is live
134 // Mark the variable known alive in this bb
135 VRInfo.AliveBlocks[BBNum] = true;
137 for (MachineBasicBlock::const_pred_reverse_iterator PI = MBB->pred_rbegin(),
138 E = MBB->pred_rend(); PI != E; ++PI)
139 WorkList.push_back(*PI);
142 void LiveVariables::MarkVirtRegAliveInBlock(VarInfo& VRInfo,
143 MachineBasicBlock *DefBlock,
144 MachineBasicBlock *MBB) {
145 std::vector<MachineBasicBlock*> WorkList;
146 MarkVirtRegAliveInBlock(VRInfo, DefBlock, MBB, WorkList);
147 while (!WorkList.empty()) {
148 MachineBasicBlock *Pred = WorkList.back();
150 MarkVirtRegAliveInBlock(VRInfo, DefBlock, Pred, WorkList);
155 void LiveVariables::HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB,
157 MachineRegisterInfo& MRI = MBB->getParent()->getRegInfo();
158 assert(MRI.getVRegDef(reg) && "Register use before def!");
160 unsigned BBNum = MBB->getNumber();
162 VarInfo& VRInfo = getVarInfo(reg);
163 VRInfo.UsedBlocks[BBNum] = true;
166 // Check to see if this basic block is already a kill block...
167 if (!VRInfo.Kills.empty() && VRInfo.Kills.back()->getParent() == MBB) {
168 // Yes, this register is killed in this basic block already. Increase the
169 // live range by updating the kill instruction.
170 VRInfo.Kills.back() = MI;
175 for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
176 assert(VRInfo.Kills[i]->getParent() != MBB && "entry should be at end!");
179 assert(MBB != MRI.getVRegDef(reg)->getParent() &&
180 "Should have kill for defblock!");
182 // Add a new kill entry for this basic block.
183 // If this virtual register is already marked as alive in this basic block,
184 // that means it is alive in at least one of the successor block, it's not
186 if (!VRInfo.AliveBlocks[BBNum])
187 VRInfo.Kills.push_back(MI);
189 // Update all dominating blocks to mark them known live.
190 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
191 E = MBB->pred_end(); PI != E; ++PI)
192 MarkVirtRegAliveInBlock(VRInfo, MRI.getVRegDef(reg)->getParent(), *PI);
195 void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) {
196 // Turn previous partial def's into read/mod/write.
197 for (unsigned i = 0, e = PhysRegPartDef[Reg].size(); i != e; ++i) {
198 MachineInstr *Def = PhysRegPartDef[Reg][i];
199 // First one is just a def. This means the use is reading some undef bits.
201 Def->addOperand(MachineOperand::CreateReg(Reg, false/*IsDef*/,
202 true/*IsImp*/,true/*IsKill*/));
203 Def->addOperand(MachineOperand::CreateReg(Reg,true/*IsDef*/,true/*IsImp*/));
205 PhysRegPartDef[Reg].clear();
207 // There was an earlier def of a super-register. Add implicit def to that MI.
210 // Add implicit def to A.
211 if (PhysRegInfo[Reg] && PhysRegInfo[Reg] != PhysRegPartUse[Reg] &&
213 MachineInstr *Def = PhysRegInfo[Reg];
214 if (!Def->findRegisterDefOperand(Reg))
215 Def->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/,
219 // There is a now a proper use, forget about the last partial use.
220 PhysRegPartUse[Reg] = NULL;
221 PhysRegInfo[Reg] = MI;
222 PhysRegUsed[Reg] = true;
224 for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg);
225 unsigned SubReg = *SubRegs; ++SubRegs) {
226 PhysRegInfo[SubReg] = MI;
227 PhysRegUsed[SubReg] = true;
230 for (const unsigned *SuperRegs = RegInfo->getSuperRegisters(Reg);
231 unsigned SuperReg = *SuperRegs; ++SuperRegs) {
232 // Remember the partial use of this superreg if it was previously defined.
233 bool HasPrevDef = PhysRegInfo[SuperReg] != NULL;
235 for (const unsigned *SSRegs = RegInfo->getSuperRegisters(SuperReg);
236 unsigned SSReg = *SSRegs; ++SSRegs) {
237 if (PhysRegInfo[SSReg] != NULL) {
244 PhysRegInfo[SuperReg] = MI;
245 PhysRegPartUse[SuperReg] = MI;
250 bool LiveVariables::HandlePhysRegKill(unsigned Reg, MachineInstr *RefMI,
251 SmallSet<unsigned, 4> &SubKills) {
252 for (const unsigned *SubRegs = RegInfo->getImmediateSubRegisters(Reg);
253 unsigned SubReg = *SubRegs; ++SubRegs) {
254 MachineInstr *LastRef = PhysRegInfo[SubReg];
255 if (LastRef != RefMI ||
256 !HandlePhysRegKill(SubReg, RefMI, SubKills))
257 SubKills.insert(SubReg);
260 if (*RegInfo->getImmediateSubRegisters(Reg) == 0) {
261 // No sub-registers, just check if reg is killed by RefMI.
262 if (PhysRegInfo[Reg] == RefMI)
264 } else if (SubKills.empty())
265 // None of the sub-registers are killed elsewhere...
270 void LiveVariables::addRegisterKills(unsigned Reg, MachineInstr *MI,
271 SmallSet<unsigned, 4> &SubKills) {
272 if (SubKills.count(Reg) == 0)
273 MI->addRegisterKilled(Reg, RegInfo, true);
275 for (const unsigned *SubRegs = RegInfo->getImmediateSubRegisters(Reg);
276 unsigned SubReg = *SubRegs; ++SubRegs)
277 addRegisterKills(SubReg, MI, SubKills);
281 bool LiveVariables::HandlePhysRegKill(unsigned Reg, MachineInstr *RefMI) {
282 SmallSet<unsigned, 4> SubKills;
283 if (HandlePhysRegKill(Reg, RefMI, SubKills)) {
284 RefMI->addRegisterKilled(Reg, RegInfo, true);
287 // Some sub-registers are killed by another MI.
288 for (const unsigned *SubRegs = RegInfo->getImmediateSubRegisters(Reg);
289 unsigned SubReg = *SubRegs; ++SubRegs)
290 addRegisterKills(SubReg, RefMI, SubKills);
295 void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI) {
296 // Does this kill a previous version of this register?
297 if (MachineInstr *LastRef = PhysRegInfo[Reg]) {
298 if (PhysRegUsed[Reg]) {
299 if (!HandlePhysRegKill(Reg, LastRef)) {
300 if (PhysRegPartUse[Reg])
301 PhysRegPartUse[Reg]->addRegisterKilled(Reg, RegInfo, true);
303 } else if (PhysRegPartUse[Reg])
304 // Add implicit use / kill to last partial use.
305 PhysRegPartUse[Reg]->addRegisterKilled(Reg, RegInfo, true);
306 else if (LastRef != MI)
307 // Defined, but not used. However, watch out for cases where a super-reg
308 // is also defined on the same MI.
309 LastRef->addRegisterDead(Reg, RegInfo);
312 for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg);
313 unsigned SubReg = *SubRegs; ++SubRegs) {
314 if (MachineInstr *LastRef = PhysRegInfo[SubReg]) {
315 if (PhysRegUsed[SubReg]) {
316 if (!HandlePhysRegKill(SubReg, LastRef)) {
317 if (PhysRegPartUse[SubReg])
318 PhysRegPartUse[SubReg]->addRegisterKilled(SubReg, RegInfo, true);
320 } else if (PhysRegPartUse[SubReg])
321 // Add implicit use / kill to last use of a sub-register.
322 PhysRegPartUse[SubReg]->addRegisterKilled(SubReg, RegInfo, true);
323 else if (LastRef != MI)
324 // This must be a def of the subreg on the same MI.
325 LastRef->addRegisterDead(SubReg, RegInfo);
330 for (const unsigned *SuperRegs = RegInfo->getSuperRegisters(Reg);
331 unsigned SuperReg = *SuperRegs; ++SuperRegs) {
332 if (PhysRegInfo[SuperReg] && PhysRegInfo[SuperReg] != MI) {
333 // The larger register is previously defined. Now a smaller part is
334 // being re-defined. Treat it as read/mod/write.
336 // AX = EAX<imp-use,kill>, EAX<imp-def>
337 MI->addOperand(MachineOperand::CreateReg(SuperReg, false/*IsDef*/,
338 true/*IsImp*/,true/*IsKill*/));
339 MI->addOperand(MachineOperand::CreateReg(SuperReg, true/*IsDef*/,
341 PhysRegInfo[SuperReg] = MI;
342 PhysRegUsed[SuperReg] = false;
343 PhysRegPartUse[SuperReg] = NULL;
345 // Remember this partial def.
346 PhysRegPartDef[SuperReg].push_back(MI);
350 PhysRegInfo[Reg] = MI;
351 PhysRegUsed[Reg] = false;
352 PhysRegPartDef[Reg].clear();
353 PhysRegPartUse[Reg] = NULL;
354 for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg);
355 unsigned SubReg = *SubRegs; ++SubRegs) {
356 PhysRegInfo[SubReg] = MI;
357 PhysRegUsed[SubReg] = false;
358 PhysRegPartDef[SubReg].clear();
359 PhysRegPartUse[SubReg] = NULL;
364 bool LiveVariables::runOnMachineFunction(MachineFunction &mf) {
366 RegInfo = MF->getTarget().getRegisterInfo();
367 MachineRegisterInfo& MRI = mf.getRegInfo();
368 assert(RegInfo && "Target doesn't have register information?");
370 ReservedRegisters = RegInfo->getReservedRegs(mf);
372 unsigned NumRegs = RegInfo->getNumRegs();
373 PhysRegInfo = new MachineInstr*[NumRegs];
374 PhysRegUsed = new bool[NumRegs];
375 PhysRegPartUse = new MachineInstr*[NumRegs];
376 PhysRegPartDef = new SmallVector<MachineInstr*,4>[NumRegs];
377 PHIVarInfo = new SmallVector<unsigned, 4>[MF->getNumBlockIDs()];
378 std::fill(PhysRegInfo, PhysRegInfo + NumRegs, (MachineInstr*)0);
379 std::fill(PhysRegUsed, PhysRegUsed + NumRegs, false);
380 std::fill(PhysRegPartUse, PhysRegPartUse + NumRegs, (MachineInstr*)0);
382 /// Get some space for a respectable number of registers...
383 VirtRegInfo.resize(64);
387 // Calculate live variable information in depth first order on the CFG of the
388 // function. This guarantees that we will see the definition of a virtual
389 // register before its uses due to dominance properties of SSA (except for PHI
390 // nodes, which are treated as a special case).
392 MachineBasicBlock *Entry = MF->begin();
393 SmallPtrSet<MachineBasicBlock*,16> Visited;
394 for (df_ext_iterator<MachineBasicBlock*, SmallPtrSet<MachineBasicBlock*,16> >
395 DFI = df_ext_begin(Entry, Visited), E = df_ext_end(Entry, Visited);
397 MachineBasicBlock *MBB = *DFI;
399 // Mark live-in registers as live-in.
400 for (MachineBasicBlock::const_livein_iterator II = MBB->livein_begin(),
401 EE = MBB->livein_end(); II != EE; ++II) {
402 assert(MRegisterInfo::isPhysicalRegister(*II) &&
403 "Cannot have a live-in virtual register!");
404 HandlePhysRegDef(*II, 0);
407 // Loop over all of the instructions, processing them.
408 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
410 MachineInstr *MI = I;
412 // Process all of the operands of the instruction...
413 unsigned NumOperandsToProcess = MI->getNumOperands();
415 // Unless it is a PHI node. In this case, ONLY process the DEF, not any
416 // of the uses. They will be handled in other basic blocks.
417 if (MI->getOpcode() == TargetInstrInfo::PHI)
418 NumOperandsToProcess = 1;
420 // Process all uses...
421 for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
422 MachineOperand &MO = MI->getOperand(i);
423 if (MO.isRegister() && MO.isUse() && MO.getReg()) {
424 if (MRegisterInfo::isVirtualRegister(MO.getReg())){
425 HandleVirtRegUse(MO.getReg(), MBB, MI);
426 } else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
427 !ReservedRegisters[MO.getReg()]) {
428 HandlePhysRegUse(MO.getReg(), MI);
433 // Process all defs...
434 for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
435 MachineOperand &MO = MI->getOperand(i);
436 if (MO.isRegister() && MO.isDef() && MO.getReg()) {
437 if (MRegisterInfo::isVirtualRegister(MO.getReg())) {
438 VarInfo &VRInfo = getVarInfo(MO.getReg());
440 VRInfo.Kills.push_back(MI);
441 } else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
442 !ReservedRegisters[MO.getReg()]) {
443 HandlePhysRegDef(MO.getReg(), MI);
449 // Handle any virtual assignments from PHI nodes which might be at the
450 // bottom of this basic block. We check all of our successor blocks to see
451 // if they have PHI nodes, and if so, we simulate an assignment at the end
452 // of the current block.
453 if (!PHIVarInfo[MBB->getNumber()].empty()) {
454 SmallVector<unsigned, 4>& VarInfoVec = PHIVarInfo[MBB->getNumber()];
456 for (SmallVector<unsigned, 4>::iterator I = VarInfoVec.begin(),
457 E = VarInfoVec.end(); I != E; ++I) {
458 // Only mark it alive only in the block we are representing.
459 MarkVirtRegAliveInBlock(getVarInfo(*I), MRI.getVRegDef(*I)->getParent(),
464 // Finally, if the last instruction in the block is a return, make sure to mark
465 // it as using all of the live-out values in the function.
466 if (!MBB->empty() && MBB->back().getDesc().isReturn()) {
467 MachineInstr *Ret = &MBB->back();
468 for (MachineRegisterInfo::liveout_iterator
469 I = MF->getRegInfo().liveout_begin(),
470 E = MF->getRegInfo().liveout_end(); I != E; ++I) {
471 assert(MRegisterInfo::isPhysicalRegister(*I) &&
472 "Cannot have a live-in virtual register!");
473 HandlePhysRegUse(*I, Ret);
474 // Add live-out registers as implicit uses.
475 if (Ret->findRegisterUseOperandIdx(*I) == -1)
476 Ret->addOperand(MachineOperand::CreateReg(*I, false, true));
480 // Loop over PhysRegInfo, killing any registers that are available at the
481 // end of the basic block. This also resets the PhysRegInfo map.
482 for (unsigned i = 0; i != NumRegs; ++i)
484 HandlePhysRegDef(i, 0);
486 // Clear some states between BB's. These are purely local information.
487 for (unsigned i = 0; i != NumRegs; ++i)
488 PhysRegPartDef[i].clear();
489 std::fill(PhysRegInfo, PhysRegInfo + NumRegs, (MachineInstr*)0);
490 std::fill(PhysRegUsed, PhysRegUsed + NumRegs, false);
491 std::fill(PhysRegPartUse, PhysRegPartUse + NumRegs, (MachineInstr*)0);
494 // Convert and transfer the dead / killed information we have gathered into
495 // VirtRegInfo onto MI's.
497 for (unsigned i = 0, e1 = VirtRegInfo.size(); i != e1; ++i)
498 for (unsigned j = 0, e2 = VirtRegInfo[i].Kills.size(); j != e2; ++j) {
499 if (VirtRegInfo[i].Kills[j] == MRI.getVRegDef(i +
500 MRegisterInfo::FirstVirtualRegister))
501 VirtRegInfo[i].Kills[j]->addRegisterDead(i +
502 MRegisterInfo::FirstVirtualRegister,
505 VirtRegInfo[i].Kills[j]->addRegisterKilled(i +
506 MRegisterInfo::FirstVirtualRegister,
510 // Check to make sure there are no unreachable blocks in the MC CFG for the
511 // function. If so, it is due to a bug in the instruction selector or some
512 // other part of the code generator if this happens.
514 for(MachineFunction::iterator i = MF->begin(), e = MF->end(); i != e; ++i)
515 assert(Visited.count(&*i) != 0 && "unreachable basic block found");
518 delete[] PhysRegInfo;
519 delete[] PhysRegUsed;
520 delete[] PhysRegPartUse;
521 delete[] PhysRegPartDef;
527 /// instructionChanged - When the address of an instruction changes, this
528 /// method should be called so that live variables can update its internal
529 /// data structures. This removes the records for OldMI, transfering them to
530 /// the records for NewMI.
531 void LiveVariables::instructionChanged(MachineInstr *OldMI,
532 MachineInstr *NewMI) {
533 // If the instruction defines any virtual registers, update the VarInfo,
534 // kill and dead information for the instruction.
535 for (unsigned i = 0, e = OldMI->getNumOperands(); i != e; ++i) {
536 MachineOperand &MO = OldMI->getOperand(i);
537 if (MO.isRegister() && MO.getReg() &&
538 MRegisterInfo::isVirtualRegister(MO.getReg())) {
539 unsigned Reg = MO.getReg();
540 VarInfo &VI = getVarInfo(Reg);
544 addVirtualRegisterDead(Reg, NewMI);
549 addVirtualRegisterKilled(Reg, NewMI);
551 // If this is a kill of the value, update the VI kills list.
552 if (VI.removeKill(OldMI))
553 VI.Kills.push_back(NewMI); // Yes, there was a kill of it
558 /// removeVirtualRegistersKilled - Remove all killed info for the specified
560 void LiveVariables::removeVirtualRegistersKilled(MachineInstr *MI) {
561 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
562 MachineOperand &MO = MI->getOperand(i);
563 if (MO.isRegister() && MO.isKill()) {
565 unsigned Reg = MO.getReg();
566 if (MRegisterInfo::isVirtualRegister(Reg)) {
567 bool removed = getVarInfo(Reg).removeKill(MI);
568 assert(removed && "kill not in register's VarInfo?");
574 /// removeVirtualRegistersDead - Remove all of the dead registers for the
575 /// specified instruction from the live variable information.
576 void LiveVariables::removeVirtualRegistersDead(MachineInstr *MI) {
577 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
578 MachineOperand &MO = MI->getOperand(i);
579 if (MO.isRegister() && MO.isDead()) {
581 unsigned Reg = MO.getReg();
582 if (MRegisterInfo::isVirtualRegister(Reg)) {
583 bool removed = getVarInfo(Reg).removeKill(MI);
584 assert(removed && "kill not in register's VarInfo?");
590 /// analyzePHINodes - Gather information about the PHI nodes in here. In
591 /// particular, we want to map the variable information of a virtual
592 /// register which is used in a PHI node. We map that to the BB the vreg is
595 void LiveVariables::analyzePHINodes(const MachineFunction& Fn) {
596 for (MachineFunction::const_iterator I = Fn.begin(), E = Fn.end();
598 for (MachineBasicBlock::const_iterator BBI = I->begin(), BBE = I->end();
599 BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI)
600 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
601 PHIVarInfo[BBI->getOperand(i + 1).getMBB()->getNumber()].
602 push_back(BBI->getOperand(i).getReg());