1 //===-- LiveVariables.cpp - Live Variable Analysis for Machine Code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveVariable analysis pass. For each machine
11 // instruction in the function, this pass calculates the set of registers that
12 // are immediately dead after the instruction (i.e., the instruction calculates
13 // the value, but it is never used) and the set of registers that are used by
14 // the instruction, but are never used after the instruction (i.e., they are
17 // This class computes live variables using are sparse implementation based on
18 // the machine code SSA form. This class computes live variable information for
19 // each virtual and _register allocatable_ physical register in a function. It
20 // uses the dominance properties of SSA form to efficiently compute live
21 // variables for virtual registers, and assumes that physical registers are only
22 // live within a single basic block (allowing it to do a single local analysis
23 // to resolve physical register lifetimes in each basic block). If a physical
24 // register is not register allocatable, it is not tracked. This is useful for
25 // things like the stack pointer and condition codes.
27 //===----------------------------------------------------------------------===//
29 #include "llvm/CodeGen/LiveVariables.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/Passes.h"
33 #include "llvm/Target/TargetRegisterInfo.h"
34 #include "llvm/Target/TargetInstrInfo.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/ADT/DepthFirstIterator.h"
37 #include "llvm/ADT/SmallPtrSet.h"
38 #include "llvm/ADT/SmallSet.h"
39 #include "llvm/ADT/STLExtras.h"
43 char LiveVariables::ID = 0;
44 static RegisterPass<LiveVariables> X("livevars", "Live Variable Analysis");
47 void LiveVariables::getAnalysisUsage(AnalysisUsage &AU) const {
48 AU.addRequiredID(UnreachableMachineBlockElimID);
50 MachineFunctionPass::getAnalysisUsage(AU);
54 LiveVariables::VarInfo::findKill(const MachineBasicBlock *MBB) const {
55 for (unsigned i = 0, e = Kills.size(); i != e; ++i)
56 if (Kills[i]->getParent() == MBB)
61 void LiveVariables::VarInfo::dump() const {
62 errs() << " Alive in blocks: ";
63 for (SparseBitVector<>::iterator I = AliveBlocks.begin(),
64 E = AliveBlocks.end(); I != E; ++I)
66 errs() << "\n Killed by:";
68 errs() << " No instructions.\n";
70 for (unsigned i = 0, e = Kills.size(); i != e; ++i)
71 errs() << "\n #" << i << ": " << *Kills[i];
76 /// getVarInfo - Get (possibly creating) a VarInfo object for the given vreg.
77 LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) {
78 assert(TargetRegisterInfo::isVirtualRegister(RegIdx) &&
79 "getVarInfo: not a virtual register!");
80 RegIdx -= TargetRegisterInfo::FirstVirtualRegister;
81 if (RegIdx >= VirtRegInfo.size()) {
82 if (RegIdx >= 2*VirtRegInfo.size())
83 VirtRegInfo.resize(RegIdx*2);
85 VirtRegInfo.resize(2*VirtRegInfo.size());
87 return VirtRegInfo[RegIdx];
90 void LiveVariables::MarkVirtRegAliveInBlock(VarInfo& VRInfo,
91 MachineBasicBlock *DefBlock,
92 MachineBasicBlock *MBB,
93 std::vector<MachineBasicBlock*> &WorkList) {
94 unsigned BBNum = MBB->getNumber();
96 // Check to see if this basic block is one of the killing blocks. If so,
98 for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
99 if (VRInfo.Kills[i]->getParent() == MBB) {
100 VRInfo.Kills.erase(VRInfo.Kills.begin()+i); // Erase entry
104 if (MBB == DefBlock) return; // Terminate recursion
106 if (VRInfo.AliveBlocks.test(BBNum))
107 return; // We already know the block is live
109 // Mark the variable known alive in this bb
110 VRInfo.AliveBlocks.set(BBNum);
112 for (MachineBasicBlock::const_pred_reverse_iterator PI = MBB->pred_rbegin(),
113 E = MBB->pred_rend(); PI != E; ++PI)
114 WorkList.push_back(*PI);
117 void LiveVariables::MarkVirtRegAliveInBlock(VarInfo &VRInfo,
118 MachineBasicBlock *DefBlock,
119 MachineBasicBlock *MBB) {
120 std::vector<MachineBasicBlock*> WorkList;
121 MarkVirtRegAliveInBlock(VRInfo, DefBlock, MBB, WorkList);
123 while (!WorkList.empty()) {
124 MachineBasicBlock *Pred = WorkList.back();
126 MarkVirtRegAliveInBlock(VRInfo, DefBlock, Pred, WorkList);
130 void LiveVariables::HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB,
132 assert(MRI->getVRegDef(reg) && "Register use before def!");
134 unsigned BBNum = MBB->getNumber();
136 VarInfo& VRInfo = getVarInfo(reg);
139 // Check to see if this basic block is already a kill block.
140 if (!VRInfo.Kills.empty() && VRInfo.Kills.back()->getParent() == MBB) {
141 // Yes, this register is killed in this basic block already. Increase the
142 // live range by updating the kill instruction.
143 VRInfo.Kills.back() = MI;
148 for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
149 assert(VRInfo.Kills[i]->getParent() != MBB && "entry should be at end!");
152 // This situation can occur:
157 // | t2 = phi ... t1 ...
161 // | ... = ... t1 ...
165 // where there is a use in a PHI node that's a predecessor to the defining
166 // block. We don't want to mark all predecessors as having the value "alive"
168 if (MBB == MRI->getVRegDef(reg)->getParent()) return;
170 // Add a new kill entry for this basic block. If this virtual register is
171 // already marked as alive in this basic block, that means it is alive in at
172 // least one of the successor blocks, it's not a kill.
173 if (!VRInfo.AliveBlocks.test(BBNum))
174 VRInfo.Kills.push_back(MI);
176 // Update all dominating blocks to mark them as "known live".
177 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
178 E = MBB->pred_end(); PI != E; ++PI)
179 MarkVirtRegAliveInBlock(VRInfo, MRI->getVRegDef(reg)->getParent(), *PI);
182 void LiveVariables::HandleVirtRegDef(unsigned Reg, MachineInstr *MI) {
183 VarInfo &VRInfo = getVarInfo(Reg);
185 if (VRInfo.AliveBlocks.empty())
186 // If vr is not alive in any block, then defaults to dead.
187 VRInfo.Kills.push_back(MI);
190 /// FindLastPartialDef - Return the last partial def of the specified register.
191 /// Also returns the sub-registers that're defined by the instruction.
192 MachineInstr *LiveVariables::FindLastPartialDef(unsigned Reg,
193 SmallSet<unsigned,4> &PartDefRegs) {
194 unsigned LastDefReg = 0;
195 unsigned LastDefDist = 0;
196 MachineInstr *LastDef = NULL;
197 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
198 unsigned SubReg = *SubRegs; ++SubRegs) {
199 MachineInstr *Def = PhysRegDef[SubReg];
202 unsigned Dist = DistanceMap[Def];
203 if (Dist > LastDefDist) {
213 PartDefRegs.insert(LastDefReg);
214 for (unsigned i = 0, e = LastDef->getNumOperands(); i != e; ++i) {
215 MachineOperand &MO = LastDef->getOperand(i);
216 if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
218 unsigned DefReg = MO.getReg();
219 if (TRI->isSubRegister(Reg, DefReg)) {
220 PartDefRegs.insert(DefReg);
221 for (const unsigned *SubRegs = TRI->getSubRegisters(DefReg);
222 unsigned SubReg = *SubRegs; ++SubRegs)
223 PartDefRegs.insert(SubReg);
229 /// HandlePhysRegUse - Turn previous partial def's into read/mod/writes. Add
230 /// implicit defs to a machine instruction if there was an earlier def of its
232 void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) {
233 MachineInstr *LastDef = PhysRegDef[Reg];
234 // If there was a previous use or a "full" def all is well.
235 if (!LastDef && !PhysRegUse[Reg]) {
236 // Otherwise, the last sub-register def implicitly defines this register.
239 // AL = ... <imp-def EAX>, <imp-kill AH>
243 // All of the sub-registers must have been defined before the use of Reg!
244 SmallSet<unsigned, 4> PartDefRegs;
245 MachineInstr *LastPartialDef = FindLastPartialDef(Reg, PartDefRegs);
246 // If LastPartialDef is NULL, it must be using a livein register.
247 if (LastPartialDef) {
248 LastPartialDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/,
250 PhysRegDef[Reg] = LastPartialDef;
251 SmallSet<unsigned, 8> Processed;
252 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
253 unsigned SubReg = *SubRegs; ++SubRegs) {
254 if (Processed.count(SubReg))
256 if (PartDefRegs.count(SubReg))
258 // This part of Reg was defined before the last partial def. It's killed
260 LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg,
263 PhysRegDef[SubReg] = LastPartialDef;
264 for (const unsigned *SS = TRI->getSubRegisters(SubReg); *SS; ++SS)
265 Processed.insert(*SS);
269 else if (LastDef && !PhysRegUse[Reg] &&
270 !LastDef->findRegisterDefOperand(Reg))
271 // Last def defines the super register, add an implicit def of reg.
272 LastDef->addOperand(MachineOperand::CreateReg(Reg,
273 true/*IsDef*/, true/*IsImp*/));
275 // Remember this use.
276 PhysRegUse[Reg] = MI;
277 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
278 unsigned SubReg = *SubRegs; ++SubRegs)
279 PhysRegUse[SubReg] = MI;
282 bool LiveVariables::HandlePhysRegKill(unsigned Reg, MachineInstr *MI) {
283 MachineInstr *LastDef = PhysRegDef[Reg];
284 MachineInstr *LastUse = PhysRegUse[Reg];
285 if (!LastDef && !LastUse)
288 MachineInstr *LastRefOrPartRef = LastUse ? LastUse : LastDef;
289 unsigned LastRefOrPartRefDist = DistanceMap[LastRefOrPartRef];
290 // The whole register is used.
295 // = AL, AX<imp-use, kill>
298 // Or whole register is defined, but not used at all.
303 // Or whole register is defined, but only partly used.
304 // AX<dead> = AL<imp-def>
307 MachineInstr *LastPartDef = 0;
308 unsigned LastPartDefDist = 0;
309 SmallSet<unsigned, 8> PartUses;
310 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
311 unsigned SubReg = *SubRegs; ++SubRegs) {
312 MachineInstr *Def = PhysRegDef[SubReg];
313 if (Def && Def != LastDef) {
314 // There was a def of this sub-register in between. This is a partial
315 // def, keep track of the last one.
316 unsigned Dist = DistanceMap[Def];
317 if (Dist > LastPartDefDist) {
318 LastPartDefDist = Dist;
323 if (MachineInstr *Use = PhysRegUse[SubReg]) {
324 PartUses.insert(SubReg);
325 for (const unsigned *SS = TRI->getSubRegisters(SubReg); *SS; ++SS)
326 PartUses.insert(*SS);
327 unsigned Dist = DistanceMap[Use];
328 if (Dist > LastRefOrPartRefDist) {
329 LastRefOrPartRefDist = Dist;
330 LastRefOrPartRef = Use;
335 if (LastRefOrPartRef == PhysRegDef[Reg] && LastRefOrPartRef != MI) {
337 // The last partial def kills the register.
338 LastPartDef->addOperand(MachineOperand::CreateReg(Reg, false/*IsDef*/,
339 true/*IsImp*/, true/*IsKill*/));
342 LastRefOrPartRef->findRegisterDefOperand(Reg, false, TRI);
343 bool NeedEC = MO->isEarlyClobber() && MO->getReg() != Reg;
344 // If the last reference is the last def, then it's not used at all.
345 // That is, unless we are currently processing the last reference itself.
346 LastRefOrPartRef->addRegisterDead(Reg, TRI, true);
348 // If we are adding a subreg def and the superreg def is marked early
349 // clobber, add an early clobber marker to the subreg def.
350 MO = LastRefOrPartRef->findRegisterDefOperand(Reg);
352 MO->setIsEarlyClobber();
355 } else if (!PhysRegUse[Reg]) {
356 // Partial uses. Mark register def dead and add implicit def of
357 // sub-registers which are used.
358 // EAX<dead> = op AL<imp-def>
359 // That is, EAX def is dead but AL def extends pass it.
360 PhysRegDef[Reg]->addRegisterDead(Reg, TRI, true);
361 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
362 unsigned SubReg = *SubRegs; ++SubRegs) {
363 if (!PartUses.count(SubReg))
366 if (PhysRegDef[Reg] == PhysRegDef[SubReg]) {
367 MachineOperand *MO = PhysRegDef[Reg]->findRegisterDefOperand(SubReg);
370 assert(!MO->isDead());
374 PhysRegDef[Reg]->addOperand(MachineOperand::CreateReg(SubReg,
375 true/*IsDef*/, true/*IsImp*/));
376 LastRefOrPartRef->addRegisterKilled(SubReg, TRI, true);
377 for (const unsigned *SS = TRI->getSubRegisters(SubReg); *SS; ++SS)
381 LastRefOrPartRef->addRegisterKilled(Reg, TRI, true);
385 void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI,
386 SmallVector<unsigned, 4> &Defs) {
387 // What parts of the register are previously defined?
388 SmallSet<unsigned, 32> Live;
389 if (PhysRegDef[Reg] || PhysRegUse[Reg]) {
391 for (const unsigned *SS = TRI->getSubRegisters(Reg); *SS; ++SS)
394 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
395 unsigned SubReg = *SubRegs; ++SubRegs) {
396 // If a register isn't itself defined, but all parts that make up of it
397 // are defined, then consider it also defined.
402 if (Live.count(SubReg))
404 if (PhysRegDef[SubReg] || PhysRegUse[SubReg]) {
406 for (const unsigned *SS = TRI->getSubRegisters(SubReg); *SS; ++SS)
412 // Start from the largest piece, find the last time any part of the register
414 HandlePhysRegKill(Reg, MI);
415 // Only some of the sub-registers are used.
416 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
417 unsigned SubReg = *SubRegs; ++SubRegs) {
418 if (!Live.count(SubReg))
419 // Skip if this sub-register isn't defined.
421 HandlePhysRegKill(SubReg, MI);
425 Defs.push_back(Reg); // Remember this def.
428 void LiveVariables::UpdatePhysRegDefs(MachineInstr *MI,
429 SmallVector<unsigned, 4> &Defs) {
430 while (!Defs.empty()) {
431 unsigned Reg = Defs.back();
433 PhysRegDef[Reg] = MI;
434 PhysRegUse[Reg] = NULL;
435 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
436 unsigned SubReg = *SubRegs; ++SubRegs) {
437 PhysRegDef[SubReg] = MI;
438 PhysRegUse[SubReg] = NULL;
445 const TargetRegisterInfo *TRI;
447 RegSorter(const TargetRegisterInfo *tri) : TRI(tri) { }
448 bool operator()(unsigned A, unsigned B) {
449 if (TRI->isSubRegister(A, B))
451 else if (TRI->isSubRegister(B, A))
458 bool LiveVariables::runOnMachineFunction(MachineFunction &mf) {
460 MRI = &mf.getRegInfo();
461 TRI = MF->getTarget().getRegisterInfo();
463 ReservedRegisters = TRI->getReservedRegs(mf);
465 unsigned NumRegs = TRI->getNumRegs();
466 PhysRegDef = new MachineInstr*[NumRegs];
467 PhysRegUse = new MachineInstr*[NumRegs];
468 PHIVarInfo = new SmallVector<unsigned, 4>[MF->getNumBlockIDs()];
469 std::fill(PhysRegDef, PhysRegDef + NumRegs, (MachineInstr*)0);
470 std::fill(PhysRegUse, PhysRegUse + NumRegs, (MachineInstr*)0);
472 /// Get some space for a respectable number of registers.
473 VirtRegInfo.resize(64);
477 // Calculate live variable information in depth first order on the CFG of the
478 // function. This guarantees that we will see the definition of a virtual
479 // register before its uses due to dominance properties of SSA (except for PHI
480 // nodes, which are treated as a special case).
481 MachineBasicBlock *Entry = MF->begin();
482 SmallPtrSet<MachineBasicBlock*,16> Visited;
484 for (df_ext_iterator<MachineBasicBlock*, SmallPtrSet<MachineBasicBlock*,16> >
485 DFI = df_ext_begin(Entry, Visited), E = df_ext_end(Entry, Visited);
487 MachineBasicBlock *MBB = *DFI;
489 // Mark live-in registers as live-in.
490 SmallVector<unsigned, 4> Defs;
491 for (MachineBasicBlock::const_livein_iterator II = MBB->livein_begin(),
492 EE = MBB->livein_end(); II != EE; ++II) {
493 assert(TargetRegisterInfo::isPhysicalRegister(*II) &&
494 "Cannot have a live-in virtual register!");
495 HandlePhysRegDef(*II, 0, Defs);
498 // Loop over all of the instructions, processing them.
501 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
503 MachineInstr *MI = I;
504 DistanceMap.insert(std::make_pair(MI, Dist++));
506 // Process all of the operands of the instruction...
507 unsigned NumOperandsToProcess = MI->getNumOperands();
509 // Unless it is a PHI node. In this case, ONLY process the DEF, not any
510 // of the uses. They will be handled in other basic blocks.
511 if (MI->getOpcode() == TargetInstrInfo::PHI)
512 NumOperandsToProcess = 1;
514 SmallVector<unsigned, 4> UseRegs;
515 SmallVector<unsigned, 4> DefRegs;
516 for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
517 const MachineOperand &MO = MI->getOperand(i);
518 if (!MO.isReg() || MO.getReg() == 0)
520 unsigned MOReg = MO.getReg();
522 UseRegs.push_back(MOReg);
524 DefRegs.push_back(MOReg);
528 for (unsigned i = 0, e = UseRegs.size(); i != e; ++i) {
529 unsigned MOReg = UseRegs[i];
530 if (TargetRegisterInfo::isVirtualRegister(MOReg))
531 HandleVirtRegUse(MOReg, MBB, MI);
532 else if (!ReservedRegisters[MOReg])
533 HandlePhysRegUse(MOReg, MI);
537 for (unsigned i = 0, e = DefRegs.size(); i != e; ++i) {
538 unsigned MOReg = DefRegs[i];
539 if (TargetRegisterInfo::isVirtualRegister(MOReg))
540 HandleVirtRegDef(MOReg, MI);
541 else if (!ReservedRegisters[MOReg])
542 HandlePhysRegDef(MOReg, MI, Defs);
544 UpdatePhysRegDefs(MI, Defs);
547 // Handle any virtual assignments from PHI nodes which might be at the
548 // bottom of this basic block. We check all of our successor blocks to see
549 // if they have PHI nodes, and if so, we simulate an assignment at the end
550 // of the current block.
551 if (!PHIVarInfo[MBB->getNumber()].empty()) {
552 SmallVector<unsigned, 4>& VarInfoVec = PHIVarInfo[MBB->getNumber()];
554 for (SmallVector<unsigned, 4>::iterator I = VarInfoVec.begin(),
555 E = VarInfoVec.end(); I != E; ++I)
556 // Mark it alive only in the block we are representing.
557 MarkVirtRegAliveInBlock(getVarInfo(*I),MRI->getVRegDef(*I)->getParent(),
561 // Finally, if the last instruction in the block is a return, make sure to
562 // mark it as using all of the live-out values in the function.
563 if (!MBB->empty() && MBB->back().getDesc().isReturn()) {
564 MachineInstr *Ret = &MBB->back();
566 for (MachineRegisterInfo::liveout_iterator
567 I = MF->getRegInfo().liveout_begin(),
568 E = MF->getRegInfo().liveout_end(); I != E; ++I) {
569 assert(TargetRegisterInfo::isPhysicalRegister(*I) &&
570 "Cannot have a live-out virtual register!");
571 HandlePhysRegUse(*I, Ret);
573 // Add live-out registers as implicit uses.
574 if (!Ret->readsRegister(*I))
575 Ret->addOperand(MachineOperand::CreateReg(*I, false, true));
579 // Loop over PhysRegDef / PhysRegUse, killing any registers that are
580 // available at the end of the basic block.
581 for (unsigned i = 0; i != NumRegs; ++i)
582 if (PhysRegDef[i] || PhysRegUse[i])
583 HandlePhysRegDef(i, 0, Defs);
585 std::fill(PhysRegDef, PhysRegDef + NumRegs, (MachineInstr*)0);
586 std::fill(PhysRegUse, PhysRegUse + NumRegs, (MachineInstr*)0);
589 // Convert and transfer the dead / killed information we have gathered into
590 // VirtRegInfo onto MI's.
591 for (unsigned i = 0, e1 = VirtRegInfo.size(); i != e1; ++i)
592 for (unsigned j = 0, e2 = VirtRegInfo[i].Kills.size(); j != e2; ++j)
593 if (VirtRegInfo[i].Kills[j] ==
594 MRI->getVRegDef(i + TargetRegisterInfo::FirstVirtualRegister))
596 .Kills[j]->addRegisterDead(i +
597 TargetRegisterInfo::FirstVirtualRegister,
601 .Kills[j]->addRegisterKilled(i +
602 TargetRegisterInfo::FirstVirtualRegister,
605 // Check to make sure there are no unreachable blocks in the MC CFG for the
606 // function. If so, it is due to a bug in the instruction selector or some
607 // other part of the code generator if this happens.
609 for(MachineFunction::iterator i = MF->begin(), e = MF->end(); i != e; ++i)
610 assert(Visited.count(&*i) != 0 && "unreachable basic block found");
620 /// replaceKillInstruction - Update register kill info by replacing a kill
621 /// instruction with a new one.
622 void LiveVariables::replaceKillInstruction(unsigned Reg, MachineInstr *OldMI,
623 MachineInstr *NewMI) {
624 VarInfo &VI = getVarInfo(Reg);
625 std::replace(VI.Kills.begin(), VI.Kills.end(), OldMI, NewMI);
628 /// removeVirtualRegistersKilled - Remove all killed info for the specified
630 void LiveVariables::removeVirtualRegistersKilled(MachineInstr *MI) {
631 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
632 MachineOperand &MO = MI->getOperand(i);
633 if (MO.isReg() && MO.isKill()) {
635 unsigned Reg = MO.getReg();
636 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
637 bool removed = getVarInfo(Reg).removeKill(MI);
638 assert(removed && "kill not in register's VarInfo?");
645 /// analyzePHINodes - Gather information about the PHI nodes in here. In
646 /// particular, we want to map the variable information of a virtual register
647 /// which is used in a PHI node. We map that to the BB the vreg is coming from.
649 void LiveVariables::analyzePHINodes(const MachineFunction& Fn) {
650 for (MachineFunction::const_iterator I = Fn.begin(), E = Fn.end();
652 for (MachineBasicBlock::const_iterator BBI = I->begin(), BBE = I->end();
653 BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI)
654 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
655 PHIVarInfo[BBI->getOperand(i + 1).getMBB()->getNumber()]
656 .push_back(BBI->getOperand(i).getReg());
659 /// addNewBlock - Add a new basic block BB as an empty succcessor to DomBB. All
660 /// variables that are live out of DomBB will be marked as passing live through
662 void LiveVariables::addNewBlock(MachineBasicBlock *BB,
663 MachineBasicBlock *DomBB) {
664 const unsigned NumNew = BB->getNumber();
665 const unsigned NumDom = DomBB->getNumber();
667 // Update info for all live variables
668 for (unsigned Reg = TargetRegisterInfo::FirstVirtualRegister,
669 E = MRI->getLastVirtReg()+1; Reg != E; ++Reg) {
670 VarInfo &VI = getVarInfo(Reg);
672 // Anything live through DomBB is also live through BB.
673 if (VI.AliveBlocks.test(NumDom)) {
674 VI.AliveBlocks.set(NumNew);
678 // Variables not defined in DomBB cannot be live out.
679 const MachineInstr *Def = MRI->getVRegDef(Reg);
680 if (!Def || Def->getParent() != DomBB)
684 if (VI.findKill(DomBB))
687 // This register is defined in DomBB and live out
688 VI.AliveBlocks.set(NumNew);