1 //===-- LiveVariables.cpp - Live Variable Analysis for Machine Code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveVariable analysis pass. For each machine
11 // instruction in the function, this pass calculates the set of registers that
12 // are immediately dead after the instruction (i.e., the instruction calculates
13 // the value, but it is never used) and the set of registers that are used by
14 // the instruction, but are never used after the instruction (i.e., they are
17 // This class computes live variables using are sparse implementation based on
18 // the machine code SSA form. This class computes live variable information for
19 // each virtual and _register allocatable_ physical register in a function. It
20 // uses the dominance properties of SSA form to efficiently compute live
21 // variables for virtual registers, and assumes that physical registers are only
22 // live within a single basic block (allowing it to do a single local analysis
23 // to resolve physical register lifetimes in each basic block). If a physical
24 // register is not register allocatable, it is not tracked. This is useful for
25 // things like the stack pointer and condition codes.
27 //===----------------------------------------------------------------------===//
29 #include "llvm/CodeGen/LiveVariables.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/Target/MRegisterInfo.h"
32 #include "llvm/Target/TargetInstrInfo.h"
33 #include "llvm/Target/TargetMachine.h"
34 #include "llvm/ADT/DepthFirstIterator.h"
35 #include "llvm/ADT/SmallPtrSet.h"
36 #include "llvm/ADT/STLExtras.h"
37 #include "llvm/Config/alloca.h"
41 char LiveVariables::ID = 0;
42 static RegisterPass<LiveVariables> X("livevars", "Live Variable Analysis");
44 void LiveVariables::VarInfo::dump() const {
45 cerr << "Register Defined by: ";
50 cerr << " Alive in blocks: ";
51 for (unsigned i = 0, e = AliveBlocks.size(); i != e; ++i)
52 if (AliveBlocks[i]) cerr << i << ", ";
53 cerr << "\n Killed by:";
55 cerr << " No instructions.\n";
57 for (unsigned i = 0, e = Kills.size(); i != e; ++i)
58 cerr << "\n #" << i << ": " << *Kills[i];
63 LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) {
64 assert(MRegisterInfo::isVirtualRegister(RegIdx) &&
65 "getVarInfo: not a virtual register!");
66 RegIdx -= MRegisterInfo::FirstVirtualRegister;
67 if (RegIdx >= VirtRegInfo.size()) {
68 if (RegIdx >= 2*VirtRegInfo.size())
69 VirtRegInfo.resize(RegIdx*2);
71 VirtRegInfo.resize(2*VirtRegInfo.size());
73 VarInfo &VI = VirtRegInfo[RegIdx];
74 VI.AliveBlocks.resize(MF->getNumBlockIDs());
78 bool LiveVariables::KillsRegister(MachineInstr *MI, unsigned Reg) const {
79 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
80 MachineOperand &MO = MI->getOperand(i);
81 if (MO.isReg() && MO.isKill()) {
82 if ((MO.getReg() == Reg) ||
83 (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
84 MRegisterInfo::isPhysicalRegister(Reg) &&
85 RegInfo->isSubRegister(MO.getReg(), Reg)))
92 bool LiveVariables::RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const {
93 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
94 MachineOperand &MO = MI->getOperand(i);
95 if (MO.isReg() && MO.isDead()) {
96 if ((MO.getReg() == Reg) ||
97 (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
98 MRegisterInfo::isPhysicalRegister(Reg) &&
99 RegInfo->isSubRegister(MO.getReg(), Reg)))
106 bool LiveVariables::ModifiesRegister(MachineInstr *MI, unsigned Reg) const {
107 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
108 MachineOperand &MO = MI->getOperand(i);
109 if (MO.isReg() && MO.isDef() && MO.getReg() == Reg)
115 void LiveVariables::MarkVirtRegAliveInBlock(VarInfo &VRInfo,
116 MachineBasicBlock *MBB,
117 std::vector<MachineBasicBlock*> &WorkList) {
118 unsigned BBNum = MBB->getNumber();
120 // Check to see if this basic block is one of the killing blocks. If so,
122 for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
123 if (VRInfo.Kills[i]->getParent() == MBB) {
124 VRInfo.Kills.erase(VRInfo.Kills.begin()+i); // Erase entry
128 if (MBB == VRInfo.DefInst->getParent()) return; // Terminate recursion
130 if (VRInfo.AliveBlocks[BBNum])
131 return; // We already know the block is live
133 // Mark the variable known alive in this bb
134 VRInfo.AliveBlocks[BBNum] = true;
136 for (MachineBasicBlock::const_pred_reverse_iterator PI = MBB->pred_rbegin(),
137 E = MBB->pred_rend(); PI != E; ++PI)
138 WorkList.push_back(*PI);
141 void LiveVariables::MarkVirtRegAliveInBlock(VarInfo &VRInfo,
142 MachineBasicBlock *MBB) {
143 std::vector<MachineBasicBlock*> WorkList;
144 MarkVirtRegAliveInBlock(VRInfo, MBB, WorkList);
145 while (!WorkList.empty()) {
146 MachineBasicBlock *Pred = WorkList.back();
148 MarkVirtRegAliveInBlock(VRInfo, Pred, WorkList);
153 void LiveVariables::HandleVirtRegUse(VarInfo &VRInfo, MachineBasicBlock *MBB,
155 assert(VRInfo.DefInst && "Register use before def!");
159 // Check to see if this basic block is already a kill block...
160 if (!VRInfo.Kills.empty() && VRInfo.Kills.back()->getParent() == MBB) {
161 // Yes, this register is killed in this basic block already. Increase the
162 // live range by updating the kill instruction.
163 VRInfo.Kills.back() = MI;
168 for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
169 assert(VRInfo.Kills[i]->getParent() != MBB && "entry should be at end!");
172 assert(MBB != VRInfo.DefInst->getParent() &&
173 "Should have kill for defblock!");
175 // Add a new kill entry for this basic block.
176 // If this virtual register is already marked as alive in this basic block,
177 // that means it is alive in at least one of the successor block, it's not
179 if (!VRInfo.AliveBlocks[MBB->getNumber()])
180 VRInfo.Kills.push_back(MI);
182 // Update all dominating blocks to mark them known live.
183 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
184 E = MBB->pred_end(); PI != E; ++PI)
185 MarkVirtRegAliveInBlock(VRInfo, *PI);
188 bool LiveVariables::addRegisterKilled(unsigned IncomingReg, MachineInstr *MI,
189 bool AddIfNotFound) {
191 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
192 MachineOperand &MO = MI->getOperand(i);
193 if (MO.isReg() && MO.isUse()) {
194 unsigned Reg = MO.getReg();
197 if (Reg == IncomingReg) {
201 } else if (MRegisterInfo::isPhysicalRegister(Reg) &&
202 MRegisterInfo::isPhysicalRegister(IncomingReg) &&
203 RegInfo->isSuperRegister(IncomingReg, Reg) &&
205 // A super-register kill already exists.
210 // If not found, this means an alias of one of the operand is killed. Add a
211 // new implicit operand if required.
212 if (!Found && AddIfNotFound) {
213 MI->addRegOperand(IncomingReg, false/*IsDef*/,true/*IsImp*/,true/*IsKill*/);
219 bool LiveVariables::addRegisterDead(unsigned IncomingReg, MachineInstr *MI,
220 bool AddIfNotFound) {
222 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
223 MachineOperand &MO = MI->getOperand(i);
224 if (MO.isReg() && MO.isDef()) {
225 unsigned Reg = MO.getReg();
228 if (Reg == IncomingReg) {
232 } else if (MRegisterInfo::isPhysicalRegister(Reg) &&
233 MRegisterInfo::isPhysicalRegister(IncomingReg) &&
234 RegInfo->isSuperRegister(IncomingReg, Reg) &&
236 // There exists a super-register that's marked dead.
241 // If not found, this means an alias of one of the operand is dead. Add a
242 // new implicit operand.
243 if (!Found && AddIfNotFound) {
244 MI->addRegOperand(IncomingReg, true/*IsDef*/,true/*IsImp*/,false/*IsKill*/,
251 void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) {
252 // There is a now a proper use, forget about the last partial use.
253 PhysRegPartUse[Reg] = NULL;
255 // Turn previous partial def's into read/mod/write.
256 for (unsigned i = 0, e = PhysRegPartDef[Reg].size(); i != e; ++i) {
257 MachineInstr *Def = PhysRegPartDef[Reg][i];
258 // First one is just a def. This means the use is reading some undef bits.
260 Def->addRegOperand(Reg, false/*IsDef*/,true/*IsImp*/,true/*IsKill*/);
261 Def->addRegOperand(Reg, true/*IsDef*/,true/*IsImp*/);
263 PhysRegPartDef[Reg].clear();
265 // There was an earlier def of a super-register. Add implicit def to that MI.
268 // Add implicit def to A.
269 if (PhysRegInfo[Reg] && !PhysRegUsed[Reg]) {
270 MachineInstr *Def = PhysRegInfo[Reg];
271 if (!Def->findRegisterDefOperand(Reg))
272 Def->addRegOperand(Reg, true/*IsDef*/,true/*IsImp*/);
275 PhysRegInfo[Reg] = MI;
276 PhysRegUsed[Reg] = true;
278 for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg);
279 unsigned SubReg = *SubRegs; ++SubRegs) {
280 PhysRegInfo[SubReg] = MI;
281 PhysRegUsed[SubReg] = true;
284 // Remember the partial uses.
285 for (const unsigned *SuperRegs = RegInfo->getSuperRegisters(Reg);
286 unsigned SuperReg = *SuperRegs; ++SuperRegs)
287 PhysRegPartUse[SuperReg] = MI;
290 bool LiveVariables::HandlePhysRegKill(unsigned Reg, MachineInstr *RefMI,
291 SmallSet<unsigned, 4> &SubKills) {
292 for (const unsigned *SubRegs = RegInfo->getImmediateSubRegisters(Reg);
293 unsigned SubReg = *SubRegs; ++SubRegs) {
294 MachineInstr *LastRef = PhysRegInfo[SubReg];
295 if (LastRef != RefMI)
296 SubKills.insert(SubReg);
297 else if (!HandlePhysRegKill(SubReg, RefMI, SubKills))
298 SubKills.insert(SubReg);
301 if (*RegInfo->getImmediateSubRegisters(Reg) == 0) {
302 // No sub-registers, just check if reg is killed by RefMI.
303 if (PhysRegInfo[Reg] == RefMI)
305 } else if (SubKills.empty())
306 // None of the sub-registers are killed elsewhere...
311 void LiveVariables::addRegisterKills(unsigned Reg, MachineInstr *MI,
312 SmallSet<unsigned, 4> &SubKills) {
313 if (SubKills.count(Reg) == 0)
314 addRegisterKilled(Reg, MI, true);
316 for (const unsigned *SubRegs = RegInfo->getImmediateSubRegisters(Reg);
317 unsigned SubReg = *SubRegs; ++SubRegs)
318 addRegisterKills(SubReg, MI, SubKills);
322 bool LiveVariables::HandlePhysRegKill(unsigned Reg, MachineInstr *RefMI) {
323 SmallSet<unsigned, 4> SubKills;
324 if (HandlePhysRegKill(Reg, RefMI, SubKills)) {
325 addRegisterKilled(Reg, RefMI);
328 // Some sub-registers are killed by another MI.
329 for (const unsigned *SubRegs = RegInfo->getImmediateSubRegisters(Reg);
330 unsigned SubReg = *SubRegs; ++SubRegs)
331 addRegisterKills(SubReg, RefMI, SubKills);
336 void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI) {
337 // Does this kill a previous version of this register?
338 if (MachineInstr *LastRef = PhysRegInfo[Reg]) {
339 if (PhysRegUsed[Reg]) {
340 if (!HandlePhysRegKill(Reg, LastRef)) {
341 if (PhysRegPartUse[Reg])
342 addRegisterKilled(Reg, PhysRegPartUse[Reg], true);
344 } else if (PhysRegPartUse[Reg])
345 // Add implicit use / kill to last use of a sub-register.
346 addRegisterKilled(Reg, PhysRegPartUse[Reg], true);
348 addRegisterDead(Reg, LastRef);
351 for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg);
352 unsigned SubReg = *SubRegs; ++SubRegs) {
353 if (MachineInstr *LastRef = PhysRegInfo[SubReg]) {
354 if (PhysRegUsed[SubReg]) {
355 if (!HandlePhysRegKill(SubReg, LastRef)) {
356 if (PhysRegPartUse[SubReg])
357 addRegisterKilled(SubReg, PhysRegPartUse[SubReg], true);
359 //addRegisterKilled(SubReg, LastRef);
360 } else if (PhysRegPartUse[SubReg])
361 // Add implicit use / kill to last use of a sub-register.
362 addRegisterKilled(SubReg, PhysRegPartUse[SubReg], true);
364 addRegisterDead(SubReg, LastRef);
369 for (const unsigned *SuperRegs = RegInfo->getSuperRegisters(Reg);
370 unsigned SuperReg = *SuperRegs; ++SuperRegs) {
371 if (PhysRegInfo[SuperReg]) {
372 // The larger register is previously defined. Now a smaller part is
373 // being re-defined. Treat it as read/mod/write.
375 // AX = EAX<imp-use,kill>, EAX<imp-def>
376 MI->addRegOperand(SuperReg, false/*IsDef*/,true/*IsImp*/,true/*IsKill*/);
377 MI->addRegOperand(SuperReg, true/*IsDef*/,true/*IsImp*/);
378 PhysRegInfo[SuperReg] = MI;
379 PhysRegUsed[SuperReg] = false;
380 PhysRegPartUse[SuperReg] = NULL;
382 // Remember this partial def.
383 PhysRegPartDef[SuperReg].push_back(MI);
387 PhysRegInfo[Reg] = MI;
388 PhysRegUsed[Reg] = false;
389 PhysRegPartUse[Reg] = NULL;
390 for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg);
391 unsigned SubReg = *SubRegs; ++SubRegs) {
392 PhysRegInfo[SubReg] = MI;
393 PhysRegUsed[SubReg] = false;
394 PhysRegPartUse[SubReg] = NULL;
399 bool LiveVariables::runOnMachineFunction(MachineFunction &mf) {
401 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
402 RegInfo = MF->getTarget().getRegisterInfo();
403 assert(RegInfo && "Target doesn't have register information?");
405 ReservedRegisters = RegInfo->getReservedRegs(mf);
407 unsigned NumRegs = RegInfo->getNumRegs();
408 PhysRegInfo = new MachineInstr*[NumRegs];
409 PhysRegUsed = new bool[NumRegs];
410 PhysRegPartUse = new MachineInstr*[NumRegs];
411 PhysRegPartDef = new SmallVector<MachineInstr*,4>[NumRegs];
412 PHIVarInfo = new SmallVector<unsigned, 4>[MF->getNumBlockIDs()];
413 std::fill(PhysRegInfo, PhysRegInfo + NumRegs, (MachineInstr*)0);
414 std::fill(PhysRegUsed, PhysRegUsed + NumRegs, false);
415 std::fill(PhysRegPartUse, PhysRegPartUse + NumRegs, (MachineInstr*)0);
417 /// Get some space for a respectable number of registers...
418 VirtRegInfo.resize(64);
422 // Calculate live variable information in depth first order on the CFG of the
423 // function. This guarantees that we will see the definition of a virtual
424 // register before its uses due to dominance properties of SSA (except for PHI
425 // nodes, which are treated as a special case).
427 MachineBasicBlock *Entry = MF->begin();
428 SmallPtrSet<MachineBasicBlock*,16> Visited;
429 for (df_ext_iterator<MachineBasicBlock*, SmallPtrSet<MachineBasicBlock*,16> >
430 DFI = df_ext_begin(Entry, Visited), E = df_ext_end(Entry, Visited);
432 MachineBasicBlock *MBB = *DFI;
434 // Mark live-in registers as live-in.
435 for (MachineBasicBlock::const_livein_iterator II = MBB->livein_begin(),
436 EE = MBB->livein_end(); II != EE; ++II) {
437 assert(MRegisterInfo::isPhysicalRegister(*II) &&
438 "Cannot have a live-in virtual register!");
439 HandlePhysRegDef(*II, 0);
442 // Loop over all of the instructions, processing them.
443 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
445 MachineInstr *MI = I;
447 // Process all of the operands of the instruction...
448 unsigned NumOperandsToProcess = MI->getNumOperands();
450 // Unless it is a PHI node. In this case, ONLY process the DEF, not any
451 // of the uses. They will be handled in other basic blocks.
452 if (MI->getOpcode() == TargetInstrInfo::PHI)
453 NumOperandsToProcess = 1;
455 // Process all uses...
456 for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
457 MachineOperand &MO = MI->getOperand(i);
458 if (MO.isRegister() && MO.isUse() && MO.getReg()) {
459 if (MRegisterInfo::isVirtualRegister(MO.getReg())){
460 HandleVirtRegUse(getVarInfo(MO.getReg()), MBB, MI);
461 } else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
462 !ReservedRegisters[MO.getReg()]) {
463 HandlePhysRegUse(MO.getReg(), MI);
468 // Process all defs...
469 for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
470 MachineOperand &MO = MI->getOperand(i);
471 if (MO.isRegister() && MO.isDef() && MO.getReg()) {
472 if (MRegisterInfo::isVirtualRegister(MO.getReg())) {
473 VarInfo &VRInfo = getVarInfo(MO.getReg());
475 assert(VRInfo.DefInst == 0 && "Variable multiply defined!");
478 VRInfo.Kills.push_back(MI);
479 } else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
480 !ReservedRegisters[MO.getReg()]) {
481 HandlePhysRegDef(MO.getReg(), MI);
487 // Handle any virtual assignments from PHI nodes which might be at the
488 // bottom of this basic block. We check all of our successor blocks to see
489 // if they have PHI nodes, and if so, we simulate an assignment at the end
490 // of the current block.
491 if (!PHIVarInfo[MBB->getNumber()].empty()) {
492 SmallVector<unsigned, 4>& VarInfoVec = PHIVarInfo[MBB->getNumber()];
494 for (SmallVector<unsigned, 4>::iterator I = VarInfoVec.begin(),
495 E = VarInfoVec.end(); I != E; ++I) {
496 VarInfo& VRInfo = getVarInfo(*I);
497 assert(VRInfo.DefInst && "Register use before def (or no def)!");
499 // Only mark it alive only in the block we are representing.
500 MarkVirtRegAliveInBlock(VRInfo, MBB);
504 // Finally, if the last instruction in the block is a return, make sure to mark
505 // it as using all of the live-out values in the function.
506 if (!MBB->empty() && TII.isReturn(MBB->back().getOpcode())) {
507 MachineInstr *Ret = &MBB->back();
508 for (MachineFunction::liveout_iterator I = MF->liveout_begin(),
509 E = MF->liveout_end(); I != E; ++I) {
510 assert(MRegisterInfo::isPhysicalRegister(*I) &&
511 "Cannot have a live-in virtual register!");
512 HandlePhysRegUse(*I, Ret);
513 // Add live-out registers as implicit uses.
514 if (Ret->findRegisterUseOperandIdx(*I) == -1)
515 Ret->addRegOperand(*I, false, true);
519 // Loop over PhysRegInfo, killing any registers that are available at the
520 // end of the basic block. This also resets the PhysRegInfo map.
521 for (unsigned i = 0; i != NumRegs; ++i)
523 HandlePhysRegDef(i, 0);
525 // Clear some states between BB's. These are purely local information.
526 for (unsigned i = 0; i != NumRegs; ++i)
527 PhysRegPartDef[i].clear();
528 std::fill(PhysRegInfo, PhysRegInfo + NumRegs, (MachineInstr*)0);
529 std::fill(PhysRegUsed, PhysRegUsed + NumRegs, false);
530 std::fill(PhysRegPartUse, PhysRegPartUse + NumRegs, (MachineInstr*)0);
533 // Convert and transfer the dead / killed information we have gathered into
534 // VirtRegInfo onto MI's.
536 for (unsigned i = 0, e1 = VirtRegInfo.size(); i != e1; ++i)
537 for (unsigned j = 0, e2 = VirtRegInfo[i].Kills.size(); j != e2; ++j) {
538 if (VirtRegInfo[i].Kills[j] == VirtRegInfo[i].DefInst)
539 addRegisterDead(i + MRegisterInfo::FirstVirtualRegister,
540 VirtRegInfo[i].Kills[j]);
542 addRegisterKilled(i + MRegisterInfo::FirstVirtualRegister,
543 VirtRegInfo[i].Kills[j]);
546 // Check to make sure there are no unreachable blocks in the MC CFG for the
547 // function. If so, it is due to a bug in the instruction selector or some
548 // other part of the code generator if this happens.
550 for(MachineFunction::iterator i = MF->begin(), e = MF->end(); i != e; ++i)
551 assert(Visited.count(&*i) != 0 && "unreachable basic block found");
554 delete[] PhysRegInfo;
555 delete[] PhysRegUsed;
556 delete[] PhysRegPartUse;
557 delete[] PhysRegPartDef;
563 /// instructionChanged - When the address of an instruction changes, this
564 /// method should be called so that live variables can update its internal
565 /// data structures. This removes the records for OldMI, transfering them to
566 /// the records for NewMI.
567 void LiveVariables::instructionChanged(MachineInstr *OldMI,
568 MachineInstr *NewMI) {
569 // If the instruction defines any virtual registers, update the VarInfo,
570 // kill and dead information for the instruction.
571 for (unsigned i = 0, e = OldMI->getNumOperands(); i != e; ++i) {
572 MachineOperand &MO = OldMI->getOperand(i);
573 if (MO.isRegister() && MO.getReg() &&
574 MRegisterInfo::isVirtualRegister(MO.getReg())) {
575 unsigned Reg = MO.getReg();
576 VarInfo &VI = getVarInfo(Reg);
580 addVirtualRegisterDead(Reg, NewMI);
582 // Update the defining instruction.
583 if (VI.DefInst == OldMI)
589 addVirtualRegisterKilled(Reg, NewMI);
591 // If this is a kill of the value, update the VI kills list.
592 if (VI.removeKill(OldMI))
593 VI.Kills.push_back(NewMI); // Yes, there was a kill of it
599 /// removeVirtualRegistersKilled - Remove all killed info for the specified
601 void LiveVariables::removeVirtualRegistersKilled(MachineInstr *MI) {
602 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
603 MachineOperand &MO = MI->getOperand(i);
604 if (MO.isReg() && MO.isKill()) {
606 unsigned Reg = MO.getReg();
607 if (MRegisterInfo::isVirtualRegister(Reg)) {
608 bool removed = getVarInfo(Reg).removeKill(MI);
609 assert(removed && "kill not in register's VarInfo?");
615 /// removeVirtualRegistersDead - Remove all of the dead registers for the
616 /// specified instruction from the live variable information.
617 void LiveVariables::removeVirtualRegistersDead(MachineInstr *MI) {
618 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
619 MachineOperand &MO = MI->getOperand(i);
620 if (MO.isReg() && MO.isDead()) {
622 unsigned Reg = MO.getReg();
623 if (MRegisterInfo::isVirtualRegister(Reg)) {
624 bool removed = getVarInfo(Reg).removeKill(MI);
625 assert(removed && "kill not in register's VarInfo?");
631 /// analyzePHINodes - Gather information about the PHI nodes in here. In
632 /// particular, we want to map the variable information of a virtual
633 /// register which is used in a PHI node. We map that to the BB the vreg is
636 void LiveVariables::analyzePHINodes(const MachineFunction& Fn) {
637 for (MachineFunction::const_iterator I = Fn.begin(), E = Fn.end();
639 for (MachineBasicBlock::const_iterator BBI = I->begin(), BBE = I->end();
640 BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI)
641 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
642 PHIVarInfo[BBI->getOperand(i + 1).getMachineBasicBlock()->getNumber()].
643 push_back(BBI->getOperand(i).getReg());